diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux')
5 files changed, 5641 insertions, 5637 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 6f639a911..5aca0e128 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,132 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.533144 # Number of seconds simulated -sim_ticks 2533143973500 # Number of ticks simulated -final_tick 2533143973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.533141 # Number of seconds simulated +sim_ticks 2533140518500 # Number of ticks simulated +final_tick 2533140518500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55009 # Simulator instruction rate (inst/s) -host_op_rate 70781 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2310577470 # Simulator tick rate (ticks/s) -host_mem_usage 405260 # Number of bytes of host memory used -host_seconds 1096.33 # Real time elapsed on the host -sim_insts 60307579 # Number of instructions simulated -sim_ops 77599125 # Number of ops (including micro ops) simulated +host_inst_rate 42664 # Simulator instruction rate (inst/s) +host_op_rate 54897 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1792038006 # Simulator tick rate (ticks/s) +host_mem_usage 435912 # Number of bytes of host memory used +host_seconds 1413.55 # Real time elapsed on the host +sim_insts 60307702 # Number of instructions simulated +sim_ops 77599241 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 796608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093392 # Number of bytes read from this memory -system.physmem.bytes_read::total 129430480 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 796608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 796608 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3782336 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 796032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093328 # Number of bytes read from this memory +system.physmem.bytes_read::total 129429840 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 796032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796032 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3782784 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6798408 # Number of bytes written to this memory +system.physmem.bytes_written::total 6798856 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 42 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12447 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142118 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096817 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59099 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12438 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142117 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096807 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59106 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813117 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47189447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1061 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314474 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3589765 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51094798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314474 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314474 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1493139 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190644 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2683783 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1493139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47189447 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1061 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314474 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4780409 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53778581 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096817 # Total number of read requests seen -system.physmem.writeReqs 813117 # Total number of write requests seen -system.physmem.cpureqs 218351 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966196288 # Total number of bytes read from memory -system.physmem.bytesWritten 52039488 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129430480 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6798408 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 227 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4679 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943948 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943440 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943386 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 944197 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943985 # Track reads on a per bank basis +system.physmem.num_writes::total 813124 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47189512 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314247 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3589745 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51094615 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314247 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314247 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493318 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190645 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2683963 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493318 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47189512 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314247 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4780390 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53778578 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096807 # Total number of read requests seen +system.physmem.writeReqs 813124 # Total number of write requests seen +system.physmem.cpureqs 218344 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966195648 # Total number of bytes read from memory +system.physmem.bytesWritten 52039936 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129429840 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6798856 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 294 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4675 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943944 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943437 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943387 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 944192 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943982 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 943146 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943274 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943868 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943807 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943277 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943871 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943786 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 943302 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943206 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943616 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943708 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943088 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 942997 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943622 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50835 # Track writes on a per bank basis +system.physmem.perBankRdReqs::10 943229 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 943609 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943686 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943077 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 942973 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943615 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50829 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 50409 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50435 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51153 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50912 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50181 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50279 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50860 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51368 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50900 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50799 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51241 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50710 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50623 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51228 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50437 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51152 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50182 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50284 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50862 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51365 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50905 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50801 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51190 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51240 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50707 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50625 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51227 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2238337 # Number of times wr buffer was full causing retry -system.physmem.totGap 2533142848500 # Total gap between requests +system.physmem.numWrRetry 32502 # Number of times wr buffer was full causing retry +system.physmem.totGap 2533139407500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154573 # Categorize read packet sizes +system.physmem.readPktSize::6 154563 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754018 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59099 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1040033 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 981185 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 950276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3550309 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2676403 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2688030 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2649604 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60807 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59178 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 108698 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 157635 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 108246 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 16712 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16586 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 21915 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 10857 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59106 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1040017 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 981099 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 950174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3550467 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2676456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2688055 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2649570 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60697 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59181 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 108712 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 157594 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 108279 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 16749 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16591 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 12584 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -139,15 +139,15 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2788 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 2815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2837 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see @@ -160,25 +160,25 @@ system.physmem.wrQLenPdf::17 35353 # Wh system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32776 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32722 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 32676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32584 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32565 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 32538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32521 # What write queue length does an incoming req see -system.physmem.totQLat 393251142750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 485645877750 # Sum of mem lat for all requests -system.physmem.totBusLat 75482950000 # Total cycles spent in databus access -system.physmem.totBankLat 16911785000 # Total cycles spent in bank access -system.physmem.avgQLat 26049.00 # Average queueing delay per request -system.physmem.avgBankLat 1120.24 # Average bank access latency per request +system.physmem.wrQLenPdf::31 32516 # What write queue length does an incoming req see +system.physmem.totQLat 393185279250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 485577085500 # Sum of mem lat for all requests +system.physmem.totBusLat 75482565000 # Total cycles spent in databus access +system.physmem.totBankLat 16909241250 # Total cycles spent in bank access +system.physmem.avgQLat 26044.77 # Average queueing delay per request +system.physmem.avgBankLat 1120.08 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32169.24 # Average memory access latency +system.physmem.avgMemAccLat 32164.85 # Average memory access latency system.physmem.avgRdBW 381.42 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s @@ -186,12 +186,12 @@ system.physmem.avgConsumedWrBW 2.68 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.14 # Data bus utilization in percentage system.physmem.avgRdQLen 0.19 # Average read queue length over time -system.physmem.avgWrQLen 9.55 # Average write queue length over time -system.physmem.readRowHits 15020272 # Number of row buffer hits during reads -system.physmem.writeRowHits 793090 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.54 # Row buffer hit rate for writes -system.physmem.avgGap 159217.68 # Average gap between requests +system.physmem.avgWrQLen 11.32 # Average write queue length over time +system.physmem.readRowHits 15020284 # Number of row buffer hits during reads +system.physmem.writeRowHits 793162 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.50 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 97.55 # Row buffer hit rate for writes +system.physmem.avgGap 159217.50 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -210,20 +210,20 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu.branchPred.lookups 14675749 # Number of BP lookups -system.cpu.branchPred.condPredicted 11761615 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 705306 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9809113 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7951342 # Number of BTB hits +system.cpu.branchPred.lookups 14656582 # Number of BP lookups +system.cpu.branchPred.condPredicted 11744816 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 702966 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9741710 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7933580 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.060765 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1398937 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72620 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.439296 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1398798 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72309 # Number of incorrect RAS predictions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 14987411 # DTB read hits +system.cpu.checker.dtb.read_hits 14987438 # DTB read hits system.cpu.checker.dtb.read_misses 7302 # DTB read misses -system.cpu.checker.dtb.write_hits 11227746 # DTB write hits +system.cpu.checker.dtb.write_hits 11227743 # DTB write hits system.cpu.checker.dtb.write_misses 2189 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -234,13 +234,13 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 14994713 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11229935 # DTB write accesses +system.cpu.checker.dtb.read_accesses 14994740 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11229932 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26215157 # DTB hits +system.cpu.checker.dtb.hits 26215181 # DTB hits system.cpu.checker.dtb.misses 9491 # DTB misses -system.cpu.checker.dtb.accesses 26224648 # DTB accesses -system.cpu.checker.itb.inst_hits 61481576 # ITB inst hits +system.cpu.checker.dtb.accesses 26224672 # DTB accesses +system.cpu.checker.itb.inst_hits 61481703 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -257,36 +257,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61486047 # ITB inst accesses -system.cpu.checker.itb.hits 61481576 # DTB hits +system.cpu.checker.itb.inst_accesses 61486174 # ITB inst accesses +system.cpu.checker.itb.hits 61481703 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61486047 # DTB accesses -system.cpu.checker.numCycles 77884929 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61486174 # DTB accesses +system.cpu.checker.numCycles 77885049 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51399217 # DTB read hits -system.cpu.dtb.read_misses 64403 # DTB read misses -system.cpu.dtb.write_hits 11701345 # DTB write hits -system.cpu.dtb.write_misses 15902 # DTB write misses +system.cpu.dtb.read_hits 51396633 # DTB read hits +system.cpu.dtb.read_misses 64067 # DTB read misses +system.cpu.dtb.write_hits 11699653 # DTB write hits +system.cpu.dtb.write_misses 15746 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 6540 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2566 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 409 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 6549 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2477 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 410 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1299 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51463620 # DTB read accesses -system.cpu.dtb.write_accesses 11717247 # DTB write accesses +system.cpu.dtb.perms_faults 1368 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51460700 # DTB read accesses +system.cpu.dtb.write_accesses 11715399 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63100562 # DTB hits -system.cpu.dtb.misses 80305 # DTB misses -system.cpu.dtb.accesses 63180867 # DTB accesses -system.cpu.itb.inst_hits 12332677 # ITB inst hits -system.cpu.itb.inst_misses 11271 # ITB inst misses +system.cpu.dtb.hits 63096286 # DTB hits +system.cpu.dtb.misses 79813 # DTB misses +system.cpu.dtb.accesses 63176099 # DTB accesses +system.cpu.itb.inst_hits 12325480 # ITB inst hits +system.cpu.itb.inst_misses 11172 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -295,113 +295,113 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 4946 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 4964 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2981 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2959 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 12343948 # ITB inst accesses -system.cpu.itb.hits 12332677 # DTB hits -system.cpu.itb.misses 11271 # DTB misses -system.cpu.itb.accesses 12343948 # DTB accesses -system.cpu.numCycles 471840254 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 12336652 # ITB inst accesses +system.cpu.itb.hits 12325480 # DTB hits +system.cpu.itb.misses 11172 # DTB misses +system.cpu.itb.accesses 12336652 # DTB accesses +system.cpu.numCycles 471810648 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30570540 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 96039987 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14675749 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9350279 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21160212 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5300332 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 123049 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 95587623 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2575 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87979 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 195754 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 322 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 12329197 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 900896 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5353 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151365911 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.785063 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.150272 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30565457 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 95962553 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14656582 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9332378 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21150277 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5290628 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 121780 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 95575206 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2486 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87600 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 195549 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 302 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12322026 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 900670 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5254 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 151331210 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.784596 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.149323 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130221030 86.03% 86.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1303083 0.86% 86.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1712964 1.13% 88.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2496255 1.65% 89.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2215475 1.46% 91.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1108052 0.73% 91.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2757455 1.82% 93.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 745629 0.49% 94.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8805968 5.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130196252 86.03% 86.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1300820 0.86% 86.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1711466 1.13% 88.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2496471 1.65% 89.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2227799 1.47% 91.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1107368 0.73% 91.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2755124 1.82% 93.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 745381 0.49% 94.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8790529 5.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151365911 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031103 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.203543 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32532272 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95215917 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19186051 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 962874 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3468797 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1957839 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171569 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 112632707 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 566700 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3468797 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34474935 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36706470 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52522148 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18150584 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6042977 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 106114460 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20538 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1004739 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4062916 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 612 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 110534596 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 485505463 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 485414558 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90905 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78389874 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32144721 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830610 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 737120 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12168217 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20326621 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13518825 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1978093 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2487494 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97939378 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983579 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124329035 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167924 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21751378 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 57069924 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501194 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151365911 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.821381 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.534880 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 151331210 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031065 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.203392 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32520642 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95204800 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19177861 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 964369 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3463538 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1955195 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171536 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 112591879 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 568560 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3463538 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34463537 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36710079 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52505351 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18142460 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6046245 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 106079174 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20496 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1005117 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4065592 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 550 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 110464487 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 485375349 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 485284525 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90824 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78390007 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 32074479 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830001 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 736568 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12176268 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20326431 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13516174 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1981962 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2490949 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97882200 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983364 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124293058 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 166652 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21701894 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 56956786 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 500965 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151331210 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.821331 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.534912 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 107121434 70.77% 70.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13552589 8.95% 79.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7069165 4.67% 84.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5942277 3.93% 88.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12602111 8.33% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2786608 1.84% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1699306 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 465403 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 127018 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 107106602 70.78% 70.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13535056 8.94% 79.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7081946 4.68% 84.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5928653 3.92% 88.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12592468 8.32% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2797891 1.85% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1698330 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 463268 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 126996 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151365911 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151331210 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 60927 0.69% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 61058 0.69% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 2 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available @@ -430,383 +430,383 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8365559 94.64% 95.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 412870 4.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8365937 94.65% 95.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 412109 4.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58631029 47.16% 47.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93272 0.08% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 18 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 18 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52917261 42.56% 90.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12321634 9.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58600875 47.15% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93259 0.08% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 16 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52914481 42.57% 90.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12318607 9.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124329035 # Type of FU issued -system.cpu.iq.rate 0.263498 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8839358 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071096 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 409088132 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 121690697 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85968255 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23084 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12548 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10294 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132792486 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12241 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 623354 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124293058 # Type of FU issued +system.cpu.iq.rate 0.263438 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8839106 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071115 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 408979270 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 121583785 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85924901 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23271 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12514 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10314 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 132756155 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12343 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 622462 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4672096 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6462 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30066 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1786745 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4671879 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6237 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29961 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1784095 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107738 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 893837 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107744 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 893407 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3468797 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27950970 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 433267 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100144689 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 200366 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20326621 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13518825 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1410950 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 112625 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3575 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30066 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 350763 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 269062 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 619825 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121548947 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52086338 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2780088 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3463538 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27955301 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 434033 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100086993 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 200996 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20326431 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13516174 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1411213 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113661 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3507 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29961 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 349347 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 268482 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 617829 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121503786 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52083788 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2789272 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221732 # number of nop insts executed -system.cpu.iew.exec_refs 64299340 # number of memory reference insts executed -system.cpu.iew.exec_branches 11561583 # Number of branches executed -system.cpu.iew.exec_stores 12213002 # Number of stores executed -system.cpu.iew.exec_rate 0.257606 # Inst execution rate -system.cpu.iew.wb_sent 120388158 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85978549 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47221894 # num instructions producing a value -system.cpu.iew.wb_consumers 88170402 # num instructions consuming a value +system.cpu.iew.exec_nop 221429 # number of nop insts executed +system.cpu.iew.exec_refs 64295144 # number of memory reference insts executed +system.cpu.iew.exec_branches 11545908 # Number of branches executed +system.cpu.iew.exec_stores 12211356 # Number of stores executed +system.cpu.iew.exec_rate 0.257527 # Inst execution rate +system.cpu.iew.wb_sent 120344767 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85935215 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47220023 # num instructions producing a value +system.cpu.iew.wb_consumers 88179927 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182220 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535575 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182139 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535496 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 21486542 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482385 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 536246 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147897114 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.525700 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.515001 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 21428892 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482399 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 533951 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147867672 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.525805 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.514985 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120445936 81.44% 81.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13320013 9.01% 90.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3904517 2.64% 93.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2120442 1.43% 94.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1947230 1.32% 95.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 967442 0.65% 96.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1598856 1.08% 97.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 701557 0.47% 98.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2891121 1.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120409023 81.43% 81.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13327348 9.01% 90.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3906728 2.64% 93.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2120462 1.43% 94.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1944541 1.32% 95.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 966495 0.65% 96.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1605335 1.09% 97.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 697137 0.47% 98.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2890603 1.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147897114 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60457960 # Number of instructions committed -system.cpu.commit.committedOps 77749506 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 147867672 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60458083 # Number of instructions committed +system.cpu.commit.committedOps 77749622 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386605 # Number of memory references committed -system.cpu.commit.loads 15654525 # Number of loads committed -system.cpu.commit.membars 403599 # Number of memory barriers committed -system.cpu.commit.branches 9961316 # Number of branches committed +system.cpu.commit.refs 27386631 # Number of memory references committed +system.cpu.commit.loads 15654552 # Number of loads committed +system.cpu.commit.membars 403601 # Number of memory barriers committed +system.cpu.commit.branches 9961338 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68854760 # Number of committed integer instructions. -system.cpu.commit.function_calls 991257 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2891121 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68854854 # Number of committed integer instructions. +system.cpu.commit.function_calls 991262 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2890603 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 242393474 # The number of ROB reads -system.cpu.rob.rob_writes 202038068 # The number of ROB writes -system.cpu.timesIdled 1769308 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320474343 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4594364653 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60307579 # Number of Instructions Simulated -system.cpu.committedOps 77599125 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60307579 # Number of Instructions Simulated -system.cpu.cpi 7.823896 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.823896 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127814 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.127814 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 550318453 # number of integer regfile reads -system.cpu.int_regfile_writes 88458214 # number of integer regfile writes -system.cpu.fp_regfile_reads 8290 # number of floating regfile reads -system.cpu.fp_regfile_writes 2932 # number of floating regfile writes -system.cpu.misc_regfile_reads 30125052 # number of misc regfile reads -system.cpu.misc_regfile_writes 831890 # number of misc regfile writes -system.cpu.icache.replacements 979629 # number of replacements -system.cpu.icache.tagsinuse 511.615707 # Cycle average of tags in use -system.cpu.icache.total_refs 11269534 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 980141 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11.497870 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 242306963 # The number of ROB reads +system.cpu.rob.rob_writes 201917005 # The number of ROB writes +system.cpu.timesIdled 1770758 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320479438 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4594387345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60307702 # Number of Instructions Simulated +system.cpu.committedOps 77599241 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60307702 # Number of Instructions Simulated +system.cpu.cpi 7.823390 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.823390 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127822 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127822 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 550141266 # number of integer regfile reads +system.cpu.int_regfile_writes 88418140 # number of integer regfile writes +system.cpu.fp_regfile_reads 8398 # number of floating regfile reads +system.cpu.fp_regfile_writes 2928 # number of floating regfile writes +system.cpu.misc_regfile_reads 30126321 # number of misc regfile reads +system.cpu.misc_regfile_writes 831893 # number of misc regfile writes +system.cpu.icache.replacements 979850 # number of replacements +system.cpu.icache.tagsinuse 511.615737 # Cycle average of tags in use +system.cpu.icache.total_refs 11261998 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 980362 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11.487591 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 6426355000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.615707 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 511.615737 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.999249 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.999249 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11269534 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11269534 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11269534 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11269534 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11269534 # number of overall hits -system.cpu.icache.overall_hits::total 11269534 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1059538 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1059538 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1059538 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1059538 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1059538 # number of overall misses -system.cpu.icache.overall_misses::total 1059538 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13993400496 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13993400496 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13993400496 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13993400496 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13993400496 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13993400496 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12329072 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12329072 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12329072 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12329072 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12329072 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12329072 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085938 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.085938 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.085938 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.085938 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.085938 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.085938 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13207.077515 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13207.077515 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13207.077515 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13207.077515 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13207.077515 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13207.077515 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4855 # number of cycles access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 11261998 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11261998 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11261998 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11261998 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11261998 # number of overall hits +system.cpu.icache.overall_hits::total 11261998 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1059902 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1059902 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1059902 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1059902 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1059902 # number of overall misses +system.cpu.icache.overall_misses::total 1059902 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13993800493 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13993800493 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13993800493 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13993800493 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13993800493 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13993800493 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12321900 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12321900 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12321900 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12321900 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12321900 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12321900 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086018 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.086018 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.086018 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.086018 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.086018 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.086018 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13202.919226 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13202.919226 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13202.919226 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13202.919226 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13202.919226 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13202.919226 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4527 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 305 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 299 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 15.918033 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 15.140468 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79361 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79361 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79361 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79361 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79361 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79361 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980177 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 980177 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 980177 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 980177 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 980177 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 980177 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11379164996 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11379164996 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11379164996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11379164996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11379164996 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11379164996 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7553500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7553500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7553500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 7553500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079501 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079501 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079501 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.079501 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079501 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.079501 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11609.296072 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11609.296072 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11609.296072 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11609.296072 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11609.296072 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11609.296072 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79506 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79506 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79506 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79506 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79506 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79506 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980396 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 980396 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 980396 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 980396 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 980396 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 980396 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11379943495 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11379943495 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11379943495 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11379943495 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11379943495 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11379943495 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7555000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7555000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7555000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 7555000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079565 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079565 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079565 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.079565 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079565 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.079565 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11607.496864 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11607.496864 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11607.496864 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11607.496864 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11607.496864 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11607.496864 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 64344 # number of replacements -system.cpu.l2cache.tagsinuse 51347.743422 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1885451 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129735 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 14.533094 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2498197459500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 36929.519444 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 26.551079 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000348 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 8159.886035 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6231.786516 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.563500 # Average percentage of cache occupancy +system.cpu.l2cache.replacements 64334 # number of replacements +system.cpu.l2cache.tagsinuse 51346.876619 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1884630 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 129728 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 14.527550 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2498196259500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 36934.415864 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 26.547842 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.003890 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 8157.503084 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6228.405939 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.563574 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000405 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.124510 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.095090 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.783504 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52475 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10450 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 966729 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 387264 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1416918 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 607832 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 607832 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 42 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 42 # number of UpgradeReq hits +system.cpu.l2cache.occ_percent::cpu.inst 0.124474 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.095038 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.783491 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52007 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10206 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 966908 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 387081 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1416202 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 607769 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 607769 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 39 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 39 # number of UpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 11 # number of SCUpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::total 11 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 112902 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 112902 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 52475 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 10450 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 966729 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 500166 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1529820 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 52475 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 10450 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 966729 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 500166 # number of overall hits -system.cpu.l2cache.overall_hits::total 1529820 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 42 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12340 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10707 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 23091 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2921 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2921 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_hits::cpu.data 112939 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 112939 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 52007 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 10206 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 966908 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 500020 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1529141 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 52007 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 10206 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 966908 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 500020 # number of overall hits +system.cpu.l2cache.overall_hits::total 1529141 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 41 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12331 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 10709 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 23084 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2919 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2919 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133192 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133192 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 42 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12340 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143899 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 156283 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 42 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12340 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143899 # number of overall misses -system.cpu.l2cache.overall_misses::total 156283 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3043500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 118000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 696478000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 634908499 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1334547999 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 523500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 523500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6738135500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6738135500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3043500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 118000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 696478000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7373043999 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8072683499 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3043500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 118000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 696478000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7373043999 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8072683499 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52517 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10452 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 979069 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 397971 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1440009 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 607832 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 607832 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2963 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2963 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 133186 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133186 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 41 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 12331 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143895 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 156270 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 41 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 12331 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143895 # number of overall misses +system.cpu.l2cache.overall_misses::total 156270 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2874000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 187000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 694978000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 630766499 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1328805499 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 455500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 455500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6732631500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6732631500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2874000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 187000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 694978000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7363397999 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8061436999 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2874000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 187000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 694978000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7363397999 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8061436999 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52048 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10209 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 979239 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 397790 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1439286 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 607769 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 607769 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2958 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2958 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 14 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 14 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246094 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246094 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52517 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 10452 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 979069 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 644065 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1686103 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52517 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 10452 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 979069 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 644065 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1686103 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000800 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000191 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012604 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026904 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016035 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985825 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985825 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246125 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246125 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52048 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 10209 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 979239 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 643915 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1685411 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52048 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 10209 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 979239 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 643915 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1685411 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000788 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000294 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012592 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026921 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.016039 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986815 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986815 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.214286 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.214286 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541224 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.541224 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000800 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000191 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012604 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.223423 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.092689 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000800 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000191 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012604 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.223423 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.092689 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 72464.285714 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 59000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56440.680713 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59298.449519 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 57795.158243 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 179.219445 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 179.219445 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50589.641270 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50589.641270 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 72464.285714 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56440.680713 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51237.631943 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51654.265013 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 72464.285714 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56440.680713 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51237.631943 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51654.265013 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541132 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.541132 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000788 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000294 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012592 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.223469 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.092719 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000788 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000294 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012592 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.223469 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.092719 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 70097.560976 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 62333.333333 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56360.230314 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58900.597535 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 57563.918688 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 156.046591 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 156.046591 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50550.594657 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50550.594657 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 70097.560976 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 62333.333333 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56360.230314 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51172.021259 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51586.593710 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 70097.560976 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 62333.333333 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56360.230314 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51172.021259 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51586.593710 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -815,109 +815,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59099 # number of writebacks -system.cpu.l2cache.writebacks::total 59099 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 59106 # number of writebacks +system.cpu.l2cache.writebacks::total 59106 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 74 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 42 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12328 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10645 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 23017 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2921 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2921 # number of UpgradeReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 41 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12319 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10648 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 23011 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2919 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2919 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133192 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133192 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 42 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12328 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143837 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 156209 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 42 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12328 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143837 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 156209 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2519791 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 93251 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 542440021 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 499891739 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1044944802 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29212921 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29212921 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133186 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133186 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 41 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12319 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143834 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 156197 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 41 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12319 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143834 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 156197 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2360290 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 149502 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 541016289 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 495761741 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1039287822 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29192919 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29192919 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5078126850 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5078126850 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2519791 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 93251 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 542440021 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5578018589 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6123071652 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2519791 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 93251 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 542440021 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5578018589 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6123071652 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5079330 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002548267 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007627597 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26903237989 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26903237989 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5079330 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193905786256 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193910865586 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000800 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012592 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026748 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015984 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985825 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985825 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5072671631 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5072671631 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2360290 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 149502 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 541016289 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5568433372 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6111959453 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2360290 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 149502 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 541016289 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5568433372 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6111959453 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5080830 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002461767 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007542597 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26898020017 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26898020017 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5080830 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193900481784 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193905562614 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000788 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000294 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012580 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026768 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015988 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986815 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986815 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.214286 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.214286 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541224 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541224 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000800 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012592 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223327 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.092645 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000800 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012592 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223327 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.092645 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 59995.023810 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44000.650633 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46960.238516 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45398.827041 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541132 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541132 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000788 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000294 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012580 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223374 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092676 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000788 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000294 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012580 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223374 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092676 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 57568.048780 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 49834 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43917.224531 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46559.141717 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45164.826474 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38126.365322 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38126.365322 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 59995.023810 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44000.650633 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38780.137162 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39197.944113 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 59995.023810 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44000.650633 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38780.137162 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39197.944113 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38087.123504 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38087.123504 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 57568.048780 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 49834 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43917.224531 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38714.305185 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39129.813332 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 57568.048780 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 49834 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43917.224531 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38714.305185 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39129.813332 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -927,161 +927,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643553 # number of replacements +system.cpu.dcache.replacements 643403 # number of replacements system.cpu.dcache.tagsinuse 511.992821 # Cycle average of tags in use -system.cpu.dcache.total_refs 21507678 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 644065 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.393645 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 21507300 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 643915 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.400837 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 42249000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.992821 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13754193 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13754193 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7259605 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7259605 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 243146 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 243146 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247602 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247602 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21013798 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21013798 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21013798 # number of overall hits -system.cpu.dcache.overall_hits::total 21013798 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 737832 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 737832 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2962746 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2962746 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13508 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13508 # number of LoadLockedReq misses +system.cpu.dcache.ReadReq_hits::cpu.data 13753934 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13753934 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7259500 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7259500 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 243166 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 243166 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247603 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247603 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21013434 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21013434 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21013434 # number of overall hits +system.cpu.dcache.overall_hits::total 21013434 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 737092 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 737092 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2962848 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2962848 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13493 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13493 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 14 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 14 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3700578 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3700578 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3700578 # number of overall misses -system.cpu.dcache.overall_misses::total 3700578 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9800700500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9800700500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 104414938731 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 104414938731 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180553500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 180553500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 3699940 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3699940 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3699940 # number of overall misses +system.cpu.dcache.overall_misses::total 3699940 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9782888500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9782888500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 104355801234 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 104355801234 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 179982000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 179982000 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 218000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 218000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 114215639231 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 114215639231 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 114215639231 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 114215639231 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14492025 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14492025 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222351 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222351 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256654 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256654 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247616 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247616 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24714376 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24714376 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24714376 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24714376 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050913 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050913 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289830 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289830 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052631 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052631 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 114138689734 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 114138689734 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 114138689734 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 114138689734 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14491026 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14491026 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222348 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222348 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256659 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256659 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247617 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247617 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24713374 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24713374 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24713374 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24713374 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050865 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050865 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289840 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289840 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052572 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052572 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000057 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000057 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149734 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149734 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149734 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149734 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13283.105775 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13283.105775 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35242.622463 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35242.622463 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13366.412496 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13366.412496 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.149714 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149714 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149714 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149714 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13272.276052 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13272.276052 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35221.449509 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35221.449509 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13338.916475 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13338.916475 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15571.428571 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15571.428571 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30864.270185 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30864.270185 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30864.270185 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30864.270185 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29973 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 17225 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2670 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 252 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.225843 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 68.353175 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30848.794773 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30848.794773 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30848.794773 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30848.794773 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29383 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 15931 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2645 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 250 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.108885 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 63.724000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607832 # number of writebacks -system.cpu.dcache.writebacks::total 607832 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351946 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 351946 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713780 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2713780 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1332 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1332 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3065726 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3065726 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3065726 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3065726 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385886 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385886 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248966 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248966 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12176 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12176 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 607769 # number of writebacks +system.cpu.dcache.writebacks::total 607769 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351375 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 351375 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713851 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2713851 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1334 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1334 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3065226 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3065226 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3065226 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3065226 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385717 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385717 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248997 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248997 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12159 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12159 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 14 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634852 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634852 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634852 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634852 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4812474000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4812474000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8188067914 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8188067914 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141180000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141180000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 634714 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634714 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634714 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634714 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4806820000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4806820000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8183010414 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8183010414 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 140641000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 140641000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 190000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 190000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13000541914 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13000541914 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13000541914 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13000541914 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395833000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395833000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36742502511 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36742502511 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219138335511 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 219138335511 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026627 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026627 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024355 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024355 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047441 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047441 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12989830414 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12989830414 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12989830414 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12989830414 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395636000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395636000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36713909190 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36713909190 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219109545190 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 219109545190 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026618 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026618 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024358 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024358 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047374 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047374 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000057 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025688 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025688 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025688 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025688 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12471.232437 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12471.232437 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32888.297655 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32888.297655 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11594.940867 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11594.940867 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025683 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025683 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025683 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025683 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12462.038230 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12462.038230 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32863.891589 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32863.891589 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11566.822930 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11566.822930 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13571.428571 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13571.428571 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20478.067194 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20478.067194 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20478.067194 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20478.067194 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20465.643446 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20465.643446 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20465.643446 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20465.643446 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1103,16 +1103,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229610797601 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1229610797601 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229610797601 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1229610797601 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229542911844 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1229542911844 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229542911844 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1229542911844 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83041 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83045 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 5e12f3369..ee857cd58 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,152 +1,152 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.102940 # Number of seconds simulated -sim_ticks 1102940172000 # Number of ticks simulated -final_tick 1102940172000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.102937 # Number of seconds simulated +sim_ticks 1102936899000 # Number of ticks simulated +final_tick 1102936899000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65652 # Simulator instruction rate (inst/s) -host_op_rate 84510 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1175755462 # Simulator tick rate (ticks/s) -host_mem_usage 411412 # Number of bytes of host memory used -host_seconds 938.07 # Real time elapsed on the host -sim_insts 61586245 # Number of instructions simulated -sim_ops 79276446 # Number of ops (including micro ops) simulated +host_inst_rate 56405 # Simulator instruction rate (inst/s) +host_op_rate 72609 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1010130266 # Simulator tick rate (ticks/s) +host_mem_usage 440004 # Number of bytes of host memory used +host_seconds 1091.88 # Real time elapsed on the host +sim_insts 61587196 # Number of instructions simulated +sim_ops 79280303 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 409472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4368500 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 408960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4359540 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 1088 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 405632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5247536 # Number of bytes read from this memory -system.physmem.bytes_read::total 59192100 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 409472 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 405632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 815104 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4269568 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 406528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5228208 # Number of bytes read from this memory +system.physmem.bytes_read::total 59164324 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 408960 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 406528 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 815488 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4242368 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7296912 # Number of bytes written to this memory +system.physmem.bytes_written::total 7269712 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6398 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68330 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6390 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68190 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 17 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6338 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82019 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6257967 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66712 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6352 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 81717 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6257533 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66287 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823548 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 44208004 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 290 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 371255 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3960777 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 823123 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 44208136 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 232 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 370792 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3952665 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 986 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 58 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 367773 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4757770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53667553 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 371255 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 367773 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 739028 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3871079 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 368587 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4740260 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53642528 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 370792 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 368587 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 739379 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3846429 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 15413 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2729381 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6615873 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3871079 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 44208004 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 290 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 371255 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3976190 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2729389 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6591231 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3846429 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 44208136 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 232 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 370792 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3968078 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 986 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 58 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 367773 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7487151 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 60283426 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6257967 # Total number of read requests seen -system.physmem.writeReqs 823548 # Total number of write requests seen -system.physmem.cpureqs 242288 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 400509888 # Total number of bytes read from memory -system.physmem.bytesWritten 52707072 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 59192100 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7296912 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 121 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 12562 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 391387 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 391216 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 390896 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 391623 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 391542 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 390911 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 390957 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 391661 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 391404 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 390709 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 390852 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 391233 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 391227 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 390512 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 390457 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 391259 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 51397 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 51233 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 51042 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51696 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51565 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51001 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51007 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51680 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 52040 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51354 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51500 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51879 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51844 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51252 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51165 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51893 # Track writes on a per bank basis +system.physmem.bw_total::cpu1.inst 368587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7469649 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 60233760 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6257533 # Total number of read requests seen +system.physmem.writeReqs 823123 # Total number of write requests seen +system.physmem.cpureqs 241438 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 400482112 # Total number of bytes read from memory +system.physmem.bytesWritten 52679872 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 59164324 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7269712 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 127 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 12571 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 391437 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 391240 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 390831 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 391593 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 391498 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 390850 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 390980 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 391704 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 391387 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 390658 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 390771 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 391161 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 391176 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 390450 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 390424 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 391246 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 51442 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 51251 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50977 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51666 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51519 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50946 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51023 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51720 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 52026 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51302 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51417 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51816 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51807 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51192 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51138 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51881 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2243059 # Number of times wr buffer was full causing retry -system.physmem.totGap 1102939019000 # Total gap between requests +system.physmem.numWrRetry 32625 # Number of times wr buffer was full causing retry +system.physmem.totGap 1102935703000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 105 # Categorize read packet sizes system.physmem.readPktSize::3 6094848 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 163014 # Categorize read packet sizes +system.physmem.readPktSize::6 162580 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 756836 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 66712 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 493693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 430180 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 391390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1441411 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1086258 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1098726 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1064578 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 26935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 24930 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 44513 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 63858 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 44248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 12053 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 11796 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 17166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 5937 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 152 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66287 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 494185 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 430784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 392337 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1441558 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1085468 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1097761 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1063978 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 26861 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 24868 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 44400 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 63675 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 44199 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 12096 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 11871 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 15313 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 7884 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -160,59 +160,59 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32635 # What write queue length does an incoming req see -system.physmem.totQLat 199192058500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 239013617250 # Sum of mem lat for all requests -system.physmem.totBusLat 31289230000 # Total cycles spent in databus access -system.physmem.totBankLat 8532328750 # Total cycles spent in bank access -system.physmem.avgQLat 31830.77 # Average queueing delay per request -system.physmem.avgBankLat 1363.46 # Average bank access latency per request +system.physmem.wrQLenPdf::0 2876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32641 # What write queue length does an incoming req see +system.physmem.totQLat 199281441500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 239111429000 # Sum of mem lat for all requests +system.physmem.totBusLat 31287030000 # Total cycles spent in databus access +system.physmem.totBankLat 8542957500 # Total cycles spent in bank access +system.physmem.avgQLat 31847.29 # Average queueing delay per request +system.physmem.avgBankLat 1365.26 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 38194.23 # Average memory access latency -system.physmem.avgRdBW 363.13 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 47.79 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 53.67 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.62 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 38212.55 # Average memory access latency +system.physmem.avgRdBW 363.11 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 47.76 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 53.64 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.59 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.21 # Data bus utilization in percentage system.physmem.avgRdQLen 0.22 # Average read queue length over time -system.physmem.avgWrQLen 12.05 # Average write queue length over time -system.physmem.readRowHits 6213954 # Number of row buffer hits during reads -system.physmem.writeRowHits 800040 # Number of row buffer hits during writes +system.physmem.avgWrQLen 11.59 # Average write queue length over time +system.physmem.readRowHits 6213376 # Number of row buffer hits during reads +system.physmem.writeRowHits 799550 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.30 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.15 # Row buffer hit rate for writes -system.physmem.avgGap 155749.02 # Average gap between requests +system.physmem.writeRowHitRate 97.14 # Row buffer hit rate for writes +system.physmem.avgGap 155767.45 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -231,251 +231,251 @@ system.realview.nvmem.bw_inst_read::total 406 # I system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 72718 # number of replacements -system.l2c.tagsinuse 53743.140165 # Cycle average of tags in use -system.l2c.total_refs 1840331 # Total number of references to valid blocks. -system.l2c.sampled_refs 137862 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.349081 # Average number of references to valid blocks. +system.l2c.replacements 72282 # number of replacements +system.l2c.tagsinuse 53744.299693 # Cycle average of tags in use +system.l2c.total_refs 1841477 # Total number of references to valid blocks. +system.l2c.sampled_refs 137500 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.392560 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 39373.587396 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 3.826422 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 1.187080 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4008.736100 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2822.118244 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 11.062372 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.921462 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3716.187342 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 3805.513745 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.600793 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000058 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000018 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.061168 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.043062 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000169 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 39371.893894 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 5.466670 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 1.665850 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4003.284493 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2820.568488 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 11.108443 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.919823 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3725.007986 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 3804.384047 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.600767 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000083 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.itb.walker 0.000025 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.061085 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.043038 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000170 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.056705 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.058068 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.820055 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 22141 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4502 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 386239 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 166660 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30329 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5168 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 590386 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 197820 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1403245 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 580806 # number of Writeback hits -system.l2c.Writeback_hits::total 580806 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1235 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 743 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1978 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 201 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 145 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 346 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 48231 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58599 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106830 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 22141 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4502 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 386239 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 214891 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 30329 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5168 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 590386 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 256419 # number of demand (read+write) hits -system.l2c.demand_hits::total 1510075 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 22141 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4502 # number of overall hits -system.l2c.overall_hits::cpu0.inst 386239 # number of overall hits -system.l2c.overall_hits::cpu0.data 214891 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30329 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5168 # number of overall hits -system.l2c.overall_hits::cpu1.inst 590386 # number of overall hits -system.l2c.overall_hits::cpu1.data 256419 # number of overall hits -system.l2c.overall_hits::total 1510075 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 11 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6277 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6416 # number of ReadReq misses +system.l2c.occ_percent::cpu1.inst 0.056839 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.058050 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.820073 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 22824 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4741 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 386299 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 167150 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 30426 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5232 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 589817 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 197825 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1404314 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 581284 # number of Writeback hits +system.l2c.Writeback_hits::total 581284 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1196 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 780 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1976 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 199 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 146 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 345 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 48442 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 58735 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 107177 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 22824 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4741 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 386299 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 215592 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 30426 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5232 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 589817 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 256560 # number of demand (read+write) hits +system.l2c.demand_hits::total 1511491 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 22824 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4741 # number of overall hits +system.l2c.overall_hits::cpu0.inst 386299 # number of overall hits +system.l2c.overall_hits::cpu0.data 215592 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 30426 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5232 # number of overall hits +system.l2c.overall_hits::cpu1.inst 589817 # number of overall hits +system.l2c.overall_hits::cpu1.data 256560 # number of overall hits +system.l2c.overall_hits::total 1511491 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 14 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 6269 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6424 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 17 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6302 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 6301 # number of ReadReq misses -system.l2c.ReadReq_misses::total 25330 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 5125 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3774 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8899 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 638 # number of SCUpgradeReq misses +system.l2c.ReadReq_misses::cpu1.inst 6316 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 6288 # number of ReadReq misses +system.l2c.ReadReq_misses::total 25333 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 5101 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3782 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 8883 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 646 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 411 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1049 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63279 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 76923 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140202 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 11 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6277 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 69695 # number of demand (read+write) misses +system.l2c.SCUpgradeReq_misses::total 1057 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 63146 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 76636 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 139782 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 14 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 6269 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 69570 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 17 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 6302 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 83224 # number of demand (read+write) misses -system.l2c.demand_misses::total 165532 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 11 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6277 # number of overall misses -system.l2c.overall_misses::cpu0.data 69695 # number of overall misses +system.l2c.demand_misses::cpu1.inst 6316 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 82924 # number of demand (read+write) misses +system.l2c.demand_misses::total 165115 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 14 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses +system.l2c.overall_misses::cpu0.inst 6269 # number of overall misses +system.l2c.overall_misses::cpu0.data 69570 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 17 # number of overall misses system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 6302 # number of overall misses -system.l2c.overall_misses::cpu1.data 83224 # number of overall misses -system.l2c.overall_misses::total 165532 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 728500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 324500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 347861000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 370402499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1384000 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu1.inst 6316 # number of overall misses +system.l2c.overall_misses::cpu1.data 82924 # number of overall misses +system.l2c.overall_misses::total 165115 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 933000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 255500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 347054000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 368774499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1319000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.itb.walker 68500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 379078500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 392453000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1492300499 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 8816984 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 11833500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 20650484 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 568000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2844000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 3412000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3138283486 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4133582496 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7271865982 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 728500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 324500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 347861000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3508685985 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 1384000 # number of demand (read+write) miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 385195500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 391956499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1495556498 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 8608988 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 11814499 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 20423487 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 591500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2846500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 3438000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 3130357988 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4120844492 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7251202480 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 933000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 255500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 347054000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3499132487 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 1319000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.itb.walker 68500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 379078500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 4526035496 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8764166481 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 728500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 324500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 347861000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3508685985 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 1384000 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu1.inst 385195500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 4512800991 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8746758978 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 933000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 255500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 347054000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3499132487 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 1319000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.itb.walker 68500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 379078500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 4526035496 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8764166481 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 22152 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 4507 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 392516 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 173076 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 30346 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 5169 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 596688 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 204121 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1428575 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 580806 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 580806 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 6360 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 4517 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 10877 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 839 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 556 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1395 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 111510 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 135522 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247032 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 22152 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 4507 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 392516 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 284586 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 30346 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 5169 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 596688 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 339643 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1675607 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 22152 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 4507 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 392516 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 284586 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 30346 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 5169 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 596688 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 339643 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1675607 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000497 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001109 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015992 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.037070 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000560 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000193 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010562 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.030869 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.017731 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.805818 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.835510 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.818148 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.760429 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.739209 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.751971 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.567474 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.567605 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.567546 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000497 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.001109 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015992 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.244900 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000560 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.000193 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010562 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.245034 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.098789 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000497 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.001109 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015992 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.244900 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000560 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.000193 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010562 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.245034 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.098789 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 66227.272727 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 64900 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55418.352716 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 57731.062812 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 81411.764706 # average ReadReq miss latency +system.l2c.overall_miss_latency::cpu1.inst 385195500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 4512800991 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8746758978 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 22838 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 4745 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 392568 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 173574 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 30443 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 5233 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 596133 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 204113 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1429647 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 581284 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 581284 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 6297 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 4562 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 10859 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 845 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 557 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1402 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 111588 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 135371 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246959 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 22838 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 4745 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 392568 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 285162 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 30443 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 5233 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 596133 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 339484 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1676606 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 22838 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 4745 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 392568 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 285162 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 30443 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 5233 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 596133 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 339484 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1676606 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000613 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000843 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015969 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.037010 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000558 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000191 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010595 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.030806 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.017720 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.810068 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.829022 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.818031 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.764497 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.737882 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.753923 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.565885 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.566118 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.566013 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000613 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000843 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015969 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.243967 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000558 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.000191 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010595 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.244265 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.098482 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000613 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000843 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015969 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.243967 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000558 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.000191 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010595 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.244265 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.098482 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 66642.857143 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 63875 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55360.344553 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 57405.743929 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 77588.235294 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 68500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 60152.094573 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 62284.240597 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 58914.350533 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1720.387122 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3135.532591 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2320.539836 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 890.282132 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6919.708029 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 3252.621544 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49594.391283 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53736.626185 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 51867.063109 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 66227.272727 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 64900 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 55418.352716 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 50343.439056 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 81411.764706 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 60987.254592 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 62334.048823 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 59035.901709 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1687.705940 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3123.875992 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 2299.165485 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 915.634675 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6925.790754 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 3252.601703 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49573.337789 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53771.654210 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 51875.080339 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 66642.857143 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 63875 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 55360.344553 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 50296.571611 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 77588.235294 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.itb.walker 68500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 60152.094573 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 54383.777468 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52945.451520 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 66227.272727 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 64900 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 55418.352716 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 50343.439056 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 81411.764706 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 60987.254592 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 54420.927488 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52973.739382 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 66642.857143 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 63875 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 55360.344553 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 50296.571611 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 77588.235294 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.itb.walker 68500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 60152.094573 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 54383.777468 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52945.451520 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 60987.254592 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 54420.927488 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52973.739382 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -484,8 +484,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 66712 # number of writebacks -system.l2c.writebacks::total 66712 # number of writebacks +system.l2c.writebacks::writebacks 66287 # number of writebacks +system.l2c.writebacks::total 66287 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu0.data 37 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits @@ -501,163 +501,163 @@ system.l2c.overall_mshr_hits::cpu0.data 37 # nu system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.data 24 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 72 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 11 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 5 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 6273 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6379 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 14 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 4 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 6265 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6387 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 17 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 6295 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 6277 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 25258 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 5125 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 3774 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 8899 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 638 # number of SCUpgradeReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 6309 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 6264 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 25261 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 5101 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 3782 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 8883 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 646 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 411 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1049 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 63279 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 76923 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 140202 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 11 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 5 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 6273 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 69658 # number of demand (read+write) MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1057 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 63146 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 76636 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 139782 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 14 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 4 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 6265 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 69533 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 17 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 6295 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 83200 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 165460 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 11 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 5 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 6273 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 69658 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 6309 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 82900 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 165043 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 14 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 4 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 6265 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 69533 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 17 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 6295 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 83200 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 165460 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 591261 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 262004 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 269548612 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 289309796 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1171267 # number of ReadReq MSHR miss cycles +system.l2c.overall_mshr_misses::cpu1.inst 6309 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 82900 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 165043 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 760014 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 205753 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 268851852 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 287876545 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1106017 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 56251 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 300356052 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 312753448 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1174048691 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51546985 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 38368705 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 89915690 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6444113 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4119409 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 10563522 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2354035161 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3171377741 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5525412902 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 591261 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 262004 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 269548612 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2643344957 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1171267 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 306166045 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 312367924 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1177390401 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51308459 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 38489213 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 89797672 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6525620 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4130906 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 10656526 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2347754082 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3162202952 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5509957034 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 760014 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 205753 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 268851852 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2635630627 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1106017 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 56251 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 300356052 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 3484131189 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6699461593 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 591261 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 262004 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 269548612 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2643344957 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1171267 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 306166045 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 3474570876 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6687347435 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 760014 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 205753 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 268851852 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2635630627 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1106017 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 56251 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 300356052 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 3484131189 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6699461593 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5299085 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12408099047 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 306166045 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3474570876 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6687347435 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5300585 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12408061544 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2100282 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154667429748 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167082928162 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1050132738 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 25922779804 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 26972912542 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5299085 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13458231785 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154666775744 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167082238155 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1050331237 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 25987896299 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 27038227536 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5300585 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13458392781 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2100282 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 180590209552 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 194055840704 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000497 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001109 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015982 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036857 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000560 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000193 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010550 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030751 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.017681 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.805818 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.835510 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.818148 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.760429 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.739209 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.751971 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.567474 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567605 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.567546 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000497 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001109 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015982 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.244770 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000560 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000193 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010550 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.244963 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.098746 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000497 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001109 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015982 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.244770 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000560 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000193 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010550 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.244963 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.098746 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 52400.800000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42969.649609 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45353.471704 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824 # average ReadReq mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 180654672043 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 194120465691 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000613 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000843 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015959 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036797 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000558 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000191 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010583 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030689 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017669 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.810068 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.829022 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.818031 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.764497 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.737882 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.753923 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.565885 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.566118 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.566013 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000613 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000843 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015959 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.243837 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000558 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000191 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010583 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.244194 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.098439 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000613 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000843 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015959 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.243837 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000558 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000191 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010583 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.244194 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.098439 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 54286.714286 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42913.304389 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45072.263191 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 65059.823529 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 47713.431612 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 49825.306357 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 46482.250812 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10057.948293 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10166.588500 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10104.021800 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10100.490596 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10022.892944 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10070.087703 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37200.890675 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41227.951861 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 39410.371478 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 52400.800000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42969.649609 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37947.471317 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 48528.458551 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 49867.165390 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 46609.017893 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10058.509900 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10176.946854 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10108.935270 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10101.578947 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10050.866180 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10081.859981 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37179.775156 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41262.630513 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 39418.215750 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 54286.714286 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42913.304389 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37904.744898 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 65059.823529 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 47713.431612 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41876.576791 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40489.916554 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 52400.800000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42969.649609 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37947.471317 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 48528.458551 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41912.797057 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40518.818944 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 54286.714286 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42913.304389 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37904.744898 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 65059.823529 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47713.431612 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41876.576791 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40489.916554 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 48528.458551 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41912.797057 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40518.818944 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -678,38 +678,38 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 5998401 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4575821 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 294349 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3757481 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2911128 # Number of BTB hits +system.cpu0.branchPred.lookups 6001640 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4577059 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 296005 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3758008 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2912273 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 77.475521 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 672992 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28616 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 77.495125 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 673236 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28713 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8907261 # DTB read hits -system.cpu0.dtb.read_misses 28773 # DTB read misses -system.cpu0.dtb.write_hits 5136781 # DTB write hits -system.cpu0.dtb.write_misses 5705 # DTB write misses +system.cpu0.dtb.read_hits 8910999 # DTB read hits +system.cpu0.dtb.read_misses 29151 # DTB read misses +system.cpu0.dtb.write_hits 5140269 # DTB write hits +system.cpu0.dtb.write_misses 5702 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1814 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1038 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 293 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1812 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1035 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 300 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 560 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8936034 # DTB read accesses -system.cpu0.dtb.write_accesses 5142486 # DTB write accesses +system.cpu0.dtb.perms_faults 584 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8940150 # DTB read accesses +system.cpu0.dtb.write_accesses 5145971 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14044042 # DTB hits -system.cpu0.dtb.misses 34478 # DTB misses -system.cpu0.dtb.accesses 14078520 # DTB accesses -system.cpu0.itb.inst_hits 4215431 # ITB inst hits -system.cpu0.itb.inst_misses 5154 # ITB inst misses +system.cpu0.dtb.hits 14051268 # DTB hits +system.cpu0.dtb.misses 34853 # DTB misses +system.cpu0.dtb.accesses 14086121 # DTB accesses +system.cpu0.itb.inst_hits 4221147 # ITB inst hits +system.cpu0.itb.inst_misses 5166 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -722,144 +722,144 @@ system.cpu0.itb.flush_entries 1347 # Nu system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1523 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1454 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4220585 # ITB inst accesses -system.cpu0.itb.hits 4215431 # DTB hits -system.cpu0.itb.misses 5154 # DTB misses -system.cpu0.itb.accesses 4220585 # DTB accesses -system.cpu0.numCycles 67803924 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4226313 # ITB inst accesses +system.cpu0.itb.hits 4221147 # DTB hits +system.cpu0.itb.misses 5166 # DTB misses +system.cpu0.itb.accesses 4226313 # DTB accesses +system.cpu0.numCycles 67826289 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11747073 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32000754 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 5998401 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3584120 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7510773 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1450164 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 64498 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 20642358 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 4878 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 46878 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 85526 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 225 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4213800 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 157670 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2178 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 41143503 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.004869 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.385262 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11756286 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32014298 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6001640 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3585509 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7517140 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1455004 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 67247 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 20650253 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 4770 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 46433 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 85685 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 203 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4219566 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 157765 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2202 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 41172573 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.004783 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.385116 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33640113 81.76% 81.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 564874 1.37% 83.14% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 815232 1.98% 85.12% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 675522 1.64% 86.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 773200 1.88% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 558709 1.36% 90.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 669860 1.63% 91.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 351529 0.85% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3094464 7.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33662869 81.76% 81.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 565639 1.37% 83.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 818038 1.99% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 675166 1.64% 86.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 774675 1.88% 88.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 559568 1.36% 90.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 667522 1.62% 91.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 352154 0.86% 92.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3096942 7.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 41143503 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.088467 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.471960 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12253117 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 20585756 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6814381 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 512539 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 977710 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 934268 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64694 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 39987776 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 212486 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 977710 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12820427 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5742393 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12731772 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6709970 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2161231 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 38889294 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1829 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 434890 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1234500 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 47 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39244828 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 175643455 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 175609334 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34121 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30926653 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8318174 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 411256 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 370334 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5351915 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7647673 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5682766 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1124413 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1217910 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 36816448 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 895564 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37227077 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 80165 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6275180 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13166441 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256842 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 41143503 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.904811 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.512506 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 41172573 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.088485 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.472004 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12265416 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 20593296 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6819123 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 513990 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 980748 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 935580 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64947 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40010595 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 213478 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 980748 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12833750 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5743138 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12737000 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6715008 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2162929 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 38912871 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1796 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 435724 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1235455 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 48 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39264355 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 175753145 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 175718969 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34176 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30934227 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8330127 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 411039 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 370083 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5348370 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7652222 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5686978 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1127413 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1231482 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 36837080 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 895317 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37247377 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 80474 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6286180 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13172304 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256448 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 41172573 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.904665 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.512453 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 26013518 63.23% 63.23% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5726772 13.92% 77.15% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3163675 7.69% 84.83% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2471330 6.01% 90.84% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2096927 5.10% 95.94% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 946781 2.30% 98.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 487184 1.18% 99.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 184280 0.45% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 53036 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26032414 63.23% 63.23% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5734790 13.93% 77.16% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3160933 7.68% 84.83% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2474953 6.01% 90.84% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2097868 5.10% 95.94% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 946815 2.30% 98.24% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 486964 1.18% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 184157 0.45% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 53679 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 41143503 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 41172573 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 25911 2.42% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 452 0.04% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 841841 78.68% 81.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 201703 18.85% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 26092 2.44% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 452 0.04% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 843251 78.76% 81.24% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 200824 18.76% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52149 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22320567 59.96% 60.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46962 0.13% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52279 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22332748 59.96% 60.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46981 0.13% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued @@ -869,14 +869,14 @@ system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Ty system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 3 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued @@ -885,363 +885,367 @@ system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Ty system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9363552 25.15% 85.38% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5443123 14.62% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9367267 25.15% 85.38% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5447389 14.62% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37227077 # Type of FU issued -system.cpu0.iq.rate 0.549040 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1069907 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028740 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 116773591 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 43995152 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34325365 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8374 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4656 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3873 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38240450 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4385 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 307272 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37247377 # Type of FU issued +system.cpu0.iq.rate 0.549158 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1070619 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028743 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 116844627 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44026356 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34344813 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8420 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4690 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3883 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38261309 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4408 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 307850 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1372635 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2428 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13158 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 533443 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1374402 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2480 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 12973 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 535370 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2192715 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5605 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2192711 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5613 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 977710 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4125178 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 98819 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 37830480 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 84891 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7647673 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5682766 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 571414 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 40435 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 2836 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13158 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 149420 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 117102 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 266522 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 36852561 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9222790 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 374516 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 980748 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4124012 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 98712 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 37850539 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 85674 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7652222 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5686978 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 571475 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 40167 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 2962 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 12973 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 149952 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 118190 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 268142 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 36871873 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9226575 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 375504 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 118468 # number of nop insts executed -system.cpu0.iew.exec_refs 14619280 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4853073 # Number of branches executed -system.cpu0.iew.exec_stores 5396490 # Number of stores executed -system.cpu0.iew.exec_rate 0.543517 # Inst execution rate -system.cpu0.iew.wb_sent 36658484 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34329238 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18277167 # num instructions producing a value -system.cpu0.iew.wb_consumers 35166979 # num instructions consuming a value +system.cpu0.iew.exec_nop 118142 # number of nop insts executed +system.cpu0.iew.exec_refs 14626690 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4856874 # Number of branches executed +system.cpu0.iew.exec_stores 5400115 # Number of stores executed +system.cpu0.iew.exec_rate 0.543622 # Inst execution rate +system.cpu0.iew.wb_sent 36677250 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34348696 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18291021 # num instructions producing a value +system.cpu0.iew.wb_consumers 35196356 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.506302 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.519725 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.506422 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.519685 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6089898 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 638722 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 230765 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 40165793 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.778810 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.740848 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6101158 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 638869 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 232197 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 40191825 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.778547 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.740754 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 28496220 70.95% 70.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5717219 14.23% 85.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1914261 4.77% 89.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 974261 2.43% 92.37% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 784320 1.95% 94.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 523319 1.30% 95.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 386116 0.96% 96.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 218199 0.54% 97.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1151878 2.87% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 28520633 70.96% 70.96% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5717076 14.22% 85.19% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1914444 4.76% 89.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 974820 2.43% 92.37% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 784169 1.95% 94.33% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 523265 1.30% 95.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 386798 0.96% 96.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 217938 0.54% 97.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1152682 2.87% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 40165793 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 23678008 # Number of instructions committed -system.cpu0.commit.committedOps 31281512 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 40191825 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23681661 # Number of instructions committed +system.cpu0.commit.committedOps 31291235 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11424361 # Number of memory references committed -system.cpu0.commit.loads 6275038 # Number of loads committed -system.cpu0.commit.membars 229662 # Number of memory barriers committed -system.cpu0.commit.branches 4244821 # Number of branches committed +system.cpu0.commit.refs 11429428 # Number of memory references committed +system.cpu0.commit.loads 6277820 # Number of loads committed +system.cpu0.commit.membars 229679 # Number of memory barriers committed +system.cpu0.commit.branches 4245347 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 27638419 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489334 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1151878 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 27647557 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489379 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1152682 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 75534199 # The number of ROB reads -system.cpu0.rob.rob_writes 75722713 # The number of ROB writes -system.cpu0.timesIdled 360446 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26660421 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2138034694 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23597266 # Number of Instructions Simulated -system.cpu0.committedOps 31200770 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23597266 # Number of Instructions Simulated -system.cpu0.cpi 2.873381 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.873381 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.348022 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.348022 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 171786019 # number of integer regfile reads -system.cpu0.int_regfile_writes 34080976 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3260 # number of floating regfile reads -system.cpu0.fp_regfile_writes 902 # number of floating regfile writes -system.cpu0.misc_regfile_reads 13006141 # number of misc regfile reads -system.cpu0.misc_regfile_writes 451094 # number of misc regfile writes -system.cpu0.icache.replacements 392511 # number of replacements -system.cpu0.icache.tagsinuse 511.076367 # Cycle average of tags in use -system.cpu0.icache.total_refs 3789958 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 393023 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.643095 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 75580359 # The number of ROB reads +system.cpu0.rob.rob_writes 75767781 # The number of ROB writes +system.cpu0.timesIdled 360539 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26653716 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2138005786 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23600919 # Number of Instructions Simulated +system.cpu0.committedOps 31210493 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23600919 # Number of Instructions Simulated +system.cpu0.cpi 2.873883 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.873883 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.347961 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.347961 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 171874490 # number of integer regfile reads +system.cpu0.int_regfile_writes 34096600 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3230 # number of floating regfile reads +system.cpu0.fp_regfile_writes 872 # number of floating regfile writes +system.cpu0.misc_regfile_reads 13012666 # number of misc regfile reads +system.cpu0.misc_regfile_writes 451076 # number of misc regfile writes +system.cpu0.icache.replacements 392591 # number of replacements +system.cpu0.icache.tagsinuse 511.076357 # Cycle average of tags in use +system.cpu0.icache.total_refs 3795579 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 393103 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.655431 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 6563458000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.076367 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu0.inst 511.076357 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.998196 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.998196 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3789958 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3789958 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3789958 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3789958 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3789958 # number of overall hits -system.cpu0.icache.overall_hits::total 3789958 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 423709 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 423709 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 423709 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 423709 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 423709 # number of overall misses -system.cpu0.icache.overall_misses::total 423709 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5803688497 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5803688497 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5803688497 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5803688497 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5803688497 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5803688497 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4213667 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4213667 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4213667 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4213667 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4213667 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4213667 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100556 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100556 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100556 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100556 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100556 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100556 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13697.345341 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13697.345341 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13697.345341 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13697.345341 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13697.345341 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13697.345341 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2656 # number of cycles access was blocked +system.cpu0.icache.ReadReq_hits::cpu0.inst 3795579 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3795579 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3795579 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3795579 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3795579 # number of overall hits +system.cpu0.icache.overall_hits::total 3795579 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 423854 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 423854 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 423854 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 423854 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 423854 # number of overall misses +system.cpu0.icache.overall_misses::total 423854 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5804082997 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5804082997 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5804082997 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5804082997 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5804082997 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5804082997 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4219433 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4219433 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4219433 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4219433 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4219433 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4219433 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100453 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100453 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100453 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100453 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100453 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100453 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13693.590239 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13693.590239 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13693.590239 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13693.590239 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13693.590239 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13693.590239 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2620 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 149 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 153 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.825503 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.124183 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30672 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 30672 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 30672 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 30672 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 30672 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 30672 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393037 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 393037 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 393037 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 393037 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 393037 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 393037 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4746801497 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4746801497 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4746801497 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4746801497 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4746801497 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4746801497 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7900500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7900500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7900500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 7900500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093277 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093277 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093277 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093277 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093277 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093277 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12077.238268 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12077.238268 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12077.238268 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12077.238268 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12077.238268 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12077.238268 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30736 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 30736 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 30736 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 30736 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 30736 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 30736 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393118 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 393118 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 393118 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 393118 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 393118 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 393118 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4745929997 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4745929997 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4745929997 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4745929997 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4745929997 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4745929997 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7902000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7902000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7902000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 7902000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093168 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093168 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093168 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093168 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093168 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093168 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12072.532921 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12072.532921 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12072.532921 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12072.532921 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12072.532921 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12072.532921 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 275921 # number of replacements -system.cpu0.dcache.tagsinuse 460.698692 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9260016 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 276433 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.498229 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 276649 # number of replacements +system.cpu0.dcache.tagsinuse 460.596566 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9262154 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 277161 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.417956 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 43509000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 460.698692 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.899802 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.899802 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5779987 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5779987 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3159663 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3159663 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139233 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 139233 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137076 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 137076 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8939650 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8939650 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8939650 # number of overall hits -system.cpu0.dcache.overall_hits::total 8939650 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 392818 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 392818 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1582384 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1582384 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8769 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8769 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7464 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7464 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1975202 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1975202 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1975202 # number of overall misses -system.cpu0.dcache.overall_misses::total 1975202 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5481439500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5481439500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60566359369 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 60566359369 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 87760500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 87760500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46440000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 46440000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 66047798869 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 66047798869 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 66047798869 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 66047798869 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6172805 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6172805 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4742047 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4742047 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148002 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 148002 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144540 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 144540 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 10914852 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 10914852 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 10914852 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 10914852 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063637 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.063637 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333692 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.333692 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059249 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059249 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051640 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051640 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.180965 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.180965 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.180965 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.180965 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13954.145431 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13954.145431 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38275.386612 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38275.386612 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10008.039685 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10008.039685 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6221.864952 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6221.864952 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33438.503439 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33438.503439 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33438.503439 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33438.503439 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 8565 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 5561 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 643 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 81 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.320373 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 68.654321 # average number of cycles each access was blocked +system.cpu0.dcache.occ_blocks::cpu0.data 460.596566 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.899603 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.899603 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5782081 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5782081 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3160908 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3160908 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139098 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 139098 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137052 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 137052 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8942989 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8942989 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8942989 # number of overall hits +system.cpu0.dcache.overall_hits::total 8942989 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 394048 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 394048 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1583429 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1583429 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8774 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8774 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7489 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7489 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1977477 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1977477 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1977477 # number of overall misses +system.cpu0.dcache.overall_misses::total 1977477 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5492603000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5492603000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60464990363 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 60464990363 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 87990000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 87990000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46572500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 46572500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 65957593363 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 65957593363 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 65957593363 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 65957593363 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6176129 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6176129 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4744337 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4744337 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147872 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 147872 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144541 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144541 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10920466 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10920466 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10920466 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10920466 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063802 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063802 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333751 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.333751 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059335 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059335 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051812 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051812 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181080 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.181080 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181080 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.181080 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13938.918609 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13938.918609 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38186.107721 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38186.107721 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10028.493276 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10028.493276 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6218.787555 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6218.787555 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33354.417454 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33354.417454 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33354.417454 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33354.417454 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8825 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 4351 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 671 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 80 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.152012 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 54.387500 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 256512 # number of writebacks -system.cpu0.dcache.writebacks::total 256512 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 204354 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 204354 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1452130 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1452130 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 476 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 476 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1656484 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1656484 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1656484 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1656484 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188464 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188464 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130254 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 130254 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8293 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8293 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7464 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7464 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 318718 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 318718 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 318718 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 318718 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2378480500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2378480500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4031341491 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4031341491 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 65938500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 65938500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31512000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31512000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6409821991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6409821991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6409821991 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6409821991 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13514864500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13514864500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180302878 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180302878 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14695167378 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14695167378 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030531 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030531 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027468 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027468 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056033 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056033 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051640 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051640 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029200 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029200 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029200 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029200 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12620.343938 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12620.343938 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30949.847920 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30949.847920 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7951.103340 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7951.103340 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4221.864952 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4221.864952 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20111.264475 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20111.264475 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20111.264475 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20111.264475 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 257146 # number of writebacks +system.cpu0.dcache.writebacks::total 257146 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 204997 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 204997 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1453030 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1453030 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 464 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 464 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1658027 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1658027 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1658027 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1658027 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189051 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 189051 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130399 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130399 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8310 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8310 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7487 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7487 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 319450 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 319450 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 319450 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 319450 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2382504500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2382504500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4025705992 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4025705992 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66268000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66268000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31600500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31600500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6408210492 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6408210492 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6408210492 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6408210492 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13514784000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13514784000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180269878 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180269878 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14695053878 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14695053878 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030610 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030610 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027485 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027485 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056197 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056197 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051798 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051798 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029252 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029252 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029252 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029252 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12602.443256 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12602.443256 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30872.215216 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30872.215216 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7974.488568 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7974.488568 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4220.715908 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4220.715908 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20060.136147 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20060.136147 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20060.136147 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20060.136147 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1249,38 +1253,38 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 9068423 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7455270 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 408018 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 6064102 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 5241151 # Number of BTB hits +system.cpu1.branchPred.lookups 9057370 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7441884 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 409640 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 6090561 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 5229548 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 86.429137 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 772299 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 42697 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 85.863158 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 772754 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 42888 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42898238 # DTB read hits -system.cpu1.dtb.read_misses 36741 # DTB read misses -system.cpu1.dtb.write_hits 6823025 # DTB write hits -system.cpu1.dtb.write_misses 10725 # DTB write misses +system.cpu1.dtb.read_hits 42905047 # DTB read hits +system.cpu1.dtb.read_misses 36603 # DTB read misses +system.cpu1.dtb.write_hits 6822006 # DTB write hits +system.cpu1.dtb.write_misses 10721 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2008 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2490 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 302 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2003 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2568 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 298 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 655 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 42934979 # DTB read accesses -system.cpu1.dtb.write_accesses 6833750 # DTB write accesses +system.cpu1.dtb.perms_faults 647 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 42941650 # DTB read accesses +system.cpu1.dtb.write_accesses 6832727 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49721263 # DTB hits -system.cpu1.dtb.misses 47466 # DTB misses -system.cpu1.dtb.accesses 49768729 # DTB accesses -system.cpu1.itb.inst_hits 8394494 # ITB inst hits -system.cpu1.itb.inst_misses 5446 # ITB inst misses +system.cpu1.dtb.hits 49727053 # DTB hits +system.cpu1.dtb.misses 47324 # DTB misses +system.cpu1.dtb.accesses 49774377 # DTB accesses +system.cpu1.itb.inst_hits 8402267 # ITB inst hits +system.cpu1.itb.inst_misses 5496 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1289,114 +1293,114 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1530 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1527 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1510 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1556 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8399940 # ITB inst accesses -system.cpu1.itb.hits 8394494 # DTB hits -system.cpu1.itb.misses 5446 # DTB misses -system.cpu1.itb.accesses 8399940 # DTB accesses -system.cpu1.numCycles 408755802 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8407763 # ITB inst accesses +system.cpu1.itb.hits 8402267 # DTB hits +system.cpu1.itb.misses 5496 # DTB misses +system.cpu1.itb.accesses 8407763 # DTB accesses +system.cpu1.numCycles 408754758 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 19793701 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 66043012 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9068423 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6013450 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 14139093 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3958938 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 65451 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 77253219 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 4575 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 41710 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 129512 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 148 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8392686 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 740378 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2825 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 114124947 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.700718 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.045131 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 19786435 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 66033865 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9057370 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6002302 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 14145991 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3963679 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 66957 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 77248735 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 4641 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 42710 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 129584 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 102 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 8400411 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 741502 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2853 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 114126440 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.700482 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.044104 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 99993030 87.62% 87.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 796567 0.70% 88.32% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 937489 0.82% 89.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1887963 1.65% 90.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1516591 1.33% 92.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 569617 0.50% 92.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2129815 1.87% 94.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 410324 0.36% 94.84% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5883551 5.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 99987714 87.61% 87.61% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 797074 0.70% 88.31% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 939049 0.82% 89.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1891067 1.66% 90.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1525429 1.34% 92.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 571908 0.50% 92.63% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2134670 1.87% 94.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 410312 0.36% 94.86% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5869217 5.14% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 114124947 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022185 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.161571 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 21308374 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 76909285 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12783383 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 523008 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2600897 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1105255 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 98147 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 75181804 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 327202 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2600897 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 22691617 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 31944842 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 40730815 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11827860 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4328916 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 69723383 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 18766 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 668457 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3086605 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 426 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 73713482 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 321023926 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 320964994 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 58932 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 49048009 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 24665473 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 444684 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 387735 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7872422 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 13201823 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8142648 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1033883 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1534096 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 63487985 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1158001 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 89118015 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 94635 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 16215431 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 45695453 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 277388 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 114124947 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.780881 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.519165 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 114126440 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022158 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.161549 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 21303172 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 76905866 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12788673 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 523903 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2604826 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1105931 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 97877 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 75200071 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 325666 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2604826 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 22687981 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 31933680 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 40739903 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11832589 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4327461 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 69726432 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 18789 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 667798 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3085321 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 1194 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 73678442 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 321083951 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 321025301 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 58650 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49043171 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 24635271 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 445050 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 388065 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7869897 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 13205633 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8143981 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1031020 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1549372 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 63452075 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1154123 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 89105675 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 94570 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 16177961 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 45638243 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 273609 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 114126440 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.780763 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.519063 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 83732864 73.37% 73.37% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8404718 7.36% 80.73% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4298594 3.77% 84.50% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3768314 3.30% 87.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10582090 9.27% 97.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1967507 1.72% 98.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1024622 0.90% 99.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 272364 0.24% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 73874 0.06% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 83740358 73.38% 73.38% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8394887 7.36% 80.73% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4311710 3.78% 84.51% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3761165 3.30% 87.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10575130 9.27% 97.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1975219 1.73% 98.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1022890 0.90% 99.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 270730 0.24% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 74351 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 114124947 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 114126440 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29701 0.38% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 998 0.01% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29540 0.38% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 995 0.01% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available @@ -1424,399 +1428,399 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.39% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7545557 95.86% 96.25% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 295033 3.75% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7547716 95.90% 96.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 292001 3.71% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 313997 0.35% 0.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 37610156 42.20% 42.55% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59163 0.07% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1504 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43962640 49.33% 91.95% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7170532 8.05% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 313932 0.35% 0.35% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 37588774 42.18% 42.54% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59166 0.07% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1504 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43972144 49.35% 91.95% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7170135 8.05% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 89118015 # Type of FU issued -system.cpu1.iq.rate 0.218023 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7871289 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.088324 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 300359292 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 80869896 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 53629107 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14882 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8062 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6802 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 96667481 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7826 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 342650 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 89105675 # Type of FU issued +system.cpu1.iq.rate 0.217993 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7870252 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.088325 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 300334896 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 80792722 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 53591705 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14852 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8010 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6792 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 96654176 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7819 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 342901 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3449296 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3766 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17093 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1304806 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3454829 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3906 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17123 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1307403 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31906048 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 888017 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31911868 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 888624 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2600897 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 24182074 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 360611 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 64750813 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 110749 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 13201823 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8142648 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 869251 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 65576 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3534 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17093 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 201242 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 155476 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 356718 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 86688682 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43267985 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2429333 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2604826 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 24177502 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 360064 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 64710295 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 111591 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 13205633 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8143981 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 865041 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 65040 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3489 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17123 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 203707 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 155314 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 359021 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 86656699 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43274731 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2448976 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 104827 # number of nop insts executed -system.cpu1.iew.exec_refs 50376799 # number of memory reference insts executed -system.cpu1.iew.exec_branches 6999376 # Number of branches executed -system.cpu1.iew.exec_stores 7108814 # Number of stores executed -system.cpu1.iew.exec_rate 0.212079 # Inst execution rate -system.cpu1.iew.wb_sent 85711710 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 53635909 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 29908204 # num instructions producing a value -system.cpu1.iew.wb_consumers 53361522 # num instructions consuming a value +system.cpu1.iew.exec_nop 104097 # number of nop insts executed +system.cpu1.iew.exec_refs 50382465 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6984824 # Number of branches executed +system.cpu1.iew.exec_stores 7107734 # Number of stores executed +system.cpu1.iew.exec_rate 0.212002 # Inst execution rate +system.cpu1.iew.wb_sent 85679792 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 53598497 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 29912489 # num instructions producing a value +system.cpu1.iew.wb_consumers 53377026 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.131217 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.560483 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.131126 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.560400 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 16119527 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 880613 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 311377 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 111524050 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.431703 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.400207 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 16097351 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 880514 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 313181 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 111521614 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.431660 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.399918 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 94787660 84.99% 84.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8229182 7.38% 92.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2114661 1.90% 94.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1254724 1.13% 95.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1244333 1.12% 96.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 567856 0.51% 97.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 997712 0.89% 97.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 503621 0.45% 98.36% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1824301 1.64% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 94783688 84.99% 84.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8232715 7.38% 92.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2113496 1.90% 94.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1251152 1.12% 95.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1245297 1.12% 96.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 569963 0.51% 97.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1001738 0.90% 97.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 503665 0.45% 98.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1819900 1.63% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 111524050 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38058618 # Number of instructions committed -system.cpu1.commit.committedOps 48145315 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 111521614 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38055916 # Number of instructions committed +system.cpu1.commit.committedOps 48139449 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16590369 # Number of memory references committed -system.cpu1.commit.loads 9752527 # Number of loads committed -system.cpu1.commit.membars 190082 # Number of memory barriers committed -system.cpu1.commit.branches 5966603 # Number of branches committed +system.cpu1.commit.refs 16587382 # Number of memory references committed +system.cpu1.commit.loads 9750804 # Number of loads committed +system.cpu1.commit.membars 190065 # Number of memory barriers committed +system.cpu1.commit.branches 5966253 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 42681078 # Number of committed integer instructions. -system.cpu1.commit.function_calls 534481 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1824301 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 42675584 # Number of committed integer instructions. +system.cpu1.commit.function_calls 534450 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1819900 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 172920681 # The number of ROB reads -system.cpu1.rob.rob_writes 131224345 # The number of ROB writes -system.cpu1.timesIdled 1408365 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 294630855 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 1796488086 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 37988979 # Number of Instructions Simulated -system.cpu1.committedOps 48075676 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 37988979 # Number of Instructions Simulated -system.cpu1.cpi 10.759852 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.759852 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.092938 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.092938 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 387889245 # number of integer regfile reads -system.cpu1.int_regfile_writes 56198451 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4879 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2320 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18462900 # number of misc regfile reads -system.cpu1.misc_regfile_writes 405383 # number of misc regfile writes -system.cpu1.icache.replacements 596769 # number of replacements -system.cpu1.icache.tagsinuse 480.741673 # Cycle average of tags in use -system.cpu1.icache.total_refs 7750669 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 597281 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 12.976587 # Average number of references to valid blocks. +system.cpu1.rob.rob_reads 172894643 # The number of ROB reads +system.cpu1.rob.rob_writes 131171187 # The number of ROB writes +system.cpu1.timesIdled 1407429 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 294628318 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 1796480472 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 37986277 # Number of Instructions Simulated +system.cpu1.committedOps 48069810 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 37986277 # Number of Instructions Simulated +system.cpu1.cpi 10.760590 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.760590 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.092932 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.092932 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 387762774 # number of integer regfile reads +system.cpu1.int_regfile_writes 56160786 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4853 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2312 # number of floating regfile writes +system.cpu1.misc_regfile_reads 18458538 # number of misc regfile reads +system.cpu1.misc_regfile_writes 405362 # number of misc regfile writes +system.cpu1.icache.replacements 596198 # number of replacements +system.cpu1.icache.tagsinuse 480.885955 # Cycle average of tags in use +system.cpu1.icache.total_refs 7759207 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 596710 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 13.003313 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 74225092500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 480.741673 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.938949 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.938949 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 7750669 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7750669 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7750669 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7750669 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7750669 # number of overall hits -system.cpu1.icache.overall_hits::total 7750669 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 641966 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 641966 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 641966 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 641966 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 641966 # number of overall misses -system.cpu1.icache.overall_misses::total 641966 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8653423491 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8653423491 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8653423491 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8653423491 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8653423491 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8653423491 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 8392635 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8392635 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8392635 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8392635 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8392635 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8392635 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076492 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.076492 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076492 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.076492 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076492 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.076492 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13479.566661 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13479.566661 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13479.566661 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13479.566661 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13479.566661 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13479.566661 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2249 # number of cycles access was blocked +system.cpu1.icache.occ_blocks::cpu1.inst 480.885955 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.939230 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.939230 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 7759207 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7759207 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7759207 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7759207 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7759207 # number of overall hits +system.cpu1.icache.overall_hits::total 7759207 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 641153 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 641153 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 641153 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 641153 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 641153 # number of overall misses +system.cpu1.icache.overall_misses::total 641153 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8644043496 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8644043496 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8644043496 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8644043496 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8644043496 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8644043496 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 8400360 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8400360 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 8400360 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 8400360 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 8400360 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 8400360 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076324 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.076324 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076324 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.076324 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076324 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.076324 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13482.029244 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13482.029244 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13482.029244 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13482.029244 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13482.029244 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13482.029244 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 2220 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 165 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 167 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.630303 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.293413 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44655 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 44655 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 44655 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 44655 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 44655 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 44655 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 597311 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 597311 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 597311 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 597311 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 597311 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 597311 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7076959992 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7076959992 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7076959992 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7076959992 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7076959992 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7076959992 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44405 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 44405 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 44405 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 44405 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 44405 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 44405 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 596748 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 596748 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 596748 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 596748 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 596748 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 596748 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7076621996 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7076621996 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7076621996 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7076621996 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7076621996 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7076621996 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3098500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3098500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3098500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 3098500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071171 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071171 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071171 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.071171 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071171 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.071171 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11848.032251 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11848.032251 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11848.032251 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11848.032251 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11848.032251 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11848.032251 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071038 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071038 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071038 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.071038 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071038 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.071038 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11858.643843 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11858.643843 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11858.643843 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11858.643843 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11858.643843 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11858.643843 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 360267 # number of replacements -system.cpu1.dcache.tagsinuse 474.654017 # Cycle average of tags in use -system.cpu1.dcache.total_refs 12671092 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 360637 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 35.135308 # Average number of references to valid blocks. +system.cpu1.dcache.replacements 359991 # number of replacements +system.cpu1.dcache.tagsinuse 474.520156 # Cycle average of tags in use +system.cpu1.dcache.total_refs 12670892 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 360323 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 35.165371 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 70354132000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 474.654017 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.927059 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.927059 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8304151 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8304151 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4137952 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4137952 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97565 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 97565 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94853 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 94853 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12442103 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12442103 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12442103 # number of overall hits -system.cpu1.dcache.overall_hits::total 12442103 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 399179 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 399179 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1556589 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1556589 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13972 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 13972 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10605 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10605 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1955768 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1955768 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1955768 # number of overall misses -system.cpu1.dcache.overall_misses::total 1955768 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6101251500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6101251500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61874023496 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 61874023496 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129109000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 129109000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53792000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 53792000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 67975274996 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 67975274996 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 67975274996 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 67975274996 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 8703330 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 8703330 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5694541 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5694541 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111537 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 111537 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105458 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 105458 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14397871 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14397871 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14397871 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14397871 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045865 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.045865 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273348 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.273348 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125268 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125268 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100561 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100561 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135837 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.135837 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135837 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.135837 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15284.500187 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15284.500187 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39749.749931 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 39749.749931 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9240.552534 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9240.552534 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5072.324375 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5072.324375 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34756.308006 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 34756.308006 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34756.308006 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 34756.308006 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 25344 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 13325 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3330 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 157 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.610811 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 84.872611 # average number of cycles each access was blocked +system.cpu1.dcache.occ_blocks::cpu1.data 474.520156 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.926797 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.926797 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8303862 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8303862 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4138320 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4138320 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97526 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 97526 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94815 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 94815 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12442182 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12442182 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12442182 # number of overall hits +system.cpu1.dcache.overall_hits::total 12442182 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 400057 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 400057 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1554920 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1554920 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13970 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 13970 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10628 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10628 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1954977 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1954977 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1954977 # number of overall misses +system.cpu1.dcache.overall_misses::total 1954977 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6105054500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6105054500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61696466986 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 61696466986 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129466000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 129466000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53986500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 53986500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 67801521486 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 67801521486 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 67801521486 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 67801521486 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8703919 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8703919 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5693240 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5693240 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111496 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 111496 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105443 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 105443 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14397159 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14397159 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14397159 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14397159 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045963 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045963 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273117 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.273117 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125296 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125296 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100794 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100794 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135789 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.135789 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135789 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.135789 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15260.461634 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15260.461634 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39678.225880 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 39678.225880 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9267.430208 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9267.430208 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5079.648099 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5079.648099 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34681.493177 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 34681.493177 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34681.493177 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 34681.493177 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 24449 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 13557 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3317 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 162 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.370817 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 83.685185 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 324294 # number of writebacks -system.cpu1.dcache.writebacks::total 324294 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171223 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 171223 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1395128 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1395128 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1450 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1450 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1566351 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1566351 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1566351 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1566351 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 227956 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 227956 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161461 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 161461 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12522 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12522 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10600 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10600 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 389417 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 389417 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 389417 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 389417 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2851782000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2851782000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5138031205 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5138031205 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88180500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88180500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32594000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32594000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.writebacks::writebacks 324138 # number of writebacks +system.cpu1.dcache.writebacks::total 324138 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 172104 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 172104 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1393517 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1393517 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1456 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1456 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1565621 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1565621 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1565621 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1565621 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 227953 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 227953 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161403 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 161403 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12514 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12514 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10624 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10624 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 389356 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 389356 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 389356 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 389356 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2849477500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2849477500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5127514196 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5127514196 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88527000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88527000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32740500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32740500 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7989813205 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 7989813205 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7989813205 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 7989813205 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168990081000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168990081000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35691035962 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35691035962 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204681116962 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204681116962 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026192 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026192 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028354 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028354 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112268 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112268 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100514 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100514 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027047 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027047 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027047 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027047 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12510.230044 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12510.230044 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31822.119304 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31822.119304 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7042.045999 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7042.045999 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3074.905660 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3074.905660 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7976991696 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 7976991696 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7976991696 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 7976991696 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168989374500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168989374500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35732843580 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35732843580 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204722218080 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204722218080 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026190 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026190 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028350 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028350 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112237 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112237 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100756 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100756 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027044 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027044 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027044 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027044 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12500.285146 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12500.285146 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31768.394615 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31768.394615 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7074.236855 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7074.236855 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3081.748870 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3081.748870 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20517.371365 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20517.371365 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20517.371365 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20517.371365 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20487.655760 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20487.655760 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20487.655760 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20487.655760 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1838,17 +1842,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540139410201 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 540139410201 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540139410201 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 540139410201 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540238105555 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 540238105555 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540238105555 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 540238105555 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 41727 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 41724 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 48854 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 9b1cbcf2d..3671417ef 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,132 +1,144 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.533144 # Number of seconds simulated -sim_ticks 2533143973500 # Number of ticks simulated -final_tick 2533143973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.533141 # Number of seconds simulated +sim_ticks 2533140518500 # Number of ticks simulated +final_tick 2533140518500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 64483 # Simulator instruction rate (inst/s) -host_op_rate 82972 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2708528376 # Simulator tick rate (ticks/s) -host_mem_usage 405264 # Number of bytes of host memory used -host_seconds 935.25 # Real time elapsed on the host -sim_insts 60307579 # Number of instructions simulated -sim_ops 77599125 # Number of ops (including micro ops) simulated +host_inst_rate 41838 # Simulator instruction rate (inst/s) +host_op_rate 53833 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1757330352 # Simulator tick rate (ticks/s) +host_mem_usage 435908 # Number of bytes of host memory used +host_seconds 1441.47 # Real time elapsed on the host +sim_insts 60307702 # Number of instructions simulated +sim_ops 77599241 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 796608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093392 # Number of bytes read from this memory -system.physmem.bytes_read::total 129430480 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 796608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 796608 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3782336 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 796032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093328 # Number of bytes read from this memory +system.physmem.bytes_read::total 129429840 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 796032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796032 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3782784 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6798408 # Number of bytes written to this memory +system.physmem.bytes_written::total 6798856 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 42 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12447 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142118 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096817 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59099 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12438 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142117 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096807 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59106 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813117 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47189447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1061 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314474 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3589765 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51094798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314474 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314474 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1493139 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190644 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2683783 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1493139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47189447 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1061 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314474 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4780409 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53778581 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096817 # Total number of read requests seen -system.physmem.writeReqs 813117 # Total number of write requests seen -system.physmem.cpureqs 218351 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966196288 # Total number of bytes read from memory -system.physmem.bytesWritten 52039488 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129430480 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6798408 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 227 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4679 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943948 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943440 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943386 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 944197 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943985 # Track reads on a per bank basis +system.physmem.num_writes::total 813124 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47189512 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314247 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3589745 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51094615 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314247 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314247 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493318 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190645 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2683963 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493318 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47189512 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314247 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4780390 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53778578 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096807 # Total number of read requests seen +system.physmem.writeReqs 813124 # Total number of write requests seen +system.physmem.cpureqs 218344 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966195648 # Total number of bytes read from memory +system.physmem.bytesWritten 52039936 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129429840 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6798856 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 294 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4675 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943944 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943437 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943387 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 944192 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943982 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 943146 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943274 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943868 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943807 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943277 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943871 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943786 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 943302 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943206 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943616 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943708 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943088 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 942997 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943622 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50835 # Track writes on a per bank basis +system.physmem.perBankRdReqs::10 943229 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 943609 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943686 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943077 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 942973 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943615 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50829 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 50409 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50435 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51153 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50912 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50181 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50279 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50860 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51368 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50900 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50799 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51241 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50710 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50623 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51228 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50437 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51152 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50182 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50284 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50862 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51365 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50905 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50801 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51190 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51240 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50707 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50625 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51227 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2238337 # Number of times wr buffer was full causing retry -system.physmem.totGap 2533142848500 # Total gap between requests +system.physmem.numWrRetry 32502 # Number of times wr buffer was full causing retry +system.physmem.totGap 2533139407500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154573 # Categorize read packet sizes +system.physmem.readPktSize::6 154563 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754018 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59099 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1040033 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 981185 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 950276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3550309 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2676403 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2688030 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2649604 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60807 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59178 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 108698 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 157635 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 108246 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 16712 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16586 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 21915 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 10857 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59106 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1040017 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 981099 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 950174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3550467 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2676456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2688055 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2649570 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60697 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59181 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 108712 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 157594 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 108279 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 16749 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16591 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 12584 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -139,15 +151,15 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2788 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 2815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2837 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see @@ -160,25 +172,25 @@ system.physmem.wrQLenPdf::17 35353 # Wh system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32776 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32722 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 32676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32584 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32565 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 32538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32521 # What write queue length does an incoming req see -system.physmem.totQLat 393251142750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 485645877750 # Sum of mem lat for all requests -system.physmem.totBusLat 75482950000 # Total cycles spent in databus access -system.physmem.totBankLat 16911785000 # Total cycles spent in bank access -system.physmem.avgQLat 26049.00 # Average queueing delay per request -system.physmem.avgBankLat 1120.24 # Average bank access latency per request +system.physmem.wrQLenPdf::31 32516 # What write queue length does an incoming req see +system.physmem.totQLat 393185279250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 485577085500 # Sum of mem lat for all requests +system.physmem.totBusLat 75482565000 # Total cycles spent in databus access +system.physmem.totBankLat 16909241250 # Total cycles spent in bank access +system.physmem.avgQLat 26044.77 # Average queueing delay per request +system.physmem.avgBankLat 1120.08 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32169.24 # Average memory access latency +system.physmem.avgMemAccLat 32164.85 # Average memory access latency system.physmem.avgRdBW 381.42 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s @@ -186,62 +198,50 @@ system.physmem.avgConsumedWrBW 2.68 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.14 # Data bus utilization in percentage system.physmem.avgRdQLen 0.19 # Average read queue length over time -system.physmem.avgWrQLen 9.55 # Average write queue length over time -system.physmem.readRowHits 15020272 # Number of row buffer hits during reads -system.physmem.writeRowHits 793090 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.54 # Row buffer hit rate for writes -system.physmem.avgGap 159217.68 # Average gap between requests -system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.avgWrQLen 11.32 # Average write queue length over time +system.physmem.readRowHits 15020284 # Number of row buffer hits during reads +system.physmem.writeRowHits 793162 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.50 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 97.55 # Row buffer hit rate for writes +system.physmem.avgGap 159217.50 # Average gap between requests system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu.branchPred.lookups 14675749 # Number of BP lookups -system.cpu.branchPred.condPredicted 11761615 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 705306 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9809113 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7951342 # Number of BTB hits +system.cpu.branchPred.lookups 14656582 # Number of BP lookups +system.cpu.branchPred.condPredicted 11744816 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 702966 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9741710 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7933580 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.060765 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1398937 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72620 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.439296 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1398798 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72309 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51399217 # DTB read hits -system.cpu.dtb.read_misses 64403 # DTB read misses -system.cpu.dtb.write_hits 11701345 # DTB write hits -system.cpu.dtb.write_misses 15902 # DTB write misses +system.cpu.dtb.read_hits 51396633 # DTB read hits +system.cpu.dtb.read_misses 64067 # DTB read misses +system.cpu.dtb.write_hits 11699653 # DTB write hits +system.cpu.dtb.write_misses 15746 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3557 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2566 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 409 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3562 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2477 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 410 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1299 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51463620 # DTB read accesses -system.cpu.dtb.write_accesses 11717247 # DTB write accesses +system.cpu.dtb.perms_faults 1368 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51460700 # DTB read accesses +system.cpu.dtb.write_accesses 11715399 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63100562 # DTB hits -system.cpu.dtb.misses 80305 # DTB misses -system.cpu.dtb.accesses 63180867 # DTB accesses -system.cpu.itb.inst_hits 12332677 # ITB inst hits -system.cpu.itb.inst_misses 11271 # ITB inst misses +system.cpu.dtb.hits 63096286 # DTB hits +system.cpu.dtb.misses 79813 # DTB misses +system.cpu.dtb.accesses 63176099 # DTB accesses +system.cpu.itb.inst_hits 12325480 # ITB inst hits +system.cpu.itb.inst_misses 11172 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -250,113 +250,113 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2475 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2484 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2981 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2959 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 12343948 # ITB inst accesses -system.cpu.itb.hits 12332677 # DTB hits -system.cpu.itb.misses 11271 # DTB misses -system.cpu.itb.accesses 12343948 # DTB accesses -system.cpu.numCycles 471840254 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 12336652 # ITB inst accesses +system.cpu.itb.hits 12325480 # DTB hits +system.cpu.itb.misses 11172 # DTB misses +system.cpu.itb.accesses 12336652 # DTB accesses +system.cpu.numCycles 471810648 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30570540 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 96039987 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14675749 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9350279 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21160212 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5300332 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 123049 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 95587623 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2575 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87979 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 195754 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 322 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 12329197 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 900896 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5353 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151365911 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.785063 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.150272 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30565457 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 95962553 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14656582 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9332378 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21150277 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5290628 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 121780 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 95575206 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2486 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87600 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 195549 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 302 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12322026 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 900670 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5254 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 151331210 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.784596 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.149323 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130221030 86.03% 86.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1303083 0.86% 86.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1712964 1.13% 88.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2496255 1.65% 89.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2215475 1.46% 91.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1108052 0.73% 91.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2757455 1.82% 93.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 745629 0.49% 94.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8805968 5.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130196252 86.03% 86.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1300820 0.86% 86.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1711466 1.13% 88.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2496471 1.65% 89.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2227799 1.47% 91.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1107368 0.73% 91.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2755124 1.82% 93.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 745381 0.49% 94.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8790529 5.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151365911 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031103 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.203543 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32532272 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95215917 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19186051 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 962874 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3468797 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1957839 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171569 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 112632707 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 566700 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3468797 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34474935 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36706470 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52522148 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18150584 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6042977 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 106114460 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20538 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1004739 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4062916 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 612 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 110534596 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 485505463 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 485414558 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90905 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78389874 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32144721 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830610 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 737120 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12168217 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20326621 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13518825 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1978093 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2487494 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97939378 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983579 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124329035 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167924 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21751378 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 57069924 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501194 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151365911 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.821381 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.534880 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 151331210 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031065 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.203392 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32520642 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95204800 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19177861 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 964369 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3463538 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1955195 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171536 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 112591879 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 568560 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3463538 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34463537 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36710079 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52505351 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18142460 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6046245 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 106079174 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20496 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1005117 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4065592 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 550 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 110464487 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 485375349 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 485284525 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90824 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78390007 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 32074479 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830001 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 736568 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12176268 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20326431 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13516174 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1981962 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2490949 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97882200 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983364 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124293058 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 166652 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21701894 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 56956786 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 500965 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151331210 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.821331 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.534912 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 107121434 70.77% 70.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13552589 8.95% 79.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7069165 4.67% 84.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5942277 3.93% 88.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12602111 8.33% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2786608 1.84% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1699306 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 465403 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 127018 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 107106602 70.78% 70.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13535056 8.94% 79.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7081946 4.68% 84.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5928653 3.92% 88.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12592468 8.32% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2797891 1.85% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1698330 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 463268 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 126996 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151365911 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151331210 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 60927 0.69% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 61058 0.69% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 2 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available @@ -385,383 +385,383 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8365559 94.64% 95.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 412870 4.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8365937 94.65% 95.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 412109 4.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58631029 47.16% 47.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93272 0.08% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 18 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 18 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52917261 42.56% 90.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12321634 9.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58600875 47.15% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93259 0.08% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 16 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52914481 42.57% 90.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12318607 9.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124329035 # Type of FU issued -system.cpu.iq.rate 0.263498 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8839358 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071096 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 409088132 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 121690697 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85968255 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23084 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12548 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10294 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132792486 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12241 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 623354 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124293058 # Type of FU issued +system.cpu.iq.rate 0.263438 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8839106 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071115 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 408979270 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 121583785 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85924901 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23271 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12514 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10314 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 132756155 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12343 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 622462 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4672096 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6462 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30066 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1786745 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4671879 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6237 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29961 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1784095 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107738 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 893837 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107744 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 893407 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3468797 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27950970 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 433267 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100144689 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 200366 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20326621 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13518825 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1410950 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 112625 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3575 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30066 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 350763 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 269062 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 619825 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121548947 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52086338 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2780088 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3463538 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27955301 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 434033 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100086993 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 200996 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20326431 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13516174 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1411213 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113661 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3507 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29961 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 349347 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 268482 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 617829 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121503786 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52083788 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2789272 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221732 # number of nop insts executed -system.cpu.iew.exec_refs 64299340 # number of memory reference insts executed -system.cpu.iew.exec_branches 11561583 # Number of branches executed -system.cpu.iew.exec_stores 12213002 # Number of stores executed -system.cpu.iew.exec_rate 0.257606 # Inst execution rate -system.cpu.iew.wb_sent 120388158 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85978549 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47221894 # num instructions producing a value -system.cpu.iew.wb_consumers 88170402 # num instructions consuming a value +system.cpu.iew.exec_nop 221429 # number of nop insts executed +system.cpu.iew.exec_refs 64295144 # number of memory reference insts executed +system.cpu.iew.exec_branches 11545908 # Number of branches executed +system.cpu.iew.exec_stores 12211356 # Number of stores executed +system.cpu.iew.exec_rate 0.257527 # Inst execution rate +system.cpu.iew.wb_sent 120344767 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85935215 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47220023 # num instructions producing a value +system.cpu.iew.wb_consumers 88179927 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182220 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535575 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182139 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535496 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 21486542 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482385 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 536246 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147897114 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.525700 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.515001 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 21428892 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482399 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 533951 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147867672 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.525805 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.514985 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120445936 81.44% 81.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13320013 9.01% 90.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3904517 2.64% 93.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2120442 1.43% 94.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1947230 1.32% 95.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 967442 0.65% 96.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1598856 1.08% 97.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 701557 0.47% 98.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2891121 1.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120409023 81.43% 81.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13327348 9.01% 90.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3906728 2.64% 93.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2120462 1.43% 94.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1944541 1.32% 95.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 966495 0.65% 96.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1605335 1.09% 97.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 697137 0.47% 98.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2890603 1.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147897114 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60457960 # Number of instructions committed -system.cpu.commit.committedOps 77749506 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 147867672 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60458083 # Number of instructions committed +system.cpu.commit.committedOps 77749622 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386605 # Number of memory references committed -system.cpu.commit.loads 15654525 # Number of loads committed -system.cpu.commit.membars 403599 # Number of memory barriers committed -system.cpu.commit.branches 9961316 # Number of branches committed +system.cpu.commit.refs 27386631 # Number of memory references committed +system.cpu.commit.loads 15654552 # Number of loads committed +system.cpu.commit.membars 403601 # Number of memory barriers committed +system.cpu.commit.branches 9961338 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68854760 # Number of committed integer instructions. -system.cpu.commit.function_calls 991257 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2891121 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68854854 # Number of committed integer instructions. +system.cpu.commit.function_calls 991262 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2890603 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 242393474 # The number of ROB reads -system.cpu.rob.rob_writes 202038068 # The number of ROB writes -system.cpu.timesIdled 1769308 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320474343 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4594364653 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60307579 # Number of Instructions Simulated -system.cpu.committedOps 77599125 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60307579 # Number of Instructions Simulated -system.cpu.cpi 7.823896 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.823896 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127814 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.127814 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 550318447 # number of integer regfile reads -system.cpu.int_regfile_writes 88458212 # number of integer regfile writes -system.cpu.fp_regfile_reads 8290 # number of floating regfile reads -system.cpu.fp_regfile_writes 2932 # number of floating regfile writes -system.cpu.misc_regfile_reads 30125052 # number of misc regfile reads -system.cpu.misc_regfile_writes 831890 # number of misc regfile writes -system.cpu.icache.replacements 979629 # number of replacements -system.cpu.icache.tagsinuse 511.615707 # Cycle average of tags in use -system.cpu.icache.total_refs 11269534 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 980141 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11.497870 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 242306963 # The number of ROB reads +system.cpu.rob.rob_writes 201917005 # The number of ROB writes +system.cpu.timesIdled 1770758 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320479438 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4594387345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60307702 # Number of Instructions Simulated +system.cpu.committedOps 77599241 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60307702 # Number of Instructions Simulated +system.cpu.cpi 7.823390 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.823390 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127822 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127822 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 550141263 # number of integer regfile reads +system.cpu.int_regfile_writes 88418139 # number of integer regfile writes +system.cpu.fp_regfile_reads 8398 # number of floating regfile reads +system.cpu.fp_regfile_writes 2928 # number of floating regfile writes +system.cpu.misc_regfile_reads 30126321 # number of misc regfile reads +system.cpu.misc_regfile_writes 831893 # number of misc regfile writes +system.cpu.icache.replacements 979850 # number of replacements +system.cpu.icache.tagsinuse 511.615737 # Cycle average of tags in use +system.cpu.icache.total_refs 11261998 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 980362 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11.487591 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 6426355000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.615707 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 511.615737 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.999249 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.999249 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11269534 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11269534 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11269534 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11269534 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11269534 # number of overall hits -system.cpu.icache.overall_hits::total 11269534 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1059538 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1059538 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1059538 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1059538 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1059538 # number of overall misses -system.cpu.icache.overall_misses::total 1059538 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13993400496 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13993400496 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13993400496 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13993400496 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13993400496 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13993400496 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12329072 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12329072 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12329072 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12329072 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12329072 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12329072 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085938 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.085938 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.085938 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.085938 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.085938 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.085938 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13207.077515 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13207.077515 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13207.077515 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13207.077515 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13207.077515 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13207.077515 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4855 # number of cycles access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 11261998 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11261998 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11261998 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11261998 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11261998 # number of overall hits +system.cpu.icache.overall_hits::total 11261998 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1059902 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1059902 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1059902 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1059902 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1059902 # number of overall misses +system.cpu.icache.overall_misses::total 1059902 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13993800493 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13993800493 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13993800493 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13993800493 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13993800493 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13993800493 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12321900 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12321900 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12321900 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12321900 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12321900 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12321900 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086018 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.086018 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.086018 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.086018 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.086018 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.086018 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13202.919226 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13202.919226 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13202.919226 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13202.919226 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13202.919226 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13202.919226 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4527 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 305 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 299 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 15.918033 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 15.140468 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79361 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79361 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79361 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79361 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79361 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79361 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980177 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 980177 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 980177 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 980177 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 980177 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 980177 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11379164996 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11379164996 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11379164996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11379164996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11379164996 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11379164996 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7553500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7553500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7553500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 7553500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079501 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079501 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079501 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.079501 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079501 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.079501 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11609.296072 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11609.296072 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11609.296072 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11609.296072 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11609.296072 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11609.296072 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79506 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79506 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79506 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79506 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79506 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79506 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980396 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 980396 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 980396 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 980396 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 980396 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 980396 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11379943495 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11379943495 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11379943495 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11379943495 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11379943495 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11379943495 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7555000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7555000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7555000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 7555000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079565 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079565 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079565 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.079565 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079565 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.079565 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11607.496864 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11607.496864 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11607.496864 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11607.496864 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11607.496864 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11607.496864 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 64344 # number of replacements -system.cpu.l2cache.tagsinuse 51347.743422 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1885451 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129735 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 14.533094 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2498197459500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 36929.519444 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 26.551079 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000348 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 8159.886035 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6231.786516 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.563500 # Average percentage of cache occupancy +system.cpu.l2cache.replacements 64334 # number of replacements +system.cpu.l2cache.tagsinuse 51346.876619 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1884630 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 129728 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 14.527550 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2498196259500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 36934.415864 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 26.547842 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.003890 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 8157.503084 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6228.405939 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.563574 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000405 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.124510 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.095090 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.783504 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52475 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10450 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 966729 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 387264 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1416918 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 607832 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 607832 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 42 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 42 # number of UpgradeReq hits +system.cpu.l2cache.occ_percent::cpu.inst 0.124474 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.095038 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.783491 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52007 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10206 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 966908 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 387081 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1416202 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 607769 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 607769 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 39 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 39 # number of UpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 11 # number of SCUpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::total 11 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 112902 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 112902 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 52475 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 10450 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 966729 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 500166 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1529820 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 52475 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 10450 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 966729 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 500166 # number of overall hits -system.cpu.l2cache.overall_hits::total 1529820 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 42 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12340 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10707 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 23091 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2921 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2921 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_hits::cpu.data 112939 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 112939 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 52007 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 10206 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 966908 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 500020 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1529141 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 52007 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 10206 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 966908 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 500020 # number of overall hits +system.cpu.l2cache.overall_hits::total 1529141 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 41 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12331 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 10709 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 23084 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2919 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2919 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133192 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133192 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 42 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12340 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143899 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 156283 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 42 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12340 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143899 # number of overall misses -system.cpu.l2cache.overall_misses::total 156283 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3043500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 118000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 696478000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 634908499 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1334547999 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 523500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 523500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6738135500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6738135500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3043500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 118000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 696478000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7373043999 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8072683499 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3043500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 118000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 696478000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7373043999 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8072683499 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52517 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10452 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 979069 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 397971 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1440009 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 607832 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 607832 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2963 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2963 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 133186 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133186 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 41 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 12331 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143895 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 156270 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 41 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 12331 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143895 # number of overall misses +system.cpu.l2cache.overall_misses::total 156270 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2874000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 187000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 694978000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 630766499 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1328805499 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 455500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 455500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6732631500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6732631500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2874000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 187000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 694978000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7363397999 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8061436999 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2874000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 187000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 694978000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7363397999 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8061436999 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52048 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10209 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 979239 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 397790 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1439286 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 607769 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 607769 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2958 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2958 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 14 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 14 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246094 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246094 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52517 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 10452 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 979069 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 644065 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1686103 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52517 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 10452 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 979069 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 644065 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1686103 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000800 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000191 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012604 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026904 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016035 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985825 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985825 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246125 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246125 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52048 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 10209 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 979239 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 643915 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1685411 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52048 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 10209 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 979239 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 643915 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1685411 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000788 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000294 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012592 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026921 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.016039 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986815 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986815 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.214286 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.214286 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541224 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.541224 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000800 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000191 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012604 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.223423 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.092689 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000800 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000191 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012604 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.223423 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.092689 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 72464.285714 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 59000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56440.680713 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59298.449519 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 57795.158243 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 179.219445 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 179.219445 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50589.641270 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50589.641270 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 72464.285714 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56440.680713 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51237.631943 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51654.265013 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 72464.285714 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56440.680713 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51237.631943 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51654.265013 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541132 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.541132 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000788 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000294 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012592 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.223469 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.092719 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000788 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000294 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012592 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.223469 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.092719 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 70097.560976 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 62333.333333 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56360.230314 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58900.597535 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 57563.918688 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 156.046591 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 156.046591 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50550.594657 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50550.594657 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 70097.560976 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 62333.333333 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56360.230314 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51172.021259 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51586.593710 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 70097.560976 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 62333.333333 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56360.230314 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51172.021259 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51586.593710 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -770,109 +770,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59099 # number of writebacks -system.cpu.l2cache.writebacks::total 59099 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 59106 # number of writebacks +system.cpu.l2cache.writebacks::total 59106 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 74 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 42 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12328 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10645 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 23017 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2921 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2921 # number of UpgradeReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 41 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12319 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10648 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 23011 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2919 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2919 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133192 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133192 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 42 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12328 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143837 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 156209 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 42 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12328 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143837 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 156209 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2519791 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 93251 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 542440021 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 499891739 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1044944802 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29212921 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29212921 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133186 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133186 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 41 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12319 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143834 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 156197 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 41 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12319 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143834 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 156197 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2360290 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 149502 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 541016289 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 495761741 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1039287822 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29192919 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29192919 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5078126850 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5078126850 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2519791 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 93251 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 542440021 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5578018589 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6123071652 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2519791 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 93251 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 542440021 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5578018589 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6123071652 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5079330 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002548267 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007627597 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26903237989 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26903237989 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5079330 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193905786256 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193910865586 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000800 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012592 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026748 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015984 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985825 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985825 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5072671631 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5072671631 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2360290 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 149502 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 541016289 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5568433372 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6111959453 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2360290 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 149502 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 541016289 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5568433372 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6111959453 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5080830 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002461767 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007542597 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26898020017 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26898020017 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5080830 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193900481784 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193905562614 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000788 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000294 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012580 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026768 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015988 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986815 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986815 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.214286 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.214286 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541224 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541224 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000800 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012592 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223327 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.092645 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000800 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012592 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223327 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.092645 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 59995.023810 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44000.650633 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46960.238516 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45398.827041 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541132 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541132 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000788 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000294 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012580 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223374 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092676 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000788 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000294 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012580 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223374 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092676 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 57568.048780 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 49834 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43917.224531 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46559.141717 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45164.826474 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38126.365322 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38126.365322 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 59995.023810 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44000.650633 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38780.137162 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39197.944113 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 59995.023810 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44000.650633 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38780.137162 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39197.944113 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38087.123504 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38087.123504 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 57568.048780 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 49834 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43917.224531 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38714.305185 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39129.813332 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 57568.048780 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 49834 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43917.224531 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38714.305185 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39129.813332 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -882,161 +882,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643553 # number of replacements +system.cpu.dcache.replacements 643403 # number of replacements system.cpu.dcache.tagsinuse 511.992821 # Cycle average of tags in use -system.cpu.dcache.total_refs 21507678 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 644065 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.393645 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 21507300 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 643915 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.400837 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 42249000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.992821 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13754193 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13754193 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7259605 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7259605 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 243146 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 243146 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247602 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247602 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21013798 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21013798 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21013798 # number of overall hits -system.cpu.dcache.overall_hits::total 21013798 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 737832 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 737832 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2962746 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2962746 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13508 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13508 # number of LoadLockedReq misses +system.cpu.dcache.ReadReq_hits::cpu.data 13753934 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13753934 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7259500 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7259500 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 243166 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 243166 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247603 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247603 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21013434 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21013434 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21013434 # number of overall hits +system.cpu.dcache.overall_hits::total 21013434 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 737092 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 737092 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2962848 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2962848 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13493 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13493 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 14 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 14 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3700578 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3700578 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3700578 # number of overall misses -system.cpu.dcache.overall_misses::total 3700578 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9800700500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9800700500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 104414938731 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 104414938731 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180553500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 180553500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 3699940 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3699940 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3699940 # number of overall misses +system.cpu.dcache.overall_misses::total 3699940 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9782888500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9782888500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 104355801234 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 104355801234 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 179982000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 179982000 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 218000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 218000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 114215639231 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 114215639231 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 114215639231 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 114215639231 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14492025 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14492025 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222351 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222351 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256654 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256654 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247616 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247616 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24714376 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24714376 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24714376 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24714376 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050913 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050913 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289830 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289830 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052631 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052631 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 114138689734 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 114138689734 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 114138689734 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 114138689734 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14491026 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14491026 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222348 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222348 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256659 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256659 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247617 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247617 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24713374 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24713374 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24713374 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24713374 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050865 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050865 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289840 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289840 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052572 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052572 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000057 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000057 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149734 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149734 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149734 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149734 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13283.105775 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13283.105775 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35242.622463 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35242.622463 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13366.412496 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13366.412496 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.149714 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149714 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149714 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149714 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13272.276052 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13272.276052 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35221.449509 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35221.449509 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13338.916475 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13338.916475 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15571.428571 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15571.428571 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30864.270185 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30864.270185 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30864.270185 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30864.270185 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29973 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 17225 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2670 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 252 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.225843 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 68.353175 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30848.794773 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30848.794773 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30848.794773 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30848.794773 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29383 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 15931 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2645 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 250 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.108885 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 63.724000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607832 # number of writebacks -system.cpu.dcache.writebacks::total 607832 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351946 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 351946 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713780 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2713780 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1332 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1332 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3065726 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3065726 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3065726 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3065726 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385886 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385886 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248966 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248966 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12176 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12176 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 607769 # number of writebacks +system.cpu.dcache.writebacks::total 607769 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351375 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 351375 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713851 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2713851 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1334 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1334 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3065226 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3065226 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3065226 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3065226 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385717 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385717 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248997 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248997 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12159 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12159 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 14 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634852 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634852 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634852 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634852 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4812474000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4812474000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8188067914 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8188067914 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141180000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141180000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 634714 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634714 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634714 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634714 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4806820000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4806820000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8183010414 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8183010414 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 140641000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 140641000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 190000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 190000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13000541914 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13000541914 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13000541914 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13000541914 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395833000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395833000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36742502511 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36742502511 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219138335511 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 219138335511 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026627 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026627 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024355 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024355 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047441 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047441 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12989830414 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12989830414 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12989830414 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12989830414 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395636000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395636000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36713909190 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36713909190 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219109545190 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 219109545190 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026618 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026618 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024358 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024358 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047374 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047374 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000057 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025688 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025688 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025688 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025688 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12471.232437 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12471.232437 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32888.297655 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32888.297655 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11594.940867 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11594.940867 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025683 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025683 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025683 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025683 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12462.038230 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12462.038230 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32863.891589 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32863.891589 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11566.822930 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11566.822930 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13571.428571 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13571.428571 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20478.067194 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20478.067194 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20478.067194 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20478.067194 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20465.643446 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20465.643446 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20465.643446 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20465.643446 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1058,16 +1058,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229610797601 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1229610797601 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229610797601 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1229610797601 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229542911844 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1229542911844 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229542911844 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1229542911844 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83041 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83045 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index d1147fb64..7a69bab79 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.401153 # Number of seconds simulated -sim_ticks 2401153455000 # Number of ticks simulated -final_tick 2401153455000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.401336 # Number of seconds simulated +sim_ticks 2401336466000 # Number of ticks simulated +final_tick 2401336466000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 200255 # Simulator instruction rate (inst/s) -host_op_rate 257182 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7970039029 # Simulator tick rate (ticks/s) -host_mem_usage 397936 # Number of bytes of host memory used -host_seconds 301.27 # Real time elapsed on the host -sim_insts 60331276 # Number of instructions simulated -sim_ops 77481997 # Number of ops (including micro ops) simulated +host_inst_rate 184517 # Simulator instruction rate (inst/s) +host_op_rate 236966 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7343776984 # Simulator tick rate (ticks/s) +host_mem_usage 427572 # Number of bytes of host memory used +host_seconds 326.99 # Real time elapsed on the host +sim_insts 60334938 # Number of instructions simulated +sim_ops 77485485 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -26,149 +26,149 @@ system.realview.nvmem.bw_total::total 8 # To system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 502176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7085840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 500256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7098320 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 85312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 678208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 177920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1312828 # Number of bytes read from this memory -system.physmem.bytes_read::total 124662252 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 502176 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 85312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 177920 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 765408 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3746944 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1490908 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 199452 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1325456 # Number of bytes written to this memory -system.physmem.bytes_written::total 6762760 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 85696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 673152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 178560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1305852 # Number of bytes read from this memory +system.physmem.bytes_read::total 124661996 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 500256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 85696 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 178560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 764512 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3746176 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1490900 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 199456 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1325460 # Number of bytes written to this memory +system.physmem.bytes_written::total 6761992 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14049 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 110750 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14019 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 110945 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1333 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10597 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2780 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 20527 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512434 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58546 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 372727 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 49863 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 331364 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812500 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47818298 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 1339 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10518 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2790 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 20418 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512430 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58534 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 372725 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 49864 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2.data 331365 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812488 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47814654 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 209139 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2951015 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 208324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2955987 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 35530 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 282451 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 267 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 74098 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 546749 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51917653 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 209139 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 35530 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 74098 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 318767 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1560477 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 620913 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 83065 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 552008 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2816463 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1560477 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47818298 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 35687 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 280324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 346 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 74359 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 543802 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51913590 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 208324 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 35687 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 74359 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 318369 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1560038 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 620863 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 83060 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 551968 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2815929 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1560038 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47814654 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 209139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3571928 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 208324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3576850 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 35530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 365516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 267 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 74098 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1098757 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54734116 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 12597264 # Total number of read requests seen -system.physmem.writeReqs 398689 # Total number of write requests seen -system.physmem.cpureqs 55044 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 806224896 # Total number of bytes read from memory -system.physmem.bytesWritten 25516096 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 102751100 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2642476 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu1.inst 35687 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 363384 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 346 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 74359 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1095770 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54729518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 12617991 # Total number of read requests seen +system.physmem.writeReqs 398645 # Total number of write requests seen +system.physmem.cpureqs 54826 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 807551424 # Total number of bytes read from memory +system.physmem.bytesWritten 25513280 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 102907452 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2639540 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 2349 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 787593 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 787339 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 787599 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 787924 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 787752 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 787476 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 787626 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 787678 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 787361 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 786762 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 786761 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 787020 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 787004 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 786857 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 787043 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 787469 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 2346 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 789133 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 788799 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 788883 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 789207 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 789032 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 788708 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 788885 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 788938 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 788613 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 788036 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 788045 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 788296 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 788257 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 788088 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 788320 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 788751 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 24965 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 24827 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 24768 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 25057 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 24837 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 24655 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 24743 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 25297 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 25167 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 24838 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 24777 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 24716 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 24963 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 24891 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 24965 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 25223 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 24839 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 24775 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 25066 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 24855 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 24641 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 25248 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 25299 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 25161 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 24839 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 24628 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 24359 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 24939 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 24843 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 24962 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 25226 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 780903 # Number of times wr buffer was full causing retry -system.physmem.totGap 2400118241500 # Total gap between requests +system.physmem.numWrRetry 14345 # Number of times wr buffer was full causing retry +system.physmem.totGap 2400301266000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 15 # Categorize read packet sizes -system.physmem.readPktSize::3 12562016 # Categorize read packet sizes +system.physmem.readPktSize::3 12582912 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 35233 # Categorize read packet sizes +system.physmem.readPktSize::6 35064 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 381227 # Categorize write packet sizes +system.physmem.writePktSize::2 381229 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 17462 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 814730 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 790825 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 796437 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2993221 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2257059 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2257380 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2245823 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 49187 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 49109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 91199 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 133310 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 91200 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 6958 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 6947 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 6939 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 6938 # What read queue length does an incoming req see +system.physmem.writePktSize::6 17416 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 815827 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 792038 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 797714 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2998166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2260876 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2261203 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2249594 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 49322 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 49193 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 91361 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 133530 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 91345 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 6960 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 6956 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 6952 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 6952 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -185,326 +185,326 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2977 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 2986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3001 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 17344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 17336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2990 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 17339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 17335 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 17331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 17327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 17323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 17319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 17312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 17309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 14405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 17328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 17325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 17317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 17311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 17307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 14404 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 14392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 14382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 14357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 14355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 14353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 14351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 14349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 14347 # What write queue length does an incoming req see -system.physmem.totQLat 276742406750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 352442416750 # Sum of mem lat for all requests -system.physmem.totBusLat 62986320000 # Total cycles spent in databus access -system.physmem.totBankLat 12713690000 # Total cycles spent in bank access -system.physmem.avgQLat 21968.45 # Average queueing delay per request -system.physmem.avgBankLat 1009.24 # Average bank access latency per request +system.physmem.wrQLenPdf::25 14384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 14356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 14354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 14352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 14350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 14348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 14346 # What write queue length does an incoming req see +system.physmem.totQLat 277202035000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 353023032500 # Sum of mem lat for all requests +system.physmem.totBusLat 63089955000 # Total cycles spent in databus access +system.physmem.totBankLat 12731042500 # Total cycles spent in bank access +system.physmem.avgQLat 21968.79 # Average queueing delay per request +system.physmem.avgBankLat 1008.96 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27977.70 # Average memory access latency -system.physmem.avgRdBW 335.77 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 10.63 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 42.79 # Average consumed read bandwidth in MB/s +system.physmem.avgMemAccLat 27977.75 # Average memory access latency +system.physmem.avgRdBW 336.29 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 10.62 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 42.85 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 1.10 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.71 # Data bus utilization in percentage system.physmem.avgRdQLen 0.15 # Average read queue length over time system.physmem.avgWrQLen 0.39 # Average write queue length over time -system.physmem.readRowHits 12542718 # Number of row buffer hits during reads -system.physmem.writeRowHits 392355 # Number of row buffer hits during writes +system.physmem.readRowHits 12563370 # Number of row buffer hits during reads +system.physmem.writeRowHits 392291 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.57 # Row buffer hit rate for reads system.physmem.writeRowHitRate 98.41 # Row buffer hit rate for writes -system.physmem.avgGap 184681.97 # Average gap between requests -system.l2c.replacements 63270 # number of replacements -system.l2c.tagsinuse 50360.149873 # Cycle average of tags in use -system.l2c.total_refs 1749953 # Total number of references to valid blocks. -system.l2c.sampled_refs 128663 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.601059 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2374435295000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36831.103707 # Average occupied blocks per requestor +system.physmem.avgGap 184402.58 # Average gap between requests +system.l2c.replacements 63266 # number of replacements +system.l2c.tagsinuse 50361.629322 # Cycle average of tags in use +system.l2c.total_refs 1749187 # Total number of references to valid blocks. +system.l2c.sampled_refs 128660 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.595422 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2374413040000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36831.903030 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5142.534834 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3774.448687 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 5145.178956 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3770.285257 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 800.238422 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 747.714108 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.dtb.walker 9.797174 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 1464.546789 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 1588.772692 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.561998 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu1.inst 800.231814 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 751.654048 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.dtb.walker 12.723407 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 1461.831435 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 1586.827913 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.562010 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.078469 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.057594 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.078509 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.057530 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.inst 0.012211 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.011409 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.dtb.walker 0.000149 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.022347 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.024243 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.768435 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 9031 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3354 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 461816 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 169436 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 2567 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1134 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 133590 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 65938 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 18164 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 4274 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 284408 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 137993 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1291705 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 597677 # number of Writeback hits -system.l2c.Writeback_hits::total 597677 # number of Writeback hits +system.l2c.occ_percent::cpu1.data 0.011469 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.dtb.walker 0.000194 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.022306 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.024213 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.768457 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 8900 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3213 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 461136 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 170235 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 2537 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1106 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 134711 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 65741 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 17822 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 4190 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 284203 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 137164 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1290958 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 597590 # number of Writeback hits +system.l2c.Writeback_hits::total 597590 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 15 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 32 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 3 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 60640 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 19583 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 33391 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113614 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 9031 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3354 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 461816 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 230076 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 2567 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1134 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 133590 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 85521 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 18164 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 4274 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 284408 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 171384 # number of demand (read+write) hits -system.l2c.demand_hits::total 1405319 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 9031 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3354 # number of overall hits -system.l2c.overall_hits::cpu0.inst 461816 # number of overall hits -system.l2c.overall_hits::cpu0.data 230076 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 2567 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1134 # number of overall hits -system.l2c.overall_hits::cpu1.inst 133590 # number of overall hits -system.l2c.overall_hits::cpu1.data 85521 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 18164 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 4274 # number of overall hits -system.l2c.overall_hits::cpu2.inst 284408 # number of overall hits -system.l2c.overall_hits::cpu2.data 171384 # number of overall hits -system.l2c.overall_hits::total 1405319 # number of overall hits +system.l2c.UpgradeReq_hits::cpu2.data 13 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 30 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu2.data 2 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 61031 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 19032 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 33560 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 113623 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 8900 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3213 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 461136 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 231266 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 2537 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1106 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 134711 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 84773 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 17822 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 4190 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 284203 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 170724 # number of demand (read+write) hits +system.l2c.demand_hits::total 1404581 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 8900 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3213 # number of overall hits +system.l2c.overall_hits::cpu0.inst 461136 # number of overall hits +system.l2c.overall_hits::cpu0.data 231266 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 2537 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1106 # number of overall hits +system.l2c.overall_hits::cpu1.inst 134711 # number of overall hits +system.l2c.overall_hits::cpu1.data 84773 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 17822 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 4190 # number of overall hits +system.l2c.overall_hits::cpu2.inst 284203 # number of overall hits +system.l2c.overall_hits::cpu2.data 170724 # number of overall hits +system.l2c.overall_hits::total 1404581 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7433 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6366 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 7403 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6349 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1333 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1201 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 10 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 2780 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 2564 # number of ReadReq misses -system.l2c.ReadReq_misses::total 21691 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1419 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 511 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 974 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2904 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 105149 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 9669 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 18547 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133365 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu1.inst 1339 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1210 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 13 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 2790 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 2574 # number of ReadReq misses +system.l2c.ReadReq_misses::total 21682 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1421 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 495 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 987 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2903 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 105359 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 9583 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 18426 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133368 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7433 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 111515 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 7403 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 111708 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1333 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 10870 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 10 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 2780 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 21111 # number of demand (read+write) misses -system.l2c.demand_misses::total 155056 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1339 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 10793 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.dtb.walker 13 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 2790 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 21000 # number of demand (read+write) misses +system.l2c.demand_misses::total 155050 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7433 # number of overall misses -system.l2c.overall_misses::cpu0.data 111515 # number of overall misses +system.l2c.overall_misses::cpu0.inst 7403 # number of overall misses +system.l2c.overall_misses::cpu0.data 111708 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1333 # number of overall misses -system.l2c.overall_misses::cpu1.data 10870 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 10 # number of overall misses -system.l2c.overall_misses::cpu2.inst 2780 # number of overall misses -system.l2c.overall_misses::cpu2.data 21111 # number of overall misses -system.l2c.overall_misses::total 155056 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1339 # number of overall misses +system.l2c.overall_misses::cpu1.data 10793 # number of overall misses +system.l2c.overall_misses::cpu2.dtb.walker 13 # number of overall misses +system.l2c.overall_misses::cpu2.inst 2790 # number of overall misses +system.l2c.overall_misses::cpu2.data 21000 # number of overall misses +system.l2c.overall_misses::total 155050 # number of overall misses system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 69000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 75831000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 69197000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 884500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 173677500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 153775000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 473434000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 137000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 92000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 229000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 434064000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 982245000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1416309000 # number of ReadExReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 76508500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 69917500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 783000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 178873500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 152904999 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 479056499 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 91500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 69000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 160500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 429692000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 973653500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1403345500 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 69000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 75831000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 503261000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 884500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 173677500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 1136020000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 1889743000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 76508500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 499609500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 783000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 178873500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1126558499 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 1882401999 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 69000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 75831000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 503261000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 884500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 173677500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 1136020000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 1889743000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 9032 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 3356 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 469249 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 175802 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 2568 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 1134 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 134923 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 67139 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 18174 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 4274 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 287188 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 140557 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1313396 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 597677 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 597677 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1432 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 515 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 989 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2936 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu2.data 3 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 165789 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 29252 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 51938 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246979 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 9032 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 3356 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 469249 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 341591 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 2568 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 1134 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 134923 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 96391 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 18174 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 4274 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 287188 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 192495 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1560375 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 9032 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 3356 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 469249 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 341591 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 2568 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 1134 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 134923 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 96391 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 18174 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 4274 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 287188 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 192495 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1560375 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000111 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000596 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015840 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.036211 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000389 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.009880 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.017888 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000550 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.009680 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.018242 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016515 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990922 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.992233 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.984833 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.989101 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.634234 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.330542 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.357099 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.539985 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000111 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000596 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015840 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.326458 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000389 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.009880 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.112770 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000550 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.009680 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.109670 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.099371 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000111 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000596 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015840 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.326458 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000389 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.009880 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.112770 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000550 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.009680 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.109670 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.099371 # miss rate for overall accesses +system.l2c.overall_miss_latency::cpu1.inst 76508500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 499609500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.dtb.walker 783000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 178873500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1126558499 # number of overall miss cycles +system.l2c.overall_miss_latency::total 1882401999 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 8901 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 3215 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 468539 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 176584 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 2538 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1106 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 136050 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 66951 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 17835 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 4190 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 286993 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 139738 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1312640 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 597590 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 597590 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1434 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 499 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 1000 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2933 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu2.data 2 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 166390 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 28615 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 51986 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246991 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 8901 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 3215 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 468539 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 342974 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 2538 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1106 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 136050 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 95566 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 17835 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 4190 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 286993 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 191724 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1559631 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 8901 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 3215 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 468539 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 342974 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 2538 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1106 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 136050 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 95566 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 17835 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 4190 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 286993 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 191724 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1559631 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000112 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000622 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015800 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.035955 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000394 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.009842 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.018073 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000729 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.009721 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.018420 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016518 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990934 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991984 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.987000 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.989772 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.633205 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.334894 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.354442 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.539971 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000112 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000622 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015800 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.325704 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000394 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.009842 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.112938 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000729 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.009721 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.109532 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.099415 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000112 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000622 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015800 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.325704 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000394 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.009842 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.112938 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000729 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.009721 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.109532 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.099415 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 69000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 56887.471868 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 57616.153206 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 88450 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 62473.920863 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 59974.648986 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 21826.287400 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 268.101761 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 94.455852 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 78.856749 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 44892.336333 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52959.777862 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 10619.795299 # average ReadExReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 57138.536221 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 57783.057851 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 60230.769231 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 64112.365591 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 59403.651515 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 22094.663730 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 184.848485 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 69.908815 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 55.287633 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 44838.985704 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52841.284055 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 10522.355438 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 69000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 56887.471868 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 46298.160074 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 88450 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 62473.920863 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 53811.756904 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 12187.487101 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 57138.536221 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 46290.141759 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 60230.769231 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 64112.365591 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 53645.642810 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 12140.612699 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 69000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 56887.471868 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 46298.160074 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 88450 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 62473.920863 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 53811.756904 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 12187.487101 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 57138.536221 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 46290.141759 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 60230.769231 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 64112.365591 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 53645.642810 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 12140.612699 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -513,8 +513,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 58546 # number of writebacks -system.l2c.writebacks::total 58546 # number of writebacks +system.l2c.writebacks::writebacks 58534 # number of writebacks +system.l2c.writebacks::total 58534 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu2.data 8 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu2.data 8 # number of demand (read+write) MSHR hits @@ -522,122 +522,122 @@ system.l2c.demand_mshr_hits::total 8 # nu system.l2c.overall_mshr_hits::cpu2.data 8 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 8 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 1333 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1201 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 10 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 2780 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 2556 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 7881 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 511 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 974 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 1485 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 9669 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 18547 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 28216 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 1339 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1210 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 13 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 2790 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 2566 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 7919 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 495 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 987 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 1482 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 9583 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 18426 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 28009 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1333 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 10870 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.dtb.walker 10 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 2780 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 21103 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 36097 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1339 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 10793 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 13 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 2790 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 20992 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 35928 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1333 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 10870 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.dtb.walker 10 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 2780 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 21103 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 36097 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1339 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 10793 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 13 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 2790 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 20992 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 35928 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 56251 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 59114583 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 54201951 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 759510 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 139044199 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 121569649 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 374746143 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5152487 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 9740974 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 14893461 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 313671410 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 751003559 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1064674969 # number of ReadExReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 59716089 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 54808460 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 621263 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 144123701 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 120589158 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 379914922 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4988470 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 9870987 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 14859457 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 310362321 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 743903257 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1054265578 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 56251 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 59114583 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 367873361 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 759510 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 139044199 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 872573208 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1439421112 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 59716089 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 365170781 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 621263 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 144123701 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 864492415 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1434180500 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 56251 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 59114583 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 367873361 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 759510 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 139044199 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 872573208 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1439421112 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25246007500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26571413012 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 51817420512 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 647804863 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 9786959359 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 10434764222 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 25893812363 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 36358372371 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 62252184734 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000389 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009880 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017888 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000550 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.009680 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018185 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.006000 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.992233 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.984833 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.505790 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.330542 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.357099 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.114245 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000389 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009880 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.112770 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000550 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.009680 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.109629 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.023134 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000389 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009880 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.112770 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000550 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.009680 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.109629 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.023134 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_latency::cpu1.inst 59716089 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 365170781 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 621263 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 144123701 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 864492415 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1434180500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25160642000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26578724012 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 51739366012 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 647954364 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 9829694360 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 10477648724 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 25808596364 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 36408418372 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 62217014736 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000394 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009842 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.018073 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000729 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.009721 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018363 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.006033 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991984 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.987000 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.505285 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.334894 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.354442 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.113401 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000394 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009842 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.112938 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000729 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.009721 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.109491 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.023036 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000394 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009842 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.112938 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000729 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.009721 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.109491 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.023036 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 44347.024006 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45130.683597 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 75951 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 50015.898921 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 47562.460485 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 47550.582794 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10083.144814 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 44597.527259 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45296.247934 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 47789.461538 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 51657.240502 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 46994.995323 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 47975.113272 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10077.717172 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10029.266667 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 32440.935981 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40491.915620 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 37733.022718 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10026.624157 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 32386.759992 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40372.476772 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 37640.243422 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 44347.024006 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33842.995492 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 75951 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 50015.898921 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41348.301568 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39876.474832 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 44597.527259 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33834.038821 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 47789.461538 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 51657.240502 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41181.993855 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39918.183589 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 44347.024006 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33842.995492 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 75951 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 50015.898921 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41348.301568 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39876.474832 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 44597.527259 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33834.038821 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 47789.461538 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 51657.240502 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41181.993855 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39918.183589 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -656,436 +656,436 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8076292 # DTB read hits -system.cpu0.dtb.read_misses 6232 # DTB read misses -system.cpu0.dtb.write_hits 6627548 # DTB write hits -system.cpu0.dtb.write_misses 2039 # DTB write misses +system.cpu0.dtb.read_hits 8079595 # DTB read hits +system.cpu0.dtb.read_misses 6254 # DTB read misses +system.cpu0.dtb.write_hits 6630051 # DTB write hits +system.cpu0.dtb.write_misses 2055 # DTB write misses system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 695 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 718 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5689 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5732 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 126 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 128 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8082524 # DTB read accesses -system.cpu0.dtb.write_accesses 6629587 # DTB write accesses +system.cpu0.dtb.perms_faults 221 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8085849 # DTB read accesses +system.cpu0.dtb.write_accesses 6632106 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14703840 # DTB hits -system.cpu0.dtb.misses 8271 # DTB misses -system.cpu0.dtb.accesses 14712111 # DTB accesses -system.cpu0.itb.inst_hits 32739442 # ITB inst hits -system.cpu0.itb.inst_misses 3479 # ITB inst misses +system.cpu0.dtb.hits 14709646 # DTB hits +system.cpu0.dtb.misses 8309 # DTB misses +system.cpu0.dtb.accesses 14717955 # DTB accesses +system.cpu0.itb.inst_hits 32707746 # ITB inst hits +system.cpu0.itb.inst_misses 3496 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 695 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 718 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2588 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2601 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32742921 # ITB inst accesses -system.cpu0.itb.hits 32739442 # DTB hits -system.cpu0.itb.misses 3479 # DTB misses -system.cpu0.itb.accesses 32742921 # DTB accesses -system.cpu0.numCycles 113988971 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32711242 # ITB inst accesses +system.cpu0.itb.hits 32707746 # DTB hits +system.cpu0.itb.misses 3496 # DTB misses +system.cpu0.itb.accesses 32711242 # DTB accesses +system.cpu0.numCycles 113988289 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 32238592 # Number of instructions committed -system.cpu0.committedOps 42426848 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37569901 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5136 # Number of float alu accesses -system.cpu0.num_func_calls 1188707 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4243711 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37569901 # number of integer instructions -system.cpu0.num_fp_insts 5136 # number of float instructions -system.cpu0.num_int_register_reads 191405612 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39677066 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3646 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1492 # number of times the floating registers were written -system.cpu0.num_mem_refs 15367259 # number of memory refs -system.cpu0.num_load_insts 8443691 # Number of load instructions -system.cpu0.num_store_insts 6923568 # Number of store instructions -system.cpu0.num_idle_cycles 13415307720.919615 # Number of idle cycles -system.cpu0.num_busy_cycles -13301318749.919615 # Number of busy cycles -system.cpu0.not_idle_fraction -116.689524 # Percentage of non-idle cycles -system.cpu0.idle_fraction 117.689524 # Percentage of idle cycles +system.cpu0.committedInsts 32205724 # Number of instructions committed +system.cpu0.committedOps 42407604 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37554027 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5120 # Number of float alu accesses +system.cpu0.num_func_calls 1187729 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4239348 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37554027 # number of integer instructions +system.cpu0.num_fp_insts 5120 # number of float instructions +system.cpu0.num_int_register_reads 191333530 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39644160 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3702 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1420 # number of times the floating registers were written +system.cpu0.num_mem_refs 15372618 # number of memory refs +system.cpu0.num_load_insts 8447076 # Number of load instructions +system.cpu0.num_store_insts 6925542 # Number of store instructions +system.cpu0.num_idle_cycles 13415449988.373053 # Number of idle cycles +system.cpu0.num_busy_cycles -13301461699.373053 # Number of busy cycles +system.cpu0.not_idle_fraction -116.691476 # Percentage of non-idle cycles +system.cpu0.idle_fraction 117.691476 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 82893 # number of quiesce instructions executed -system.cpu0.icache.replacements 892272 # number of replacements -system.cpu0.icache.tagsinuse 511.604135 # Cycle average of tags in use -system.cpu0.icache.total_refs 44302234 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 892784 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 49.622567 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 82896 # number of quiesce instructions executed +system.cpu0.icache.replacements 892496 # number of replacements +system.cpu0.icache.tagsinuse 511.604237 # Cycle average of tags in use +system.cpu0.icache.total_refs 44360992 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 893008 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 49.675918 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 8108819000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 477.646185 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 17.780881 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu2.inst 16.177069 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.932903 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.034728 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu2.inst 0.031596 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::cpu0.inst 478.427369 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 17.974038 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu2.inst 15.202829 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.934428 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.035106 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu2.inst 0.029693 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.999227 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 32272136 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 8284220 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3745878 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 44302234 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 32272136 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 8284220 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3745878 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 44302234 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 32272136 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 8284220 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 3745878 # number of overall hits -system.cpu0.icache.overall_hits::total 44302234 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 469978 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 135194 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 311533 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 916705 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 469978 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 135194 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 311533 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 916705 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 469978 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 135194 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 311533 # number of overall misses -system.cpu0.icache.overall_misses::total 916705 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1823611000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4151773488 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5975384488 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1823611000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4151773488 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5975384488 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1823611000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4151773488 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5975384488 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 32742114 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 8419414 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 4057411 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 45218939 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 32742114 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 8419414 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 4057411 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 45218939 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 32742114 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 8419414 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 4057411 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 45218939 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014354 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016057 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076781 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.020273 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014354 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016057 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076781 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.020273 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014354 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016057 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076781 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.020273 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13488.845659 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13326.913964 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6518.328675 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13488.845659 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13326.913964 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6518.328675 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13488.845659 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13326.913964 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6518.328675 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2346 # number of cycles access was blocked +system.cpu0.icache.ReadReq_hits::cpu0.inst 32241170 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 8377396 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 3742426 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 44360992 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 32241170 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 8377396 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 3742426 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 44360992 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 32241170 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 8377396 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 3742426 # number of overall hits +system.cpu0.icache.overall_hits::total 44360992 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 469261 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 136323 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 311228 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 916812 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 469261 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 136323 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 311228 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 916812 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 469261 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 136323 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 311228 # number of overall misses +system.cpu0.icache.overall_misses::total 916812 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1838935000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4152917486 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5991852486 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 1838935000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 4152917486 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5991852486 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 1838935000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 4152917486 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5991852486 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 32710431 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 8513719 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 4053654 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 45277804 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 32710431 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 8513719 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 4053654 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 45277804 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 32710431 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 8513719 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 4053654 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 45277804 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014346 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016012 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076777 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.020249 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014346 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016012 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076777 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.020249 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014346 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016012 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076777 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.020249 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13489.543217 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13343.649948 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 6535.530170 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13489.543217 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13343.649948 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6535.530170 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13489.543217 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13343.649948 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6535.530170 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3861 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 187 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 220 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.545455 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.550000 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 23911 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 23911 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 23911 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 23911 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 23911 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 23911 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 135194 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 287622 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 422816 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 135194 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 287622 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 422816 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 135194 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 287622 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 422816 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1553223000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3386037488 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4939260488 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1553223000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3386037488 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4939260488 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1553223000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3386037488 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4939260488 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016057 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.070888 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009350 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016057 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.070888 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009350 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016057 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.070888 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009350 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11488.845659 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11772.526052 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11681.820196 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11488.845659 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11772.526052 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11681.820196 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11488.845659 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11772.526052 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11681.820196 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 23796 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 23796 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 23796 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 23796 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 23796 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 23796 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 136323 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 287432 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 423755 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 136323 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 287432 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 423755 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 136323 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 287432 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 423755 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1566289000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3388078986 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4954367986 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1566289000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3388078986 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4954367986 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1566289000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3388078986 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4954367986 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016012 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.070907 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009359 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016012 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.070907 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009359 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016012 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.070907 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009359 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11489.543217 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11787.410539 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11691.585907 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11489.543217 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11787.410539 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11691.585907 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11489.543217 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11787.410539 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11691.585907 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 629965 # number of replacements +system.cpu0.dcache.replacements 629752 # number of replacements system.cpu0.dcache.tagsinuse 511.997116 # Cycle average of tags in use -system.cpu0.dcache.total_refs 23216121 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 630477 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 36.823105 # Average number of references to valid blocks. +system.cpu0.dcache.total_refs 23211225 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 630264 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 36.827782 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 495.769504 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 9.745655 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu2.data 6.481956 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.968300 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.019034 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu2.data 0.012660 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 495.729006 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 9.821503 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu2.data 6.446607 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.968221 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.019183 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu2.data 0.012591 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6957822 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1890811 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4457613 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13306246 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5949587 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1349737 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2121933 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9421257 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131174 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 34256 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 72800 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 238230 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137548 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 35976 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 73869 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247393 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12907409 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 3240548 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 6579546 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 22727503 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12907409 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 3240548 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 6579546 # number of overall hits -system.cpu0.dcache.overall_hits::total 22727503 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 169428 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 65419 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 282959 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 517806 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 167221 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 29767 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 598117 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 795105 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6374 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1720 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3877 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11971 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 3 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 336649 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 95186 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 881076 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1312911 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 336649 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 95186 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 881076 # number of overall misses -system.cpu0.dcache.overall_misses::total 1312911 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 911962500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 4076352000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4988314500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 730880500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 18449241407 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 19180121907 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 22516000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 52369500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 74885500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 39000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 39000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 1642843000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 22525593407 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 24168436407 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 1642843000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 22525593407 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 24168436407 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7127250 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1956230 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4740572 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13824052 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 6116808 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1379504 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2720050 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10216362 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 137548 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 35976 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 76677 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 250201 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137548 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 35976 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 73872 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247396 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13244058 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 3335734 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7460622 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24040414 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13244058 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 3335734 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7460622 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24040414 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.023772 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033441 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.059689 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.037457 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027338 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021578 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.219892 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.077827 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046340 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.047810 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050563 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047846 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000041 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000012 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025419 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028535 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.118097 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.054613 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.025419 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028535 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.118097 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.054613 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13940.330791 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14406.157783 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 9633.558707 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 24553.381261 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30845.539262 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 24122.753482 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13090.697674 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13507.737942 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6255.575975 # average LoadLockedReq miss latency +system.cpu0.dcache.ReadReq_hits::cpu0.data 6959921 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1905228 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4437258 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13302407 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5951579 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1349529 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 2119159 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9420267 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131066 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 34182 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 72930 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 238178 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137461 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 35898 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 74040 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247399 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12911500 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 3254757 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 6556417 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 22722674 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12911500 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 3254757 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 6556417 # number of overall hits +system.cpu0.dcache.overall_hits::total 22722674 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 170189 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 65235 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 281776 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 517200 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 167824 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 29114 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 599232 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 796170 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6395 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1716 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3875 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 11986 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu2.data 2 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 338013 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 94349 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 881008 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1313370 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 338013 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 94349 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 881008 # number of overall misses +system.cpu0.dcache.overall_misses::total 1313370 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 910187500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 4059279000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4969466500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 718682500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 18333372895 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 19052055395 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 22464000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 52254000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 74718000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 26000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 1628870000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 22392651895 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 24021521895 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 1628870000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 22392651895 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 24021521895 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7130110 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 1970463 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 4719034 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13819607 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 6119403 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 1378643 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 2718391 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10216437 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 137461 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 35898 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 76805 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 250164 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137461 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 35898 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 74042 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247401 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13249513 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 3349106 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 7437425 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24036044 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13249513 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 3349106 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 7437425 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24036044 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.023869 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033106 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.059711 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.037425 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027425 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021118 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.220436 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.077930 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046522 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.047802 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050452 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047913 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000027 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025511 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028171 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.118456 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.054642 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.025511 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028171 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.118456 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.054642 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13952.441174 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14406.049486 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 9608.403906 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 24685.117126 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30594.782814 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 23929.632359 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13090.909091 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13484.903226 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6233.772735 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17259.292333 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25566.004984 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 18408.282364 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17259.292333 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25566.004984 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 18408.282364 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 9007 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1035 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 1102 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 47 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.173321 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 22.021277 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17264.305928 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25417.081224 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 18289.988271 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17264.305928 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25417.081224 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 18289.988271 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 9551 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1722 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 1090 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 46 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.762385 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 37.434783 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 597677 # number of writebacks -system.cpu0.dcache.writebacks::total 597677 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 145837 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 145837 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 545226 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 545226 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 406 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 406 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 691063 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 691063 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 691063 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 691063 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 65419 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 137122 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 202541 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29767 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 52891 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 82658 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1720 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3471 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5191 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 3 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 95186 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 190013 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 285199 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 95186 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 190013 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 285199 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 781124500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1779796500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2560921000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 671346500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1430416990 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2101763490 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19076000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 40648000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 59724000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 33000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 33000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1452471000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3210213490 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 4662684490 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1452471000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3210213490 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 4662684490 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27580693500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 29009829000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56590522500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1281089000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 14115638625 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15396727625 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28861782500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 43125467625 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71987250125 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033441 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.028925 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014651 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021578 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019445 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008091 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.047810 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.045268 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020747 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000041 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000012 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028535 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025469 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011863 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028535 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025469 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011863 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11940.330791 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12979.656802 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12643.963444 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22553.381261 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 27044.619879 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25427.224104 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11090.697674 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11710.746183 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11505.297631 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 597590 # number of writebacks +system.cpu0.dcache.writebacks::total 597590 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 145454 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 145454 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 546284 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 546284 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 421 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 421 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 691738 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 691738 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 691738 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 691738 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 65235 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 136322 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 201557 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29114 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 52948 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 82062 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1716 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3454 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5170 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 94349 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 189270 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 283619 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 94349 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 189270 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 283619 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 779717500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1769361500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2549079000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 660454500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1423557990 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2084012490 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19032000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 40419500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 59451500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1440172000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3192919490 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 4633091490 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1440172000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3192919490 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 4633091490 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27487398000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 29017842000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56505240000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1281263000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 14147361293 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15428624293 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28768661000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 43165203293 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71933864293 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033106 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.028888 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014585 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021118 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019478 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008032 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.047802 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.044971 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020666 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000027 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028171 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025448 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011800 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028171 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025448 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011800 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11952.441174 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12979.280674 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12646.938583 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22685.117126 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26885.963398 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25395.584924 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11090.909091 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11702.229299 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11499.323017 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15259.292333 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16894.704520 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16348.880922 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15259.292333 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16894.704520 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16348.880922 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15264.305928 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16869.654409 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16335.617466 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15264.305928 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16869.654409 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16335.617466 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1098,218 +1098,218 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2171794 # DTB read hits -system.cpu1.dtb.read_misses 2101 # DTB read misses -system.cpu1.dtb.write_hits 1466259 # DTB write hits -system.cpu1.dtb.write_misses 389 # DTB write misses +system.cpu1.dtb.read_hits 2185339 # DTB read hits +system.cpu1.dtb.read_misses 2099 # DTB read misses +system.cpu1.dtb.write_hits 1465312 # DTB write hits +system.cpu1.dtb.write_misses 382 # DTB write misses system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1716 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 1728 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 36 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 37 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 80 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2173895 # DTB read accesses -system.cpu1.dtb.write_accesses 1466648 # DTB write accesses +system.cpu1.dtb.perms_faults 70 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 2187438 # DTB read accesses +system.cpu1.dtb.write_accesses 1465694 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3638053 # DTB hits -system.cpu1.dtb.misses 2490 # DTB misses -system.cpu1.dtb.accesses 3640543 # DTB accesses -system.cpu1.itb.inst_hits 8419414 # ITB inst hits -system.cpu1.itb.inst_misses 1129 # ITB inst misses +system.cpu1.dtb.hits 3650651 # DTB hits +system.cpu1.dtb.misses 2481 # DTB misses +system.cpu1.dtb.accesses 3653132 # DTB accesses +system.cpu1.itb.inst_hits 8513719 # ITB inst hits +system.cpu1.itb.inst_misses 1131 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 827 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 841 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8420543 # ITB inst accesses -system.cpu1.itb.hits 8419414 # DTB hits -system.cpu1.itb.misses 1129 # DTB misses -system.cpu1.itb.accesses 8420543 # DTB accesses -system.cpu1.numCycles 574251142 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8514850 # ITB inst accesses +system.cpu1.itb.hits 8513719 # DTB hits +system.cpu1.itb.misses 1131 # DTB misses +system.cpu1.itb.accesses 8514850 # DTB accesses +system.cpu1.numCycles 574637078 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 8213191 # Number of instructions committed -system.cpu1.committedOps 10466435 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9372254 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 2062 # Number of float alu accesses -system.cpu1.num_func_calls 317964 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1146067 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9372254 # number of integer instructions -system.cpu1.num_fp_insts 2062 # number of float instructions -system.cpu1.num_int_register_reads 54024867 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10146423 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1613 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 450 # number of times the floating registers were written -system.cpu1.num_mem_refs 3811897 # number of memory refs -system.cpu1.num_load_insts 2267853 # Number of load instructions -system.cpu1.num_store_insts 1544044 # Number of store instructions -system.cpu1.num_idle_cycles 537580210.089888 # Number of idle cycles -system.cpu1.num_busy_cycles 36670931.910112 # Number of busy cycles -system.cpu1.not_idle_fraction 0.063859 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.936141 # Percentage of idle cycles +system.cpu1.committedInsts 8294211 # Number of instructions committed +system.cpu1.committedOps 10531754 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9421872 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 2078 # Number of float alu accesses +system.cpu1.num_func_calls 319530 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1158784 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9421872 # number of integer instructions +system.cpu1.num_fp_insts 2078 # number of float instructions +system.cpu1.num_int_register_reads 54337439 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10233618 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1565 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 514 # number of times the floating registers were written +system.cpu1.num_mem_refs 3824850 # number of memory refs +system.cpu1.num_load_insts 2281405 # Number of load instructions +system.cpu1.num_store_insts 1543445 # Number of store instructions +system.cpu1.num_idle_cycles 540667957.850120 # Number of idle cycles +system.cpu1.num_busy_cycles 33969120.149880 # Number of busy cycles +system.cpu1.not_idle_fraction 0.059114 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.940886 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4709991 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3829375 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 221875 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3139297 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2527298 # Number of BTB hits +system.cpu2.branchPred.lookups 4687055 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3808844 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 220686 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3132450 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2515746 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 80.505221 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 410694 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21534 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 80.312407 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 409998 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21415 # Number of incorrect RAS predictions. system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10865348 # DTB read hits -system.cpu2.dtb.read_misses 22611 # DTB read misses -system.cpu2.dtb.write_hits 3267482 # DTB write hits -system.cpu2.dtb.write_misses 5780 # DTB write misses +system.cpu2.dtb.read_hits 10844149 # DTB read hits +system.cpu2.dtb.read_misses 22603 # DTB read misses +system.cpu2.dtb.write_hits 3263914 # DTB write hits +system.cpu2.dtb.write_misses 5857 # DTB write misses system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 504 # Number of times TLB was flushed by MVA & ASID -system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID +system.cpu2.dtb.flush_tlb_mva_asid 500 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID system.cpu2.dtb.flush_entries 2308 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 877 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 154 # Number of TLB faults due to prefetch +system.cpu2.dtb.align_faults 825 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 159 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 449 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10887959 # DTB read accesses -system.cpu2.dtb.write_accesses 3273262 # DTB write accesses +system.cpu2.dtb.perms_faults 466 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10866752 # DTB read accesses +system.cpu2.dtb.write_accesses 3269771 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14132830 # DTB hits -system.cpu2.dtb.misses 28391 # DTB misses -system.cpu2.dtb.accesses 14161221 # DTB accesses -system.cpu2.itb.inst_hits 4058794 # ITB inst hits -system.cpu2.itb.inst_misses 4496 # ITB inst misses +system.cpu2.dtb.hits 14108063 # DTB hits +system.cpu2.dtb.misses 28460 # DTB misses +system.cpu2.dtb.accesses 14136523 # DTB accesses +system.cpu2.itb.inst_hits 4055013 # ITB inst hits +system.cpu2.itb.inst_misses 4560 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 504 # Number of times TLB was flushed by MVA & ASID -system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1567 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_tlb_mva_asid 500 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID +system.cpu2.itb.flush_entries 1575 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1061 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1017 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4063290 # ITB inst accesses -system.cpu2.itb.hits 4058794 # DTB hits -system.cpu2.itb.misses 4496 # DTB misses -system.cpu2.itb.accesses 4063290 # DTB accesses -system.cpu2.numCycles 88265633 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4059573 # ITB inst accesses +system.cpu2.itb.hits 4055013 # DTB hits +system.cpu2.itb.misses 4560 # DTB misses +system.cpu2.itb.accesses 4059573 # DTB accesses +system.cpu2.numCycles 88254759 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9438008 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32342862 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4709991 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2937992 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6815885 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1813158 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 52200 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 19319240 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 204 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 990 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 33528 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 57014 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 272 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4057414 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 309972 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1938 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 36961797 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.050032 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.436638 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9429776 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32237470 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4687055 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2925744 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6801535 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1807730 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 51877 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 19337159 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 319 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 987 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 33898 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 57137 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 401 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4053658 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 309769 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1939 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 36952841 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.047181 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.432989 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30150982 81.57% 81.57% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 382433 1.03% 82.61% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 508858 1.38% 83.98% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 812110 2.20% 86.18% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 648973 1.76% 87.94% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 344473 0.93% 88.87% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1008779 2.73% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 237853 0.64% 92.24% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2867336 7.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30156381 81.61% 81.61% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 380935 1.03% 82.64% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 507291 1.37% 84.01% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 812322 2.20% 86.21% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 657376 1.78% 87.99% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 343317 0.93% 88.92% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1003055 2.71% 91.63% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 237893 0.64% 92.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2854271 7.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 36961797 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.053362 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.366426 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10050266 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19257143 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6169060 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 292369 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1191852 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 610072 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 53860 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36648451 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 182697 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1191852 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10623039 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6559507 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11162234 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5869128 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1554979 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34406679 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2425 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 416595 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 876326 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 106 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 36902595 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 157291448 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 157264010 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 27438 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 25708511 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 11194083 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 230845 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 207258 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3329183 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6509687 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3839458 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 526321 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 767723 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 31666176 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 511259 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34215654 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 53951 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7402351 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19875920 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 155450 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 36961797 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.925703 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.580463 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 36952841 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.053108 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.365277 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10041048 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19275643 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6155197 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 292391 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1187539 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 608222 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 53447 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36559853 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 181421 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1187539 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10612647 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6555727 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11181502 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5856266 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1558172 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34319277 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2410 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 422959 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 872955 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 107 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 36779919 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 156919879 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 156892837 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 27042 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 25654971 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 11124947 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 231561 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 207869 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3330119 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6484809 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3835337 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 528235 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 785937 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 31561835 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 513874 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34144653 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 53839 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7344925 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19731311 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 156774 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 36952841 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.924006 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.578400 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24411546 66.05% 66.05% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3907285 10.57% 76.62% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2341872 6.34% 82.95% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 1974558 5.34% 88.29% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2782177 7.53% 95.82% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 896473 2.43% 98.25% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 480042 1.30% 99.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 133126 0.36% 99.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 34718 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24411645 66.06% 66.06% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3911686 10.59% 76.65% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2348900 6.36% 83.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 1966009 5.32% 88.32% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2782600 7.53% 95.85% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 888012 2.40% 98.26% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 476049 1.29% 99.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 133134 0.36% 99.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 34806 0.09% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 36961797 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 36952841 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 16658 1.09% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 16764 1.09% 1.09% # attempts to use FU when none available system.cpu2.iq.fu_full::IntMult 0 0.00% 1.09% # attempts to use FU when none available system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.09% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.09% # attempts to use FU when none available @@ -1338,148 +1338,148 @@ system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.09% # at system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.09% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.09% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1407260 91.71% 92.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 110601 7.21% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1407478 91.75% 92.84% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 109853 7.16% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 61295 0.18% 0.18% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19329502 56.49% 56.67% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 25951 0.08% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 9 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 8 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 376 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11364260 33.21% 89.96% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3434245 10.04% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 61419 0.18% 0.18% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19283233 56.48% 56.65% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 25726 0.08% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 6 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 6 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 370 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11342799 33.22% 89.95% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3431088 10.05% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34215654 # Type of FU issued -system.cpu2.iq.rate 0.387644 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1534519 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.044848 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 107003021 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39584963 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 27346219 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 6827 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3771 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3100 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 35685269 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 3609 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 207108 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34144653 # Type of FU issued +system.cpu2.iq.rate 0.386887 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1534095 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.044929 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 106851627 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39425823 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 27268218 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 6778 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 3706 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3093 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 35613758 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 3571 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 205973 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1576105 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1884 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9268 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 580803 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1568043 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1874 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9216 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 577978 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5370889 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 352686 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5372164 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 352557 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1191852 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 4868557 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 91379 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32255245 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 59750 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6509687 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3839458 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 369212 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 31393 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2360 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9268 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 105822 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 88057 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 193879 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33230591 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11076582 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 985063 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1187539 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 4864839 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 90375 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32148379 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 60078 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6484809 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3835337 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 371219 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 30634 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2404 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9216 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 105461 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 87459 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 192920 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33152533 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11055310 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 992120 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 77810 # number of nop insts executed -system.cpu2.iew.exec_refs 14478078 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3688656 # Number of branches executed -system.cpu2.iew.exec_stores 3401496 # Number of stores executed -system.cpu2.iew.exec_rate 0.376484 # Inst execution rate -system.cpu2.iew.wb_sent 32812407 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 27349319 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 15625261 # num instructions producing a value -system.cpu2.iew.wb_consumers 28412503 # num instructions consuming a value +system.cpu2.iew.exec_nop 72670 # number of nop insts executed +system.cpu2.iew.exec_refs 14453415 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3670278 # Number of branches executed +system.cpu2.iew.exec_stores 3398105 # Number of stores executed +system.cpu2.iew.exec_rate 0.375646 # Inst execution rate +system.cpu2.iew.wb_sent 32735616 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 27271311 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 15591378 # num instructions producing a value +system.cpu2.iew.wb_consumers 28369462 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.309852 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.549943 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.309007 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.549583 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7344146 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 355809 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 168786 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 35769820 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.688862 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.716544 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7280422 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 357100 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 167971 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 35765164 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.687670 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.714660 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27147085 75.89% 75.89% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4176329 11.68% 87.57% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1256730 3.51% 91.08% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 649005 1.81% 92.90% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 570906 1.60% 94.49% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 316592 0.89% 95.38% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 399111 1.12% 96.49% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 290067 0.81% 97.31% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 963995 2.69% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27144865 75.90% 75.90% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4185503 11.70% 87.60% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1252343 3.50% 91.10% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 650255 1.82% 92.92% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 570350 1.59% 94.51% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 312906 0.87% 95.39% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 397008 1.11% 96.50% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 289788 0.81% 97.31% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 962146 2.69% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 35769820 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 19931262 # Number of instructions committed -system.cpu2.commit.committedOps 24640483 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 35765164 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 19883492 # Number of instructions committed +system.cpu2.commit.committedOps 24594616 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8192237 # Number of memory references committed -system.cpu2.commit.loads 4933582 # Number of loads committed -system.cpu2.commit.membars 94126 # Number of memory barriers committed -system.cpu2.commit.branches 3155533 # Number of branches committed +system.cpu2.commit.refs 8174125 # Number of memory references committed +system.cpu2.commit.loads 4916766 # Number of loads committed +system.cpu2.commit.membars 94500 # Number of memory barriers committed +system.cpu2.commit.branches 3146107 # Number of branches committed system.cpu2.commit.fp_insts 3055 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 21875712 # Number of committed integer instructions. -system.cpu2.commit.function_calls 294009 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 963995 # number cycles where commit BW limit reached +system.cpu2.commit.int_insts 21842455 # Number of committed integer instructions. +system.cpu2.commit.function_calls 293773 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 962146 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 66266303 # The number of ROB reads -system.cpu2.rob.rob_writes 65202475 # The number of ROB writes -system.cpu2.timesIdled 360564 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 51303836 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3567277023 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 19879493 # Number of Instructions Simulated -system.cpu2.committedOps 24588714 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 19879493 # Number of Instructions Simulated -system.cpu2.cpi 4.440034 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.440034 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.225223 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.225223 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 153509449 # number of integer regfile reads -system.cpu2.int_regfile_writes 29174173 # number of integer regfile writes -system.cpu2.fp_regfile_reads 22340 # number of floating regfile reads -system.cpu2.fp_regfile_writes 20840 # number of floating regfile writes -system.cpu2.misc_regfile_reads 9001304 # number of misc regfile reads -system.cpu2.misc_regfile_writes 240409 # number of misc regfile writes +system.cpu2.rob.rob_reads 66150526 # The number of ROB reads +system.cpu2.rob.rob_writes 64978873 # The number of ROB writes +system.cpu2.timesIdled 360296 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 51301918 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3567267972 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 19835003 # Number of Instructions Simulated +system.cpu2.committedOps 24546127 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 19835003 # Number of Instructions Simulated +system.cpu2.cpi 4.449445 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.449445 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.224747 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.224747 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 153135451 # number of integer regfile reads +system.cpu2.int_regfile_writes 29084509 # number of integer regfile writes +system.cpu2.fp_regfile_reads 22287 # number of floating regfile reads +system.cpu2.fp_regfile_writes 20832 # number of floating regfile writes +system.cpu2.misc_regfile_reads 8972562 # number of misc regfile reads +system.cpu2.misc_regfile_writes 241289 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1494,10 +1494,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 979501914046 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 979501914046 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 979501914046 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 979501914046 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 981130976648 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 981130976648 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 981130976648 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 981130976648 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 8c9cf8058..56b72ce02 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.541288 # Number of seconds simulated -sim_ticks 2541288206500 # Number of ticks simulated -final_tick 2541288206500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.541275 # Number of seconds simulated +sim_ticks 2541275479000 # Number of ticks simulated +final_tick 2541275479000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 64704 # Simulator instruction rate (inst/s) -host_op_rate 83256 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2726411009 # Simulator tick rate (ticks/s) -host_mem_usage 408332 # Number of bytes of host memory used -host_seconds 932.10 # Real time elapsed on the host -sim_insts 60310239 # Number of instructions simulated -sim_ops 77602695 # Number of ops (including micro ops) simulated +host_inst_rate 58368 # Simulator instruction rate (inst/s) +host_op_rate 75104 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2459458086 # Simulator tick rate (ticks/s) +host_mem_usage 437960 # Number of bytes of host memory used +host_seconds 1033.27 # Real time elapsed on the host +sim_insts 60310144 # Number of instructions simulated +sim_ops 77602537 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory @@ -24,137 +24,137 @@ system.realview.nvmem.bw_inst_read::total 25 # I system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 503232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4160720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 503040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4153104 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 298048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4933980 # Number of bytes read from this memory -system.physmem.bytes_read::total 131009132 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 503232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 298048 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 801280 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3786176 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1345260 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1670852 # Number of bytes written to this memory -system.physmem.bytes_written::total 6802288 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 296576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4940508 # Number of bytes read from this memory +system.physmem.bytes_read::total 131006444 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 503040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 296576 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799616 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3785600 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1346056 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1670056 # Number of bytes written to this memory +system.physmem.bytes_written::total 6801712 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7863 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 65045 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 29 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 7860 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 64926 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4657 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 77100 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293522 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59159 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 336315 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 417713 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813187 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47657140 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 680 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 76 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 198022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1637248 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 4634 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 77202 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293480 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59150 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 336514 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 417514 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813178 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47657379 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 730 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 197948 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1634260 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 277 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 117282 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1941527 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51552253 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 198022 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 117282 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315305 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1489865 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 529361 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 657482 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2676709 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1489865 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47657140 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 680 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 198022 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2166610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 116704 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1944106 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51551453 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 197948 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 116704 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314651 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1489646 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 529677 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 657172 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2676495 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1489646 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47657379 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 730 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 197948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2163937 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 277 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 117282 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2599009 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54228961 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293522 # Total number of read requests seen -system.physmem.writeReqs 813187 # Total number of write requests seen -system.physmem.cpureqs 218489 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 978785408 # Total number of bytes read from memory -system.physmem.bytesWritten 52043968 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131009132 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6802288 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4667 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 956238 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 955736 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 955671 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 956488 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 956266 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 955445 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 955566 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 956169 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 956096 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 955614 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 955529 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 955925 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956031 # Track reads on a per bank basis +system.physmem.bw_total::cpu1.inst 116704 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2601278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54227949 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293480 # Total number of read requests seen +system.physmem.writeReqs 813178 # Total number of write requests seen +system.physmem.cpureqs 218453 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 978782720 # Total number of bytes read from memory +system.physmem.bytesWritten 52043392 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 131006444 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6801712 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 10 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4682 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 956235 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 955733 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 955667 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 956482 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 956264 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 955442 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 955569 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 956164 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 956098 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 955607 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 955524 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 955922 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 956025 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 955431 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 955324 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955982 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50841 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50414 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50430 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51154 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50910 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50187 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50285 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50862 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51363 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50905 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50809 # Track writes on a per bank basis +system.physmem.perBankRdReqs::14 955322 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 955985 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50834 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50413 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50428 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51152 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50912 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50190 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50284 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50859 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51371 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50904 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50808 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 51186 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51250 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50729 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50633 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51229 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51242 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50728 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50631 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51236 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1856598 # Number of times wr buffer was full causing retry -system.physmem.totGap 2541287063000 # Total gap between requests +system.physmem.numWrRetry 32469 # Number of times wr buffer was full causing retry +system.physmem.totGap 2541274319500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 43 # Categorize read packet sizes system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154663 # Categorize read packet sizes +system.physmem.readPktSize::6 154621 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754028 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59159 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1054970 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 992041 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 961924 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3604913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2718058 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2722873 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2698919 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60155 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59150 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1054746 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 991862 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 961693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3604884 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2718217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2723048 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2699101 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60161 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 59416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 109994 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 160422 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 109940 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 10067 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 9978 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 10954 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8840 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 110020 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 160431 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 109941 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 10084 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 9995 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 10658 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 9166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 25 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -168,46 +168,46 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2931 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2881 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2935 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35287 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 35277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32516 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32512 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32493 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32483 # What write queue length does an incoming req see -system.physmem.totQLat 346675714750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 439850413500 # Sum of mem lat for all requests -system.physmem.totBusLat 76467555000 # Total cycles spent in databus access -system.physmem.totBankLat 16707143750 # Total cycles spent in bank access -system.physmem.avgQLat 22668.16 # Average queueing delay per request -system.physmem.avgBankLat 1092.43 # Average bank access latency per request +system.physmem.wrQLenPdf::18 35256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32475 # What write queue length does an incoming req see +system.physmem.totQLat 346695398500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 439867444750 # Sum of mem lat for all requests +system.physmem.totBusLat 76467350000 # Total cycles spent in databus access +system.physmem.totBankLat 16704696250 # Total cycles spent in bank access +system.physmem.avgQLat 22669.51 # Average queueing delay per request +system.physmem.avgBankLat 1092.28 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28760.59 # Average memory access latency +system.physmem.avgMemAccLat 28761.78 # Average memory access latency system.physmem.avgRdBW 385.15 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.48 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.55 # Average consumed read bandwidth in MB/s @@ -215,235 +215,235 @@ system.physmem.avgConsumedWrBW 2.68 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.17 # Data bus utilization in percentage system.physmem.avgRdQLen 0.17 # Average read queue length over time -system.physmem.avgWrQLen 1.14 # Average write queue length over time -system.physmem.readRowHits 15218363 # Number of row buffer hits during reads -system.physmem.writeRowHits 794663 # Number of row buffer hits during writes +system.physmem.avgWrQLen 1.12 # Average write queue length over time +system.physmem.readRowHits 15218335 # Number of row buffer hits during reads +system.physmem.writeRowHits 794661 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.51 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.72 # Row buffer hit rate for writes -system.physmem.avgGap 157778.17 # Average gap between requests -system.l2c.replacements 64431 # number of replacements -system.l2c.tagsinuse 51403.772051 # Cycle average of tags in use -system.l2c.total_refs 1904252 # Total number of references to valid blocks. -system.l2c.sampled_refs 129822 # Sample count of references to valid blocks. -system.l2c.avg_refs 14.668176 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2505297860000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36947.477101 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 17.181776 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.004228 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5147.781121 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3278.488158 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 8.683561 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3058.770363 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2945.385742 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.563774 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000262 # Average percentage of cache occupancy +system.physmem.avgGap 157777.88 # Average gap between requests +system.l2c.replacements 64389 # number of replacements +system.l2c.tagsinuse 51396.917216 # Cycle average of tags in use +system.l2c.total_refs 1903765 # Total number of references to valid blocks. +system.l2c.sampled_refs 129779 # Sample count of references to valid blocks. +system.l2c.avg_refs 14.669284 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2505294633000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36944.332930 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 18.025643 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.000349 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 5127.291089 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3277.380324 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 9.553076 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3076.231813 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2944.101992 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.563726 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000275 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.078549 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.050026 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000133 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.046673 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.044943 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.784359 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 32227 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 7171 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 490580 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 213578 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30476 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6774 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 480341 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 174067 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1435214 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608440 # number of Writeback hits -system.l2c.Writeback_hits::total 608440 # number of Writeback hits +system.l2c.occ_percent::cpu0.inst 0.078236 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.050009 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000146 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.046940 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.044923 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.784255 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 32015 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 7355 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 491964 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 214249 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 30395 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6870 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 478610 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 173362 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1434820 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 608422 # number of Writeback hits +system.l2c.Writeback_hits::total 608422 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 18 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 34 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 6 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 11 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 57838 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 55045 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112883 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 32227 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 7171 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 490580 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 271416 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 30476 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6774 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 480341 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 229112 # number of demand (read+write) hits -system.l2c.demand_hits::total 1548097 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 32227 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 7171 # number of overall hits -system.l2c.overall_hits::cpu0.inst 490580 # number of overall hits -system.l2c.overall_hits::cpu0.data 271416 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30476 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6774 # number of overall hits -system.l2c.overall_hits::cpu1.inst 480341 # number of overall hits -system.l2c.overall_hits::cpu1.data 229112 # number of overall hits -system.l2c.overall_hits::total 1548097 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 27 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7754 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6099 # number of ReadReq misses +system.l2c.SCUpgradeReq_hits::cpu1.data 5 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 57870 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 55015 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112885 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 32015 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 7355 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 491964 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 272119 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 30395 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 6870 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 478610 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 228377 # number of demand (read+write) hits +system.l2c.demand_hits::total 1547705 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 32015 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 7355 # number of overall hits +system.l2c.overall_hits::cpu0.inst 491964 # number of overall hits +system.l2c.overall_hits::cpu0.data 272119 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 30395 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 6870 # number of overall hits +system.l2c.overall_hits::cpu1.inst 478610 # number of overall hits +system.l2c.overall_hits::cpu1.data 228377 # number of overall hits +system.l2c.overall_hits::total 1547705 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 29 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 7751 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6089 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 11 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 4662 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4629 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23185 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1530 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1369 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2899 # number of UpgradeReq misses +system.l2c.ReadReq_misses::cpu1.inst 4640 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4614 # number of ReadReq misses +system.l2c.ReadReq_misses::total 23136 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1537 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1371 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2908 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 59920 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 73280 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133200 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 27 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7754 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 66019 # number of demand (read+write) misses +system.l2c.ReadExReq_misses::cpu0.data 59818 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 73396 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133214 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 29 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 7751 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 65907 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 11 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 4662 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 77909 # number of demand (read+write) misses -system.l2c.demand_misses::total 156385 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 27 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7754 # number of overall misses -system.l2c.overall_misses::cpu0.data 66019 # number of overall misses +system.l2c.demand_misses::cpu1.inst 4640 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 78010 # number of demand (read+write) misses +system.l2c.demand_misses::total 156350 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 29 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses +system.l2c.overall_misses::cpu0.inst 7751 # number of overall misses +system.l2c.overall_misses::cpu0.data 65907 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 11 # number of overall misses -system.l2c.overall_misses::cpu1.inst 4662 # number of overall misses -system.l2c.overall_misses::cpu1.data 77909 # number of overall misses -system.l2c.overall_misses::total 156385 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1843000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 186500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 426974500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 345172998 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1040500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 269759500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 270421498 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1315398496 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 183000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 204000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 387000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3134918000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 3645169500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6780087500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 1843000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 186500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 426974500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3480090998 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 1040500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 269759500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 3915590998 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8095485996 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 1843000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 186500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 426974500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3480090998 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 1040500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 269759500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 3915590998 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8095485996 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 32254 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 7174 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 498334 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 219677 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 30487 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 6774 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 485003 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 178696 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1458399 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 608440 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 608440 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1548 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1385 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2933 # number of UpgradeReq accesses(hits+misses) +system.l2c.overall_misses::cpu1.inst 4640 # number of overall misses +system.l2c.overall_misses::cpu1.data 78010 # number of overall misses +system.l2c.overall_misses::total 156350 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1945000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 118000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 430985000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 344391500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 737500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 265908000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 270917500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1315002500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 204500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 227500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 432000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 3114638500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 3663340000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6777978500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 1945000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 118000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 430985000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3459030000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 737500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 265908000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 3934257500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8092981000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 1945000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 118000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 430985000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3459030000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 737500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 265908000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 3934257500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8092981000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 32044 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 7357 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 499715 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 220338 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 30406 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 6870 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 483250 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 177976 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1457956 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 608422 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 608422 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1555 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1384 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2939 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 6 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 6 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 12 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 117758 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 128325 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246083 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 32254 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 7174 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 498334 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 337435 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 30487 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 6774 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 485003 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 307021 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1704482 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 32254 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 7174 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 498334 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 337435 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 30487 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6774 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 485003 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 307021 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1704482 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000837 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000418 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015560 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.027763 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000361 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.009612 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.025904 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.015898 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.988372 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.988448 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.988408 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_accesses::cpu1.data 5 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 11 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 117688 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 128411 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246099 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 32044 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 7357 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 499715 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 338026 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 30406 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 6870 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 483250 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 306387 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1704055 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 32044 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 7357 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 499715 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 338026 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 30406 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 6870 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 483250 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 306387 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1704055 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000905 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000272 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015511 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.027635 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000362 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.009602 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.025925 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.015869 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.988424 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.990607 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.989452 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.166667 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.083333 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.508840 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.571050 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.541281 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000837 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000418 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015560 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.195650 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000361 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.009612 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.253758 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.091749 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000837 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000418 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015560 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.195650 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000361 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.009612 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.253758 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.091749 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 68259.259259 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 62166.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55065.063193 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 56595.015248 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 94590.909091 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 57863.470613 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 58418.988550 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 56734.893077 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 119.607843 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 149.013879 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 133.494308 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52318.391188 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 49743.033570 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 50901.557808 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 68259.259259 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 62166.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 55065.063193 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52713.476393 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 94590.909091 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 57863.470613 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 50258.519529 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 51766.384218 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 68259.259259 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 62166.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 55065.063193 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52713.476393 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 94590.909091 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 57863.470613 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 50258.519529 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 51766.384218 # average overall miss latency +system.l2c.SCUpgradeReq_miss_rate::total 0.090909 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.508276 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.571571 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.541302 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000905 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000272 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015511 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.194976 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000362 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.009602 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.254613 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.091752 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000905 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000272 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015511 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.194976 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000362 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.009602 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.254613 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.091752 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 67068.965517 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 59000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55603.793059 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 56559.615700 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 67045.454545 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 57307.758621 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 58716.406589 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 56837.936549 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 133.051399 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 165.937272 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 148.555708 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52068.583035 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 49911.984304 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 50880.376687 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 67068.965517 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 55603.793059 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52483.499477 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 67045.454545 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 57307.758621 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 50432.732983 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 51761.950752 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 67068.965517 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 55603.793059 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52483.499477 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 67045.454545 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 57307.758621 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 50432.732983 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 51761.950752 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -452,166 +452,166 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 59159 # number of writebacks -system.l2c.writebacks::total 59159 # number of writebacks +system.l2c.writebacks::writebacks 59150 # number of writebacks +system.l2c.writebacks::total 59150 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 10 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu0.data 38 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 6 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.data 21 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 10 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu0.data 38 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.data 21 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.inst 10 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu0.data 38 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.data 21 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 74 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 27 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 7744 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6061 # number of ReadReq MSHR misses +system.l2c.overall_mshr_hits::total 75 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 29 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 7741 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6051 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 11 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 4657 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4608 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 23111 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1530 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1369 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2899 # number of UpgradeReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 4634 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 4593 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 23061 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1537 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1371 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2908 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 59920 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 73280 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 133200 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 27 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 7744 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 65981 # number of demand (read+write) MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 59818 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 73396 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 133214 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 29 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 7741 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 65869 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 11 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 4657 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 77888 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 156311 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 27 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 7744 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 65981 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 4634 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 77989 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 156275 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 29 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 7741 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 65869 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 11 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 4657 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 77888 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 156311 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1507275 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 149502 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 330180239 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 268243202 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 901261 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 211476104 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 212129075 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1024586658 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 15301530 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 13761322 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 29062852 # number of UpgradeReq MSHR miss cycles +system.l2c.overall_mshr_misses::cpu1.inst 4634 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 77989 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 156275 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1583028 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 93251 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 334226230 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 267591443 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 598510 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 207854839 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 212784313 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1024731614 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 15371537 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 13786326 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 29157863 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 10001 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2387584034 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2732413305 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5119997339 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1507275 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 149502 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 330180239 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2655827236 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 901261 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 211476104 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 2944542380 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6144583997 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1507275 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 149502 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 330180239 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2655827236 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 901261 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 211476104 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 2944542380 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6144583997 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5050830 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 84192707267 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82774865254 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 166972623351 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 10456103308 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 13163812667 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 23619915975 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2368364997 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2749328891 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5117693888 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1583028 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 93251 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 334226230 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2635956440 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 598510 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 207854839 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 2962113204 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6142425502 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1583028 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 93251 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 334226230 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2635956440 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 598510 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 207854839 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 2962113204 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6142425502 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5052330 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 84119678267 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82847227004 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166971957601 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 10487963006 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 13201284574 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 23689247580 # number of WriteReq MSHR uncacheable cycles system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 76253 # number of LoadLockedReq MSHR uncacheable cycles system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 76253 # number of LoadLockedReq MSHR uncacheable cycles system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data 30003 # number of StoreCondReq MSHR uncacheable cycles system.l2c.StoreCondReq_mshr_uncacheable_latency::total 30003 # number of StoreCondReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5050830 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 94648810575 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 95938677921 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 190592539326 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000837 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000418 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015540 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027591 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000361 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009602 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025787 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015847 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.988372 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.988448 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.988408 # mshr miss rate for UpgradeReq accesses +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5052330 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 94607641273 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 96048511578 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 190661205181 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000905 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000272 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015491 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027462 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000362 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009589 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025807 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015817 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.988424 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.990607 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.989452 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.166667 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.083333 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.508840 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.571050 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541281 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000837 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000418 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015540 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.195537 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000361 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009602 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.253689 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.091706 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000837 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000418 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015540 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.195537 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000361 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009602 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.253689 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.091706 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 55825 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42636.911028 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44257.251609 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 81932.818182 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 45410.372343 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 46034.955512 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 44333.289689 # average ReadReq mshr miss latency +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.090909 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.508276 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.571571 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541302 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000905 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000272 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015491 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.194864 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000362 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009589 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.254544 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.091708 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000905 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000272 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015491 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.194864 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000362 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009589 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.254544 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091708 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 54587.172414 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 43176.105154 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44222.681044 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 54410 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 44854.302762 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 46327.958415 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 44435.697238 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10052.097882 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10025.130045 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10055.671772 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10026.775447 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39846.195494 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37287.299468 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 38438.418461 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 55825 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42636.911028 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40251.394129 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 81932.818182 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 45410.372343 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37804.827188 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39309.990960 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 55825 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42636.911028 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40251.394129 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 81932.818182 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 45410.372343 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37804.827188 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39309.990960 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39592.848256 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37458.838234 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 38417.087453 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 54587.172414 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 43176.105154 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40018.163931 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 54410 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 44854.302762 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37981.166626 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39305.234375 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 54587.172414 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 43176.105154 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40018.163931 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 54410 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 44854.302762 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37981.166626 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39305.234375 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -634,155 +634,155 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 7613725 # Number of BP lookups -system.cpu0.branchPred.condPredicted 6072642 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 379429 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4956500 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4052223 # Number of BTB hits +system.cpu0.branchPred.lookups 7621777 # Number of BP lookups +system.cpu0.branchPred.condPredicted 6075515 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 381764 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4964344 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4051622 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 81.755735 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 731018 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 39412 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 81.614449 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 732539 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 39625 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 26054269 # DTB read hits -system.cpu0.dtb.read_misses 40148 # DTB read misses -system.cpu0.dtb.write_hits 5888543 # DTB write hits -system.cpu0.dtb.write_misses 9328 # DTB write misses +system.cpu0.dtb.read_hits 26065013 # DTB read hits +system.cpu0.dtb.read_misses 39990 # DTB read misses +system.cpu0.dtb.write_hits 5895229 # DTB write hits +system.cpu0.dtb.write_misses 9395 # DTB write misses system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 772 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 770 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5631 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1467 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 272 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 5652 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1415 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 280 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 635 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 26094417 # DTB read accesses -system.cpu0.dtb.write_accesses 5897871 # DTB write accesses +system.cpu0.dtb.perms_faults 669 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 26105003 # DTB read accesses +system.cpu0.dtb.write_accesses 5904624 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31942812 # DTB hits -system.cpu0.dtb.misses 49476 # DTB misses -system.cpu0.dtb.accesses 31992288 # DTB accesses -system.cpu0.itb.inst_hits 6107608 # ITB inst hits -system.cpu0.itb.inst_misses 7459 # ITB inst misses +system.cpu0.dtb.hits 31960242 # DTB hits +system.cpu0.dtb.misses 49385 # DTB misses +system.cpu0.dtb.accesses 32009627 # DTB accesses +system.cpu0.itb.inst_hits 6121620 # ITB inst hits +system.cpu0.itb.inst_misses 7590 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 772 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 770 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2620 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2650 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1567 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1597 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 6115067 # ITB inst accesses -system.cpu0.itb.hits 6107608 # DTB hits -system.cpu0.itb.misses 7459 # DTB misses -system.cpu0.itb.accesses 6115067 # DTB accesses -system.cpu0.numCycles 239065725 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 6129210 # ITB inst accesses +system.cpu0.itb.hits 6121620 # DTB hits +system.cpu0.itb.misses 7590 # DTB misses +system.cpu0.itb.accesses 6129210 # DTB accesses +system.cpu0.numCycles 238950356 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15475182 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 47810378 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7613725 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4783241 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10599303 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2556412 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 92588 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 49524214 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1680 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1986 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 51259 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 101215 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 252 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6105640 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 396425 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3088 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 77615764 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.762044 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.119690 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15511561 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 47861098 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7621777 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4784161 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10616760 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2562446 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 93609 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 49488171 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1734 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1985 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 51736 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 101083 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 287 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6119617 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 397619 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3186 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 77638963 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.762623 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.119947 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 67024086 86.35% 86.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 687549 0.89% 87.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 884780 1.14% 88.38% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1227446 1.58% 89.96% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1139052 1.47% 91.43% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 576391 0.74% 92.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1322616 1.70% 93.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 397461 0.51% 94.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4356383 5.61% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67029800 86.34% 86.34% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 691008 0.89% 87.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 886701 1.14% 88.37% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1229558 1.58% 89.95% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1143059 1.47% 91.42% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 577576 0.74% 92.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1327799 1.71% 93.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 398469 0.51% 94.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4354993 5.61% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77615764 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.031848 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.199988 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16521961 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 49260251 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9602479 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 548826 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1680126 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1023427 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 90450 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 56271590 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 301516 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1680126 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17454704 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 18993172 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 27018669 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9147780 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3319243 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 53454491 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 13507 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 621630 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2155035 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 566 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 55623215 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 243327513 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 243280007 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 47506 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 40387894 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 15235321 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 429274 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 381163 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6745844 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10343403 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6774259 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1062911 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1310407 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 49609262 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1043693 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 63170275 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 95774 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10510467 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 26507766 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 267313 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77615764 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.813885 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.519252 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77638963 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.031897 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.200297 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16561693 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 49223207 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9616319 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 551624 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1684026 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1027423 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 90511 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 56351612 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 302709 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1684026 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17495833 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 18963913 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 27008828 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9162852 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3321475 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 53533397 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 13490 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 620965 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2156088 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 544 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 55691405 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 243710313 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 243662711 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 47602 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 40470990 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 15220415 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 429980 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 381705 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6754845 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10370790 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6781090 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1064335 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1313359 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 49665444 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1039347 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 63215993 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 96269 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10485149 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 26517521 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 261916 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77638963 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.814230 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.519509 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 54780189 70.58% 70.58% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 7210578 9.29% 79.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3685843 4.75% 84.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3149398 4.06% 88.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6278761 8.09% 96.76% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1404530 1.81% 98.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 809241 1.04% 99.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 231115 0.30% 99.91% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 66109 0.09% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 54786055 70.57% 70.57% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 7213649 9.29% 79.86% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3700645 4.77% 84.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3137751 4.04% 88.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6288496 8.10% 96.76% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1404757 1.81% 98.57% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 809185 1.04% 99.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 232478 0.30% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 65947 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77615764 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77638963 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 29823 0.67% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 3 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 29964 0.67% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 4 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available @@ -810,13 +810,13 @@ system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # at system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4228133 94.76% 95.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 204148 4.58% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4227609 94.71% 95.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 206392 4.62% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 195616 0.31% 0.31% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29937335 47.39% 47.70% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46928 0.07% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 195815 0.31% 0.31% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29964622 47.40% 47.71% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46968 0.07% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.78% # Type of FU issued @@ -832,7 +832,7 @@ system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.78% # Ty system.cpu0.iq.FU_type_0::SimdMisc 6 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.78% # Type of FU issued @@ -840,474 +840,474 @@ system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.78% # Ty system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1205 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26771956 42.38% 90.16% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6217218 9.84% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1209 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26783752 42.37% 90.16% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6223613 9.84% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 63170275 # Type of FU issued -system.cpu0.iq.rate 0.264238 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4462107 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.070636 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 208551330 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 61172484 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 44142185 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12154 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6481 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5464 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 67430354 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6412 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 323195 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 63215993 # Type of FU issued +system.cpu0.iq.rate 0.264557 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4463969 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.070615 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 208668164 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 61198847 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 44188793 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12222 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6485 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5502 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 67477689 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6458 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 323157 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2268860 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3534 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 16121 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 886667 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2276582 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3606 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 15957 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 887836 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17166750 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 367684 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17155494 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 367481 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1680126 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 14230285 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 233349 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 50770143 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 105944 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10343403 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6774259 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 742754 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 56167 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3335 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 16121 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 186307 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 146952 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 333259 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 62002420 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26414016 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1167855 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1684026 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 14200734 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 233893 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 50821833 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 107458 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10370790 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6781090 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 738100 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 56554 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3388 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 15957 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 188011 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 147687 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 335698 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 62040059 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26425172 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1175934 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 117188 # number of nop insts executed -system.cpu0.iew.exec_refs 32573974 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6027717 # Number of branches executed -system.cpu0.iew.exec_stores 6159958 # Number of stores executed -system.cpu0.iew.exec_rate 0.259353 # Inst execution rate -system.cpu0.iew.wb_sent 61473665 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 44147649 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24301400 # num instructions producing a value -system.cpu0.iew.wb_consumers 44653762 # num instructions consuming a value +system.cpu0.iew.exec_nop 117042 # number of nop insts executed +system.cpu0.iew.exec_refs 32592128 # number of memory reference insts executed +system.cpu0.iew.exec_branches 6029174 # Number of branches executed +system.cpu0.iew.exec_stores 6166956 # Number of stores executed +system.cpu0.iew.exec_rate 0.259636 # Inst execution rate +system.cpu0.iew.wb_sent 61509785 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 44194295 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24341972 # num instructions producing a value +system.cpu0.iew.wb_consumers 44715542 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.184667 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.544218 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.184952 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.544374 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 10356873 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 776380 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 290234 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75935638 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.525589 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.508198 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 10343604 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 777431 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 292475 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75954937 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.526454 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.509299 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 61722766 81.28% 81.28% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6904437 9.09% 90.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2039889 2.69% 93.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1134781 1.49% 94.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1032872 1.36% 95.92% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 547307 0.72% 96.64% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 702356 0.92% 97.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 369637 0.49% 98.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1481593 1.95% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 61716542 81.25% 81.25% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6915967 9.11% 90.36% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2042261 2.69% 93.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1137231 1.50% 94.55% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1037452 1.37% 95.91% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 547322 0.72% 96.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 703732 0.93% 97.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 369670 0.49% 98.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1484760 1.95% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75935638 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 31265183 # Number of instructions committed -system.cpu0.commit.committedOps 39910920 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75954937 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 31329293 # Number of instructions committed +system.cpu0.commit.committedOps 39986762 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13962135 # Number of memory references committed -system.cpu0.commit.loads 8074543 # Number of loads committed -system.cpu0.commit.membars 212305 # Number of memory barriers committed -system.cpu0.commit.branches 5202337 # Number of branches committed -system.cpu0.commit.fp_insts 5433 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 35261936 # Number of committed integer instructions. -system.cpu0.commit.function_calls 513908 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1481593 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13987462 # Number of memory references committed +system.cpu0.commit.loads 8094208 # Number of loads committed +system.cpu0.commit.membars 212609 # Number of memory barriers committed +system.cpu0.commit.branches 5213704 # Number of branches committed +system.cpu0.commit.fp_insts 5481 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 35328328 # Number of committed integer instructions. +system.cpu0.commit.function_calls 514863 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1484760 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 123744681 # The number of ROB reads -system.cpu0.rob.rob_writes 102258102 # The number of ROB writes -system.cpu0.timesIdled 883709 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 161449961 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2289675923 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 31185911 # Number of Instructions Simulated -system.cpu0.committedOps 39831648 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 31185911 # Number of Instructions Simulated -system.cpu0.cpi 7.665825 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 7.665825 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.130449 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.130449 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 280645626 # number of integer regfile reads -system.cpu0.int_regfile_writes 45419186 # number of integer regfile writes -system.cpu0.fp_regfile_reads 22697 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19806 # number of floating regfile writes -system.cpu0.misc_regfile_reads 15480369 # number of misc regfile reads -system.cpu0.misc_regfile_writes 429671 # number of misc regfile writes -system.cpu0.icache.replacements 983987 # number of replacements -system.cpu0.icache.tagsinuse 511.561827 # Cycle average of tags in use -system.cpu0.icache.total_refs 11034736 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 984499 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 11.208479 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 123824951 # The number of ROB reads +system.cpu0.rob.rob_writes 102387078 # The number of ROB writes +system.cpu0.timesIdled 884056 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 161311393 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2289794473 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 31249850 # Number of Instructions Simulated +system.cpu0.committedOps 39907319 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 31249850 # Number of Instructions Simulated +system.cpu0.cpi 7.646448 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 7.646448 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.130780 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.130780 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 280856495 # number of integer regfile reads +system.cpu0.int_regfile_writes 45466199 # number of integer regfile writes +system.cpu0.fp_regfile_reads 22714 # number of floating regfile reads +system.cpu0.fp_regfile_writes 19802 # number of floating regfile writes +system.cpu0.misc_regfile_reads 15537514 # number of misc regfile reads +system.cpu0.misc_regfile_writes 430329 # number of misc regfile writes +system.cpu0.icache.replacements 983581 # number of replacements +system.cpu0.icache.tagsinuse 511.609112 # Cycle average of tags in use +system.cpu0.icache.total_refs 11036717 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 984093 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 11.215116 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 6522889000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 357.606132 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 153.955695 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.698449 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.300695 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999144 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5565566 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5469170 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 11034736 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5565566 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5469170 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 11034736 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5565566 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5469170 # number of overall hits -system.cpu0.icache.overall_hits::total 11034736 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 539949 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 524997 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1064946 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 539949 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 524997 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1064946 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 539949 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 524997 # number of overall misses -system.cpu0.icache.overall_misses::total 1064946 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7306962994 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6971237994 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14278200988 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7306962994 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6971237994 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14278200988 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7306962994 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6971237994 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14278200988 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6105515 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5994167 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 12099682 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6105515 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5994167 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 12099682 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6105515 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5994167 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 12099682 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088436 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087585 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.088014 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088436 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087585 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.088014 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.088436 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087585 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.088014 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13532.691039 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13278.624438 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13407.441305 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13532.691039 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13278.624438 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13407.441305 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13532.691039 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13278.624438 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13407.441305 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4578 # number of cycles access was blocked +system.cpu0.icache.occ_blocks::cpu0.inst 356.975852 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 154.633260 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.697218 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.302018 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999237 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5578101 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 5458616 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 11036717 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5578101 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 5458616 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 11036717 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5578101 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 5458616 # number of overall hits +system.cpu0.icache.overall_hits::total 11036717 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 541391 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 523221 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1064612 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 541391 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 523221 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1064612 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 541391 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 523221 # number of overall misses +system.cpu0.icache.overall_misses::total 1064612 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7337521992 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6947086995 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14284608987 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7337521992 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 6947086995 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14284608987 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7337521992 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 6947086995 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14284608987 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6119492 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 5981837 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 12101329 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6119492 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 5981837 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 12101329 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6119492 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 5981837 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 12101329 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088470 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087468 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.087975 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088470 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087468 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.087975 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.088470 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087468 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.087975 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13553.091928 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13277.538545 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13417.666706 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13553.091928 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13277.538545 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13417.666706 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13553.091928 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13277.538545 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13417.666706 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4893 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 340 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 347 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.464706 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.100865 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41021 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39404 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 80425 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 41021 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 39404 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 80425 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 41021 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 39404 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 80425 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 498928 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 485593 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 984521 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 498928 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 485593 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 984521 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 498928 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 485593 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 984521 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5964947994 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5687451995 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11652399989 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5964947994 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5687451995 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11652399989 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5964947994 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5687451995 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11652399989 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7526000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7526000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7526000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 7526000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.081718 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.081011 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.081368 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.081718 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.081011 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.081368 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.081718 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.081011 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.081368 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11955.528641 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11712.384641 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11835.603292 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11955.528641 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11712.384641 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11835.603292 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11955.528641 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11712.384641 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11835.603292 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41083 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39415 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 80498 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 41083 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 39415 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 80498 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 41083 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 39415 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 80498 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 500308 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 483806 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 984114 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 500308 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 483806 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 984114 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 500308 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 483806 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 984114 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5984214993 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5663833496 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11648048489 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5984214993 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5663833496 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11648048489 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5984214993 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5663833496 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11648048489 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7527500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7527500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7527500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 7527500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.081756 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.080879 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.081323 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.081756 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.080879 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.081323 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.081756 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.080879 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.081323 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11961.061972 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11706.827728 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11836.076399 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11961.061972 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11706.827728 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11836.076399 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11961.061972 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11706.827728 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11836.076399 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 643944 # number of replacements +system.cpu0.dcache.replacements 643901 # number of replacements system.cpu0.dcache.tagsinuse 511.992715 # Cycle average of tags in use -system.cpu0.dcache.total_refs 21531615 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 644456 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.410528 # Average number of references to valid blocks. +system.cpu0.dcache.total_refs 21533518 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 644413 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.415710 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 43205000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 318.816885 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 193.175830 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.622689 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.377297 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 318.189291 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 193.803424 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.621463 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.378522 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7106399 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6669591 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13775990 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3768165 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3493394 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 7261559 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 125825 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117550 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 243375 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 127797 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 119821 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247618 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10874564 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 10162985 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 21037549 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10874564 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 10162985 # number of overall hits -system.cpu0.dcache.overall_hits::total 21037549 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 435409 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 315775 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 751184 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1387586 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1573694 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2961280 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6805 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6784 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13589 # number of LoadLockedReq misses +system.cpu0.dcache.ReadReq_hits::cpu0.data 7127084 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6650362 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13777446 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3774490 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3487348 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 7261838 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 125952 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117576 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 243528 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 127946 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 119673 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247619 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10901574 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 10137710 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 21039284 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10901574 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 10137710 # number of overall hits +system.cpu0.dcache.overall_hits::total 21039284 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 437179 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 313532 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 750711 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1386171 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1574804 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2960975 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6802 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6759 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13561 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 6 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1822995 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 1889469 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3712464 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1822995 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 1889469 # number of overall misses -system.cpu0.dcache.overall_misses::total 3712464 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6464424000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 4870396500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11334820500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 52533360348 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 61938473792 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 114471834140 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 92175500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 94175500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 186351000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_misses::cpu1.data 5 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1823350 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 1888336 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3711686 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1823350 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 1888336 # number of overall misses +system.cpu0.dcache.overall_misses::total 3711686 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6487702500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 4845715000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11333417500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 52314948357 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 62070901782 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 114385850139 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 91825500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 94465000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 186290500 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 90000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 78000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 168000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 58997784348 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 66808870292 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 125806654640 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 58997784348 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 66808870292 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 125806654640 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7541808 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 6985366 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 14527174 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5155751 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 5067088 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10222839 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 132630 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 124334 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 256964 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 127803 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 119827 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 65000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 155000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 58802650857 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 66916616782 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 125719267639 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 58802650857 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 66916616782 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 125719267639 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7564263 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 6963894 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 14528157 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5160661 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 5062152 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10222813 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 132754 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 124335 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 257089 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 127952 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 119678 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 247630 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12697559 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 12052454 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24750013 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12697559 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 12052454 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24750013 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.057733 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.045205 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.051709 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.269134 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.310572 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.289673 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.051308 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054563 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052883 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 12724924 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 12026046 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24750970 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12724924 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 12026046 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24750970 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.057795 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.045023 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.051673 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.268603 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.311094 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.289644 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.051238 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054361 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052748 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000047 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000050 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.143571 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.156770 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.149998 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.143571 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.156770 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.149998 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14846.785436 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15423.629166 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15089.273068 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 37859.534723 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39358.651550 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38656.200744 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13545.260838 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13882.001769 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13713.371109 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000042 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000044 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.143290 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.157021 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.149961 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.143290 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.157021 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.149961 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14839.922549 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15455.248587 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15096.911461 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 37740.616675 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39415.001347 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38631.143505 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13499.779477 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13976.179908 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13737.224393 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32363.108153 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35358.542687 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33887.642989 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32363.108153 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35358.542687 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33887.642989 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 35225 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 16625 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 3569 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 263 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.869711 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 63.212928 # average number of cycles each access was blocked +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14090.909091 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32249.787949 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35436.816743 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33871.202370 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32249.787949 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35436.816743 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33871.202370 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 36391 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 16051 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 3543 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 264 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.271239 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 60.799242 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 608440 # number of writebacks -system.cpu0.dcache.writebacks::total 608440 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 221787 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 143125 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 364912 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1268338 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1444026 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 2712364 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 692 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 696 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1388 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1490125 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 1587151 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 3077276 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1490125 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 1587151 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 3077276 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 213622 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 172650 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 386272 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 119248 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 129668 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 248916 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6113 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 6088 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12201 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 608422 # number of writebacks +system.cpu0.dcache.writebacks::total 608422 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 222914 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 141593 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 364507 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1266986 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1445051 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 2712037 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 671 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 680 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1351 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1489900 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1586644 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 3076544 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1489900 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1586644 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3076544 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 214265 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 171939 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 386204 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 119185 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 129753 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 248938 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6131 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 6079 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12210 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 6 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 6 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 332870 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 302318 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 635188 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 332870 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 302318 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 635188 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2899035000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2323789000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5222824000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3973939486 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4489804935 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8463744421 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 71655500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73661500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145317000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 5 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 333450 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 301692 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 635142 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 333450 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 301692 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 635142 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2906449500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2315533500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5221983000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3953585991 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4507381433 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8460967424 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 71518000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74200000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145718000 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 78000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 66000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 144000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6872974486 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6813593935 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13686568421 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6872974486 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6813593935 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13686568421 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91950216500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90410818500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182361035000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 14891141407 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 18622831131 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 33513972538 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 55000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 133000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6860035491 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6822914933 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13682950424 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6860035491 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6822914933 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13682950424 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91872733500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90487640000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182360373500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 14914514407 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 18644008670 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 33558523077 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106841357907 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109033649631 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215875007538 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028325 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024716 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026590 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023129 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025590 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024349 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046091 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048965 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047481 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106787247907 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109131648670 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215918896577 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028326 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024690 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026583 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023095 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025632 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024351 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046183 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048892 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047493 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000047 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000050 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026215 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025084 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025664 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026215 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025084 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025664 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13570.863488 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13459.536635 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13521.104300 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33324.999044 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34625.388955 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34002.412143 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11721.822346 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12099.457950 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11910.253258 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000042 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026204 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025087 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025661 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026204 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025087 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025661 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13564.742258 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13467.180221 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13521.307392 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33171.842019 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34738.167387 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33988.251790 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11664.981243 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12205.954927 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11934.316134 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20647.623655 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22537.837426 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21547.271707 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20647.623655 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22537.837426 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21547.271707 # average overall mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12090.909091 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20572.905956 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22615.498366 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21543.135903 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20572.905956 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22615.498366 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21543.135903 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1322,155 +1322,155 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7039242 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5645782 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 344121 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4649860 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3812908 # Number of BTB hits +system.cpu1.branchPred.lookups 7016100 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5626613 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 342958 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4632911 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3801004 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 82.000490 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 671568 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 34742 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 82.043536 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 670740 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 35021 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25307959 # DTB read hits -system.cpu1.dtb.read_misses 36376 # DTB read misses -system.cpu1.dtb.write_hits 5825723 # DTB write hits -system.cpu1.dtb.write_misses 9311 # DTB write misses +system.cpu1.dtb.read_hits 25297638 # DTB read hits +system.cpu1.dtb.read_misses 36209 # DTB read misses +system.cpu1.dtb.write_hits 5817747 # DTB write hits +system.cpu1.dtb.write_misses 9250 # DTB write misses system.cpu1.dtb.flush_tlb 254 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 667 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 669 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5515 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1387 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 246 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 5517 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1319 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 238 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 651 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25344335 # DTB read accesses -system.cpu1.dtb.write_accesses 5835034 # DTB write accesses +system.cpu1.dtb.perms_faults 648 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25333847 # DTB read accesses +system.cpu1.dtb.write_accesses 5826997 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31133682 # DTB hits -system.cpu1.dtb.misses 45687 # DTB misses -system.cpu1.dtb.accesses 31179369 # DTB accesses -system.cpu1.itb.inst_hits 5996114 # ITB inst hits -system.cpu1.itb.inst_misses 6834 # ITB inst misses +system.cpu1.dtb.hits 31115385 # DTB hits +system.cpu1.dtb.misses 45459 # DTB misses +system.cpu1.dtb.accesses 31160844 # DTB accesses +system.cpu1.itb.inst_hits 5983825 # ITB inst hits +system.cpu1.itb.inst_misses 6876 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 254 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 667 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 669 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2600 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2607 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1401 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1422 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 6002948 # ITB inst accesses -system.cpu1.itb.hits 5996114 # DTB hits -system.cpu1.itb.misses 6834 # DTB misses -system.cpu1.itb.accesses 6002948 # DTB accesses -system.cpu1.numCycles 234172204 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5990701 # ITB inst accesses +system.cpu1.itb.hits 5983825 # DTB hits +system.cpu1.itb.misses 6876 # DTB misses +system.cpu1.itb.accesses 5990701 # DTB accesses +system.cpu1.numCycles 234271094 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 15150430 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 46599302 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7039242 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4484476 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 10276938 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2612454 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 82512 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 47518747 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 979 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 2108 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 42921 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 94711 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 94 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5994168 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 443200 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2937 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 74957939 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.773072 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.138667 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 15106075 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 46495215 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7016100 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4471744 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 10263244 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2607774 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 83065 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 47539930 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 913 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 2033 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 42850 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 94637 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 151 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5981839 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 442153 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2974 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 74917861 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.771750 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.136158 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 64688840 86.30% 86.30% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 619651 0.83% 87.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 831575 1.11% 88.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1205005 1.61% 89.84% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1040099 1.39% 91.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 534718 0.71% 91.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1368218 1.83% 93.77% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 351871 0.47% 94.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4317962 5.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 64662198 86.31% 86.31% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 618220 0.83% 87.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 830780 1.11% 88.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1202992 1.61% 89.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1054171 1.41% 91.26% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 533923 0.71% 91.97% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1365534 1.82% 93.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 350745 0.47% 94.26% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4299298 5.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 74957939 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.030060 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.198996 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 16159118 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 47313522 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9319419 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 458702 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1705045 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 945660 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 85957 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 54861176 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 287371 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1705045 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 17094797 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 18547389 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 25741637 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8764339 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3102678 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 51699813 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 7117 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 482642 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2122595 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 48 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 53761457 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 237355866 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 237312988 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 42878 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 38005573 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 15755883 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 403501 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 357316 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6247551 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9846699 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6699378 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 894839 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1124277 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 47671789 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 942558 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 60820762 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 80974 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10554667 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 27991193 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 236389 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 74957939 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.811399 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.521506 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 74917861 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.029949 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.198468 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 16114785 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 47334136 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9307437 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 457642 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1701687 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 943149 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 85752 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 54765911 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 286536 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1701687 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 17049791 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 18574833 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 25739106 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8750674 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3099680 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 51604165 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 7083 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 481938 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2120083 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 47 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 53629483 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 236928405 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 236886159 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 42246 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 37922365 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 15707117 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 402858 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 356707 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6241200 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9820106 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6689053 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 876297 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1123238 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 47543883 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 946480 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 60738625 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 81609 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10509389 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 27830287 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 241377 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 74917861 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.810736 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.521004 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 53217841 71.00% 71.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6660852 8.89% 79.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3522155 4.70% 84.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2891310 3.86% 88.44% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6221103 8.30% 96.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1440067 1.92% 98.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 734950 0.98% 99.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 210065 0.28% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 59596 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 53210773 71.03% 71.03% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6641164 8.86% 79.89% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3529295 4.71% 84.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2876551 3.84% 88.44% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6221124 8.30% 96.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1436861 1.92% 98.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 733077 0.98% 99.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 210173 0.28% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 58843 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 74957939 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 74917861 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 24217 0.55% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 1 0.00% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 24144 0.55% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 0.55% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.55% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.55% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.55% # attempts to use FU when none available @@ -1498,148 +1498,148 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.55% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.55% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.55% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4143294 94.86% 95.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 200406 4.59% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4145479 94.86% 95.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 200357 4.58% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 168050 0.28% 0.28% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28446121 46.77% 47.05% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46643 0.08% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 5 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 906 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26040786 42.82% 89.94% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6118237 10.06% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 167851 0.28% 0.28% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 28384328 46.73% 47.01% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46613 0.08% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 903 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.09% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26029174 42.85% 89.94% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6109728 10.06% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 60820762 # Type of FU issued -system.cpu1.iq.rate 0.259727 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4367918 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.071816 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 201083162 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 59177242 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 41793523 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 10683 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 5961 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 4808 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 65014989 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 5641 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 303389 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 60738625 # Type of FU issued +system.cpu1.iq.rate 0.259266 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4369980 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.071947 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 200881299 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 59008077 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 41690782 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 10661 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 5857 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 4774 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 64935130 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 5624 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 302237 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2265840 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3135 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 14672 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 854347 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2258994 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3096 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 14702 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 849711 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 16937147 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 456872 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 16948413 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 457547 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1705045 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 13964953 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 229910 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48720174 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 98231 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9846699 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6699378 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 669323 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 49676 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3736 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 14672 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 165888 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 133425 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 299313 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 59456626 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25635805 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1364136 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1701687 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 13992381 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 229468 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 48596033 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 98735 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9820106 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6689053 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 673721 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 49557 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3683 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 14702 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 165794 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 132525 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 298319 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 59364884 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25624684 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1373741 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 105827 # number of nop insts executed -system.cpu1.iew.exec_refs 31702395 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5527346 # Number of branches executed -system.cpu1.iew.exec_stores 6066590 # Number of stores executed -system.cpu1.iew.exec_rate 0.253901 # Inst execution rate -system.cpu1.iew.wb_sent 58878116 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 41798331 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 22764679 # num instructions producing a value -system.cpu1.iew.wb_consumers 41753721 # num instructions consuming a value +system.cpu1.iew.exec_nop 105670 # number of nop insts executed +system.cpu1.iew.exec_refs 31682928 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5509079 # Number of branches executed +system.cpu1.iew.exec_stores 6058244 # Number of stores executed +system.cpu1.iew.exec_rate 0.253403 # Inst execution rate +system.cpu1.iew.wb_sent 58786539 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 41695556 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 22722145 # num instructions producing a value +system.cpu1.iew.wb_consumers 41696703 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.178494 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.545213 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.177980 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.544939 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 10481198 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 706169 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 259373 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 73252894 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.516596 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.497283 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 10421777 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 705103 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 258416 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 73216174 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.515817 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.496135 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 59734394 81.55% 81.55% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6658117 9.09% 90.63% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1908666 2.61% 93.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1009766 1.38% 94.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 959602 1.31% 95.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 525640 0.72% 96.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 705032 0.96% 97.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 372807 0.51% 98.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1378870 1.88% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 59718106 81.56% 81.56% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6653283 9.09% 90.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1904372 2.60% 93.25% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1008936 1.38% 94.63% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 956792 1.31% 95.94% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 521917 0.71% 96.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 703785 0.96% 97.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 374006 0.51% 98.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1374977 1.88% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 73252894 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 29195437 # Number of instructions committed -system.cpu1.commit.committedOps 37842156 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 73216174 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 29131232 # Number of instructions committed +system.cpu1.commit.committedOps 37766156 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13425890 # Number of memory references committed -system.cpu1.commit.loads 7580859 # Number of loads committed -system.cpu1.commit.membars 191347 # Number of memory barriers committed -system.cpu1.commit.branches 4759387 # Number of branches committed -system.cpu1.commit.fp_insts 4779 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 33596023 # Number of committed integer instructions. -system.cpu1.commit.function_calls 477418 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1378870 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13400454 # Number of memory references committed +system.cpu1.commit.loads 7561112 # Number of loads committed +system.cpu1.commit.membars 191037 # Number of memory barriers committed +system.cpu1.commit.branches 4747981 # Number of branches committed +system.cpu1.commit.fp_insts 4731 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 33529515 # Number of committed integer instructions. +system.cpu1.commit.function_calls 476457 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1374977 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 119325211 # The number of ROB reads -system.cpu1.rob.rob_writes 98404070 # The number of ROB writes -system.cpu1.timesIdled 873125 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 159214265 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2285839594 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 29124328 # Number of Instructions Simulated -system.cpu1.committedOps 37771047 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 29124328 # Number of Instructions Simulated -system.cpu1.cpi 8.040433 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 8.040433 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.124371 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.124371 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 269378788 # number of integer regfile reads -system.cpu1.int_regfile_writes 42887039 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22080 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19702 # number of floating regfile writes -system.cpu1.misc_regfile_reads 14812812 # number of misc regfile reads -system.cpu1.misc_regfile_writes 402828 # number of misc regfile writes +system.cpu1.rob.rob_reads 119155388 # The number of ROB reads +system.cpu1.rob.rob_writes 98129561 # The number of ROB writes +system.cpu1.timesIdled 872896 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 159353233 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2285655752 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 29060294 # Number of Instructions Simulated +system.cpu1.committedOps 37695218 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 29060294 # Number of Instructions Simulated +system.cpu1.cpi 8.061553 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 8.061553 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.124046 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.124046 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 268946784 # number of integer regfile reads +system.cpu1.int_regfile_writes 42787312 # number of integer regfile writes +system.cpu1.fp_regfile_reads 22150 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19734 # number of floating regfile writes +system.cpu1.misc_regfile_reads 14724221 # number of misc regfile reads +system.cpu1.misc_regfile_writes 402169 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1654,10 +1654,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192668399444 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1192668399444 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192668399444 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1192668399444 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192686110607 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1192686110607 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192686110607 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1192686110607 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |