diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux')
16 files changed, 4731 insertions, 6275 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index 088e3cb9c..366d8d2c3 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/projects/pd/randd/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 dtb_filename= @@ -19,7 +19,7 @@ enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -65,7 +65,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img read_only=true [system.cpu] @@ -627,6 +627,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -677,6 +678,7 @@ children=badaddr_responder block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio @@ -702,25 +704,27 @@ pio=system.membus.default [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 clock=1000 conf_table_reported=true in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false @@ -850,7 +854,7 @@ warn_access= pio=system.iobus.master[24] [system.realview.gic] -type=Gic +type=Pl390 clock=1000 cpu_addr=520093952 cpu_pio_delay=10000 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr index 8bdebac6a..28e40a40b 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr @@ -10,23 +10,25 @@ warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented -warn: 5659150500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 -warn: 5667223500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 -warn: 5701468500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 -warn: 5716197500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 -warn: 6234360500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 +warn: 5720641500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 +warn: 5728757500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 +warn: 5763076500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 +warn: 5777835500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 +warn: 6298513500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 warn: LCD dual screen mode not supported -warn: 51492621000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 +warn: 52553050000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 +warn: 2291164927000: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0 warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr bpiallis' unimplemented -warn: 2473679746000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 -warn: 2487454314500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2488664454000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0 -warn: 2509713816500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2510230497500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2515951942000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 -warn: 2516461974500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0 -warn: 2517022987000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 -warn: 2517024145000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 -warn: 2517574344000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0 +warn: 2483733168000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 +warn: 2497502762000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2498707540000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0 +warn: 2519748168000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2520262198000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2525920507000: Instruction results do not match! (Values may not actually be integers) Inst: 0xee6b2, checker: 0x200da +warn: 2525942893500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 +warn: 2526450197000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0 +warn: 2527009496000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 +warn: 2527010611500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 +warn: 2527557612000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0 hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout index d7b72fe61..e0cb5000c 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker/simout -Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 19:43:25 -gem5 started Jan 23 2013 21:57:44 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Feb 13 2013 11:38:19 +gem5 started Feb 13 2013 20:59:50 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2523204701000 because m5_exit instruction encountered +Exiting @ tick 2533147650000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 4d949983c..9c75c4e0e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,114 +1,126 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.533245 # Number of seconds simulated -sim_ticks 2533245380500 # Number of ticks simulated -final_tick 2533245380500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.533148 # Number of seconds simulated +sim_ticks 2533147650000 # Number of ticks simulated +final_tick 2533147650000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 68339 # Simulator instruction rate (inst/s) -host_op_rate 87933 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2870562080 # Simulator tick rate (ticks/s) -host_mem_usage 409768 # Number of bytes of host memory used -host_seconds 882.49 # Real time elapsed on the host -sim_insts 60308251 # Number of instructions simulated -sim_ops 77599937 # Number of ops (including micro ops) simulated +host_inst_rate 55856 # Simulator instruction rate (inst/s) +host_op_rate 71871 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2346171672 # Simulator tick rate (ticks/s) +host_mem_usage 407620 # Number of bytes of host memory used +host_seconds 1079.69 # Real time elapsed on the host +sim_insts 60307315 # Number of instructions simulated +sim_ops 77598799 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 797824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9094032 # Number of bytes read from this memory -system.physmem.bytes_read::total 129432592 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 797824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 797824 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784128 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 795840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093648 # Number of bytes read from this memory +system.physmem.bytes_read::total 129429904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 795840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 795840 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3782016 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800200 # Number of bytes written to this memory +system.physmem.bytes_written::total 6798088 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 46 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12466 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142128 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096850 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59127 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12435 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142122 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096808 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59094 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813145 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47187558 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1162 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813112 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47189379 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314941 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3589874 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51093587 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314941 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314941 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1493787 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190596 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2684383 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1493787 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47187558 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1162 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314170 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3589861 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51094497 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314170 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314170 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493010 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190642 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2683652 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493010 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47189379 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314941 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4780470 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53777969 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096850 # Total number of read requests seen -system.physmem.writeReqs 813145 # Total number of write requests seen -system.physmem.cpureqs 218417 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966198400 # Total number of bytes read from memory -system.physmem.bytesWritten 52041280 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129432592 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6800200 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 331 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed +system.physmem.bw_total::cpu.inst 314170 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4780503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53778149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096808 # Total number of read requests seen +system.physmem.writeReqs 813112 # Total number of write requests seen +system.physmem.cpureqs 218335 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966195712 # Total number of bytes read from memory +system.physmem.bytesWritten 52039168 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129429904 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6798088 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 295 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4677 # Reqs where no action is needed system.physmem.perBankRdReqs::0 943938 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943448 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943393 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943447 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943391 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 944192 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943987 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943149 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943276 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943874 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943803 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943307 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943198 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943602 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943695 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943079 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 942979 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943599 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50829 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50415 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50439 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51156 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50914 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50181 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50283 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50861 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51365 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50905 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50799 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51242 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50716 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50629 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51227 # Track writes on a per bank basis +system.physmem.perBankRdReqs::4 943982 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943143 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943273 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943872 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943781 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943299 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943231 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 943609 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943694 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943087 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 942964 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943610 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50827 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50416 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50443 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51149 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50907 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50180 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50280 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50862 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51358 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50899 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50801 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51187 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51246 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50710 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50619 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51228 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2173038 # Number of times wr buffer was full causing retry -system.physmem.totGap 2533244279000 # Total gap between requests +system.physmem.numWrRetry 2236976 # Number of times wr buffer was full causing retry +system.physmem.totGap 2533146526000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154606 # Categorize read packet sizes +system.physmem.readPktSize::6 154564 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 2927056 # categorize write packet sizes +system.physmem.writePktSize::2 2990994 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 59127 # categorize write packet sizes +system.physmem.writePktSize::6 59094 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -117,29 +129,29 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4684 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4677 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1040308 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 981234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 950339 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3550137 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2675999 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2688015 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2649233 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60810 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59292 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 108760 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 157649 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 108311 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 16828 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16678 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 21784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 11013 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1039969 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 980923 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 950073 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3550359 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2676584 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2688258 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2649649 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60661 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 108720 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 157659 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 108272 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 16731 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16591 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 21899 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 10876 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -153,109 +165,97 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3024 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32629 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32035 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 31926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 31872 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2580 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2817 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32773 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32611 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32536 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32521 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 393028587393 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 485428123643 # Sum of mem lat for all requests -system.physmem.totBusLat 75482595000 # Total cycles spent in databus access -system.physmem.totBankLat 16916941250 # Total cycles spent in bank access -system.physmem.avgQLat 26034.38 # Average queueing delay per request -system.physmem.avgBankLat 1120.59 # Average bank access latency per request +system.physmem.totQLat 393223278963 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 485615648963 # Sum of mem lat for all requests +system.physmem.totBusLat 75482565000 # Total cycles spent in databus access +system.physmem.totBankLat 16909805000 # Total cycles spent in bank access +system.physmem.avgQLat 26047.29 # Average queueing delay per request +system.physmem.avgBankLat 1120.11 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32154.97 # Average memory access latency -system.physmem.avgRdBW 381.41 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 32167.41 # Average memory access latency +system.physmem.avgRdBW 381.42 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.14 # Data bus utilization in percentage system.physmem.avgRdQLen 0.19 # Average read queue length over time -system.physmem.avgWrQLen 12.52 # Average write queue length over time -system.physmem.readRowHits 15020214 # Number of row buffer hits during reads -system.physmem.writeRowHits 793069 # Number of row buffer hits during writes +system.physmem.avgWrQLen 11.48 # Average write queue length over time +system.physmem.readRowHits 15020221 # Number of row buffer hits during reads +system.physmem.writeRowHits 793131 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.53 # Row buffer hit rate for writes -system.physmem.avgGap 159223.45 # Average gap between requests -system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.writeRowHitRate 97.54 # Row buffer hit rate for writes +system.physmem.avgGap 159218.06 # Average gap between requests system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu.branchPred.lookups 14667589 # Number of BP lookups -system.cpu.branchPred.condPredicted 11748926 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 705805 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9784798 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7931964 # Number of BTB hits +system.cpu.branchPred.lookups 14676489 # Number of BP lookups +system.cpu.branchPred.condPredicted 11762878 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 704619 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9800840 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7950249 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.064157 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1398744 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72667 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.118037 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1398960 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72172 # Number of incorrect RAS predictions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 14987593 # DTB read hits -system.cpu.checker.dtb.read_misses 7307 # DTB read misses -system.cpu.checker.dtb.write_hits 11227866 # DTB write hits +system.cpu.checker.dtb.read_hits 14987326 # DTB read hits +system.cpu.checker.dtb.read_misses 7302 # DTB read misses +system.cpu.checker.dtb.write_hits 11227680 # DTB write hits system.cpu.checker.dtb.write_misses 2189 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_entries 6416 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 14994900 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11230055 # DTB write accesses +system.cpu.checker.dtb.read_accesses 14994628 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11229869 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26215459 # DTB hits -system.cpu.checker.dtb.misses 9496 # DTB misses -system.cpu.checker.dtb.accesses 26224955 # DTB accesses -system.cpu.checker.itb.inst_hits 61482253 # ITB inst hits +system.cpu.checker.dtb.hits 26215006 # DTB hits +system.cpu.checker.dtb.misses 9491 # DTB misses +system.cpu.checker.dtb.accesses 26224497 # DTB accesses +system.cpu.checker.itb.inst_hits 61481313 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -272,36 +272,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61486724 # ITB inst accesses -system.cpu.checker.itb.hits 61482253 # DTB hits +system.cpu.checker.itb.inst_accesses 61485784 # ITB inst accesses +system.cpu.checker.itb.hits 61481313 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61486724 # DTB accesses -system.cpu.checker.numCycles 77885746 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61485784 # DTB accesses +system.cpu.checker.numCycles 77884604 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51389080 # DTB read hits -system.cpu.dtb.read_misses 73326 # DTB read misses -system.cpu.dtb.write_hits 11702658 # DTB write hits -system.cpu.dtb.write_misses 17128 # DTB write misses +system.cpu.dtb.read_hits 51394402 # DTB read hits +system.cpu.dtb.read_misses 64202 # DTB read misses +system.cpu.dtb.write_hits 11700782 # DTB write hits +system.cpu.dtb.write_misses 15842 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 7749 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2506 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 491 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 6555 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2475 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1337 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51462406 # DTB read accesses -system.cpu.dtb.write_accesses 11719786 # DTB write accesses +system.cpu.dtb.perms_faults 1357 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51458604 # DTB read accesses +system.cpu.dtb.write_accesses 11716624 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63091738 # DTB hits -system.cpu.dtb.misses 90454 # DTB misses -system.cpu.dtb.accesses 63182192 # DTB accesses -system.cpu.itb.inst_hits 12277036 # ITB inst hits -system.cpu.itb.inst_misses 11490 # ITB inst misses +system.cpu.dtb.hits 63095184 # DTB hits +system.cpu.dtb.misses 80044 # DTB misses +system.cpu.dtb.accesses 63175228 # DTB accesses +system.cpu.itb.inst_hits 12330326 # ITB inst hits +system.cpu.itb.inst_misses 11351 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -310,518 +310,518 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 5150 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 4952 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2988 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2994 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 12288526 # ITB inst accesses -system.cpu.itb.hits 12277036 # DTB hits -system.cpu.itb.misses 11490 # DTB misses -system.cpu.itb.accesses 12288526 # DTB accesses -system.cpu.numCycles 472097236 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 12341677 # ITB inst accesses +system.cpu.itb.hits 12330326 # DTB hits +system.cpu.itb.misses 11351 # DTB misses +system.cpu.itb.accesses 12341677 # DTB accesses +system.cpu.numCycles 471833351 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30535145 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 95659606 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14667589 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9330708 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21094710 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5261516 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 125902 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 95951841 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2603 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 94532 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 195374 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 334 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 12273314 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 886277 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5889 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151614227 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.781014 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.145237 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30572359 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 96029601 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14676489 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9349209 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21156129 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5298120 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 120373 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 95586316 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2531 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87050 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 195749 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 271 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12326631 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 900507 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5718 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 151357354 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.785025 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.150266 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130534830 86.10% 86.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1304262 0.86% 86.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1711991 1.13% 88.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2483160 1.64% 89.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2210564 1.46% 91.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1108348 0.73% 91.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2746367 1.81% 93.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 744764 0.49% 94.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8769941 5.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130216652 86.03% 86.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1302204 0.86% 86.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1711626 1.13% 88.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2495193 1.65% 89.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2215033 1.46% 91.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1107976 0.73% 91.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2757688 1.82% 93.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 745754 0.49% 94.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8805228 5.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151614227 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031069 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.202627 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32507875 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95564460 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19109346 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 988199 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3444347 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1959915 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171959 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 112281673 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 569222 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3444347 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34437159 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36947144 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52554741 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18109845 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6120991 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 105853391 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21725 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1011282 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4135399 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 28413 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 110224508 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 484220176 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 484129547 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90629 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78390630 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 31833877 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830294 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 736801 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12261174 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20294238 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13503315 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1968797 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2454387 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97750102 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983216 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124244624 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 169680 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21546848 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 56327140 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 500803 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151614227 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.819479 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.532560 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 151357354 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031105 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.203524 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32536934 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95207461 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19182239 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 963280 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3467440 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1956290 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171623 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 112620131 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 567256 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3467440 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34479585 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36699027 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52520178 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18147266 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6043858 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 106106757 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20523 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1005521 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4063485 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 592 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 110532069 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 485468581 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 485377824 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90757 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78389582 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 32142486 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830463 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 737014 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12171984 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20324763 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13518088 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1981188 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2478536 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97936678 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983499 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124321529 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167156 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21750573 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 57066044 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501117 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151357354 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.821378 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.534899 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 107320603 70.79% 70.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13614389 8.98% 79.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7121261 4.70% 84.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5900322 3.89% 88.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12601828 8.31% 96.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2772948 1.83% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1691791 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 464731 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 126354 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 107117235 70.77% 70.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13550856 8.95% 79.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7067177 4.67% 84.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5940673 3.92% 88.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12604400 8.33% 96.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2784028 1.84% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1701066 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 465188 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 126731 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151614227 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151357354 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 59822 0.68% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8365800 94.71% 95.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 407388 4.61% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 61039 0.69% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 3 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8364044 94.63% 95.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 413790 4.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58568271 47.14% 47.43% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93243 0.08% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 14 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52895196 42.57% 90.08% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12322086 9.92% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58631158 47.16% 47.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93232 0.07% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 20 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 15 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52911235 42.56% 90.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12320074 9.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124244624 # Type of FU issued -system.cpu.iq.rate 0.263176 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8833017 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071094 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 409173362 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 121296699 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85947126 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 22922 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12496 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10285 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132701824 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12151 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 625056 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124321529 # Type of FU issued +system.cpu.iq.rate 0.263486 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8838876 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071097 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 409062941 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 121687155 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85967434 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23205 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12488 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10289 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 132784424 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12315 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 622437 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4639526 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6246 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30083 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1771107 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4670323 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6258 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30023 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1786078 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107778 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 879356 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107730 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 893047 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3444347 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28046391 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 438374 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 99953895 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 200970 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20294238 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13503315 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1410324 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 116022 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3795 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30083 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 349489 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 270440 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 619929 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121508078 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52074968 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2736546 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3467440 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27945377 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 433355 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100140842 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 200439 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20324763 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13518088 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1411116 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 112674 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3579 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30023 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 350481 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 268612 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 619093 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121545908 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52081707 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2775621 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 220577 # number of nop insts executed -system.cpu.iew.exec_refs 64289334 # number of memory reference insts executed -system.cpu.iew.exec_branches 11563754 # Number of branches executed -system.cpu.iew.exec_stores 12214366 # Number of stores executed -system.cpu.iew.exec_rate 0.257379 # Inst execution rate -system.cpu.iew.wb_sent 120366152 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85957411 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47207424 # num instructions producing a value -system.cpu.iew.wb_consumers 88142728 # num instructions consuming a value +system.cpu.iew.exec_nop 220665 # number of nop insts executed +system.cpu.iew.exec_refs 64294282 # number of memory reference insts executed +system.cpu.iew.exec_branches 11561887 # Number of branches executed +system.cpu.iew.exec_stores 12212575 # Number of stores executed +system.cpu.iew.exec_rate 0.257603 # Inst execution rate +system.cpu.iew.wb_sent 120387103 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85977723 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47219839 # num instructions producing a value +system.cpu.iew.wb_consumers 88163371 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182076 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535579 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182221 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535595 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 21297531 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482413 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 536366 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 148169880 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.524738 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.515080 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 21484846 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482382 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 535483 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147889914 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.525723 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.514974 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120738862 81.49% 81.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13327822 8.99% 90.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3883611 2.62% 93.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2123257 1.43% 94.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1920888 1.30% 95.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 968544 0.65% 96.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1598005 1.08% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 699927 0.47% 98.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2908964 1.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120439692 81.44% 81.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13316642 9.00% 90.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3906186 2.64% 93.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2120970 1.43% 94.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1946250 1.32% 95.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 970441 0.66% 96.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1598227 1.08% 97.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 701359 0.47% 98.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2890147 1.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 148169880 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60458632 # Number of instructions committed -system.cpu.commit.committedOps 77750318 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 147889914 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60457696 # Number of instructions committed +system.cpu.commit.committedOps 77749180 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386920 # Number of memory references committed -system.cpu.commit.loads 15654712 # Number of loads committed -system.cpu.commit.membars 403607 # Number of memory barriers committed -system.cpu.commit.branches 9961406 # Number of branches committed +system.cpu.commit.refs 27386450 # Number of memory references committed +system.cpu.commit.loads 15654440 # Number of loads committed +system.cpu.commit.membars 403595 # Number of memory barriers committed +system.cpu.commit.branches 9961299 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68855494 # Number of committed integer instructions. -system.cpu.commit.function_calls 991273 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2908964 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68854449 # Number of committed integer instructions. +system.cpu.commit.function_calls 991256 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2890147 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 242460133 # The number of ROB reads -system.cpu.rob.rob_writes 201635862 # The number of ROB writes -system.cpu.timesIdled 1769557 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320483009 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4594310480 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60308251 # Number of Instructions Simulated -system.cpu.committedOps 77599937 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60308251 # Number of Instructions Simulated -system.cpu.cpi 7.828070 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.828070 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127745 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.127745 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 550197997 # number of integer regfile reads -system.cpu.int_regfile_writes 88410648 # number of integer regfile writes -system.cpu.fp_regfile_reads 8198 # number of floating regfile reads -system.cpu.fp_regfile_writes 2906 # number of floating regfile writes -system.cpu.misc_regfile_reads 30226423 # number of misc regfile reads -system.cpu.misc_regfile_writes 831902 # number of misc regfile writes -system.cpu.icache.replacements 980802 # number of replacements -system.cpu.icache.tagsinuse 511.577289 # Cycle average of tags in use -system.cpu.icache.total_refs 11213050 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 981314 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11.426567 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6406924000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.577289 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999174 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999174 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11213050 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11213050 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11213050 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11213050 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11213050 # number of overall hits -system.cpu.icache.overall_hits::total 11213050 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1060138 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1060138 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1060138 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1060138 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1060138 # number of overall misses -system.cpu.icache.overall_misses::total 1060138 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14001105997 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14001105997 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14001105997 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14001105997 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14001105997 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14001105997 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12273188 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12273188 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12273188 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12273188 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12273188 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12273188 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086378 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.086378 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.086378 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.086378 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.086378 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.086378 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13206.871178 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13206.871178 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13206.871178 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13206.871178 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13206.871178 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13206.871178 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4476 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 4 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 295 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 15.172881 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 4 # average number of cycles each access was blocked +system.cpu.rob.rob_reads 242385214 # The number of ROB reads +system.cpu.rob.rob_writes 202032533 # The number of ROB writes +system.cpu.timesIdled 1770643 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320475997 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4594378908 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60307315 # Number of Instructions Simulated +system.cpu.committedOps 77598799 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60307315 # Number of Instructions Simulated +system.cpu.cpi 7.823816 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.823816 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127815 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127815 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 550300284 # number of integer regfile reads +system.cpu.int_regfile_writes 88460224 # number of integer regfile writes +system.cpu.fp_regfile_reads 8330 # number of floating regfile reads +system.cpu.fp_regfile_writes 2914 # number of floating regfile writes +system.cpu.misc_regfile_reads 30137587 # number of misc regfile reads +system.cpu.misc_regfile_writes 831885 # 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number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219125045582 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 219125045582 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026617 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026617 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047424 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047424 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12466.156523 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12466.156523 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32865.097408 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32865.097408 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11564.117309 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11564.117309 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14600 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14600 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20469.298364 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20469.298364 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20469.298364 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20469.298364 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1118,16 +1118,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229394161981 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1229394161981 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229394161981 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1229394161981 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229589046447 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1229589046447 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229589046447 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1229589046447 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83046 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83042 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 86e60df6e..2403b9510 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/projects/pd/randd/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 dtb_filename= @@ -19,7 +19,7 @@ enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -65,7 +65,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img read_only=true [system.cpu0] @@ -1048,6 +1048,7 @@ children=badaddr_responder block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio @@ -1073,25 +1074,27 @@ pio=system.membus.default [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 clock=1000 conf_table_reported=true in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false @@ -1221,7 +1224,7 @@ warn_access= pio=system.iobus.master[24] [system.realview.gic] -type=Gic +type=Pl390 clock=1000 cpu_addr=520093952 cpu_pio_delay=10000 @@ -1500,6 +1503,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=8 master=system.l2c.cpu_side diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index a480bab99..d8e2a14f0 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simout -Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 19:43:25 -gem5 started Jan 23 2013 22:02:35 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Feb 13 2013 11:38:19 +gem5 started Feb 13 2013 21:11:40 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1092968826500 because m5_exit instruction encountered +Exiting @ tick 1102937390000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index c67fcab1e..93139ea5d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,131 +1,149 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.103053 # Number of seconds simulated -sim_ticks 1103052934500 # Number of ticks simulated -final_tick 1103052934500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.102937 # Number of seconds simulated +sim_ticks 1102937390000 # Number of ticks simulated +final_tick 1102937390000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 84555 # Simulator instruction rate (inst/s) -host_op_rate 108843 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1514437253 # Simulator tick rate (ticks/s) -host_mem_usage 415912 # Number of bytes of host memory used -host_seconds 728.36 # Real time elapsed on the host -sim_insts 61586372 # Number of instructions simulated -sim_ops 79276491 # Number of ops (including micro ops) simulated +host_inst_rate 67484 # Simulator instruction rate (inst/s) +host_op_rate 86868 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1208579190 # Simulator tick rate (ticks/s) +host_mem_usage 412736 # Number of bytes of host memory used +host_seconds 912.59 # Real time elapsed on the host +sim_insts 61585042 # Number of instructions simulated +sim_ops 79274675 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 704 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 409536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4368116 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 405952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5246000 # Number of bytes read from this memory -system.physmem.bytes_read::total 59190564 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 409536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 405952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 815488 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4268032 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 408896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4378804 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 405888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5226160 # Number of bytes read from this memory +system.physmem.bytes_read::total 59180644 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 408896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 405888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 814784 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4259456 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7295376 # Number of bytes written to this memory +system.physmem.bytes_written::total 7286800 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 11 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6399 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68324 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 19 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6343 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 81995 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6257943 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66688 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6389 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68491 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 20 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6342 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 81685 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6257788 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66554 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823524 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 44203485 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 754 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 823390 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 44208116 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 638 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 116 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 371275 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3960024 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1102 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 368026 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4755891 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53660674 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 371275 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 368026 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 739301 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3869290 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 15412 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2729102 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6613804 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3869290 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 44203485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 754 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 370734 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3970129 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1161 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 368006 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4738401 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53657301 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 370734 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 368006 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 738740 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3861920 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 15413 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2729388 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6606721 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3861920 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 44208116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 638 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 116 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 371275 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3975436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1102 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 368026 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7484993 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 60274478 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6257943 # Total number of read requests seen -system.physmem.writeReqs 823524 # Total number of write requests seen -system.physmem.cpureqs 281760 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 400508352 # Total number of bytes read from memory -system.physmem.bytesWritten 52705536 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 59190564 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7295376 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 71 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 12603 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 391392 # Track reads on a per bank basis +system.physmem.bw_total::cpu0.inst 370734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3985543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1161 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 368006 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7467789 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 60264023 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6257788 # Total number of read requests seen +system.physmem.writeReqs 823390 # Total number of write requests seen +system.physmem.cpureqs 281560 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 400498432 # Total number of bytes read from memory +system.physmem.bytesWritten 52696960 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 59180644 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7286800 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 80 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 12623 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 391400 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 391208 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 390903 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 391629 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 391534 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 390909 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 390959 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 391652 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 391399 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 390708 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 390860 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 391237 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 391228 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 390865 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 391604 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 391517 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 390867 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 390930 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 391637 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 391401 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 390707 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 390849 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 391231 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 391237 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 390522 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 390463 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 391269 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 51397 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 51232 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 51042 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51695 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51560 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50999 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51006 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51676 # Track writes on a per bank basis +system.physmem.perBankRdReqs::14 390468 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 391265 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 51411 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 51226 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 51010 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51681 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51542 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50958 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50977 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51664 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 52039 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51354 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51498 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51880 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51836 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51352 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51491 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51878 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51845 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 51250 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51165 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51895 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51172 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51894 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2168609 # Number of times wr buffer was full causing retry -system.physmem.totGap 1103051731500 # Total gap between requests +system.physmem.numWrRetry 2242937 # Number of times wr buffer was full causing retry +system.physmem.totGap 1102936257500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 105 # Categorize read packet sizes system.physmem.readPktSize::3 6094848 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 162990 # Categorize read packet sizes +system.physmem.readPktSize::6 162835 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 2925445 # categorize write packet sizes +system.physmem.writePktSize::2 2999773 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 66688 # categorize write packet sizes +system.physmem.writePktSize::6 66554 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -134,29 +152,29 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 12603 # categorize neither packet sizes +system.physmem.neitherpktsize::6 12623 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 494466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 430633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 391954 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1441360 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1085395 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1097883 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1063934 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 26865 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 24928 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 44608 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 63920 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 44461 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 12221 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 11894 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 16880 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 6309 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 135 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 493621 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 430392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 391768 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1441431 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1086063 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1098338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1064335 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 26976 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 24854 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 44565 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 63872 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 44300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 12061 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 11818 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 17153 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 5993 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 138 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -170,309 +188,291 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3929 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32079 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 31963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 31877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2985 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32905 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32779 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32651 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 198980528034 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 238811291784 # Sum of mem lat for all requests -system.physmem.totBusLat 31289360000 # Total cycles spent in databus access -system.physmem.totBankLat 8541403750 # Total cycles spent in bank access -system.physmem.avgQLat 31796.84 # Average queueing delay per request -system.physmem.avgBankLat 1364.91 # Average bank access latency per request +system.physmem.totQLat 199170690855 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 238991050855 # Sum of mem lat for all requests +system.physmem.totBusLat 31288540000 # Total cycles spent in databus access +system.physmem.totBankLat 8531820000 # Total cycles spent in bank access +system.physmem.avgQLat 31828.06 # Average queueing delay per request +system.physmem.avgBankLat 1363.41 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 38161.74 # Average memory access latency -system.physmem.avgRdBW 363.09 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 38191.47 # Average memory access latency +system.physmem.avgRdBW 363.12 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 47.78 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 53.66 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 6.61 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.21 # Data bus utilization in percentage system.physmem.avgRdQLen 0.22 # Average read queue length over time -system.physmem.avgWrQLen 10.13 # Average write queue length over time -system.physmem.readRowHits 6214096 # Number of row buffer hits during reads -system.physmem.writeRowHits 800077 # Number of row buffer hits during writes +system.physmem.avgWrQLen 10.24 # Average write queue length over time +system.physmem.readRowHits 6213872 # Number of row buffer hits during reads +system.physmem.writeRowHits 799892 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.30 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.15 # Row buffer hit rate for writes -system.physmem.avgGap 155765.99 # Average gap between requests -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 72694 # number of replacements -system.l2c.tagsinuse 53751.744794 # Cycle average of tags in use -system.l2c.total_refs 1868125 # Total number of references to valid blocks. -system.l2c.sampled_refs 137855 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.551376 # Average number of references to valid blocks. +system.physmem.avgGap 155756.04 # Average gap between requests +system.l2c.replacements 72539 # number of replacements +system.l2c.tagsinuse 53752.248637 # Cycle average of tags in use +system.l2c.total_refs 1841179 # Total number of references to valid blocks. +system.l2c.sampled_refs 137732 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.367838 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 39374.569084 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 4.396186 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 39388.476412 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 3.826353 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.itb.walker 0.000803 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4014.541431 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2824.438134 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 12.707800 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3714.133429 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 3806.957928 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.600808 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000067 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu0.inst 4008.993875 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2816.909683 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 12.612753 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3717.226162 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 3804.202595 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.601020 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000058 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.061257 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.043098 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000194 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.056673 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.058090 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.820187 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 30721 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4484 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 386372 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 166390 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 49432 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5306 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 590682 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 197805 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1431192 # 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average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10041.940678 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37149.669502 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41303.995234 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 39421.162768 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 53752 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42683.404048 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37783.852845 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56252 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 46743.304762 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41934.145399 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40400.783708 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 54136.615385 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42892.739464 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37823.525502 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 55464.450000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 47955.743610 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41994.162067 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40496.088344 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 53752 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42683.404048 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37783.852845 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56252 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 46743.304762 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41934.145399 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40400.783708 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42892.739464 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37823.525502 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 55464.450000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47955.743610 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41994.162067 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40496.088344 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -663,38 +663,38 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 6009414 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4584575 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 296794 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3746905 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2916795 # Number of BTB hits +system.cpu0.branchPred.lookups 5998436 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4575399 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 294209 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3753379 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2912017 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 77.845448 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 672462 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28490 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 77.583878 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 673016 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28669 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8911826 # DTB read hits -system.cpu0.dtb.read_misses 33481 # DTB read misses -system.cpu0.dtb.write_hits 5139826 # DTB write hits -system.cpu0.dtb.write_misses 6231 # DTB write misses +system.cpu0.dtb.read_hits 8902974 # DTB read hits +system.cpu0.dtb.read_misses 28685 # DTB read misses +system.cpu0.dtb.write_hits 5134917 # DTB write hits +system.cpu0.dtb.write_misses 5599 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2125 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 943 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 378 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1816 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1018 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 297 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 509 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8945307 # DTB read accesses -system.cpu0.dtb.write_accesses 5146057 # DTB write accesses +system.cpu0.dtb.perms_faults 573 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8931659 # DTB read accesses +system.cpu0.dtb.write_accesses 5140516 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14051652 # DTB hits -system.cpu0.dtb.misses 39712 # DTB misses -system.cpu0.dtb.accesses 14091364 # DTB accesses -system.cpu0.itb.inst_hits 4224274 # ITB inst hits -system.cpu0.itb.inst_misses 5167 # ITB inst misses +system.cpu0.dtb.hits 14037891 # DTB hits +system.cpu0.dtb.misses 34284 # DTB misses +system.cpu0.dtb.accesses 14072175 # DTB accesses +system.cpu0.itb.inst_hits 4215172 # ITB inst hits +system.cpu0.itb.inst_misses 5141 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -703,113 +703,113 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1374 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1342 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1487 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1479 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4229441 # ITB inst accesses -system.cpu0.itb.hits 4224274 # DTB hits -system.cpu0.itb.misses 5167 # DTB misses -system.cpu0.itb.accesses 4229441 # DTB accesses -system.cpu0.numCycles 67942321 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4220313 # ITB inst accesses +system.cpu0.itb.hits 4215172 # DTB hits +system.cpu0.itb.misses 5141 # DTB misses +system.cpu0.itb.accesses 4220313 # DTB accesses +system.cpu0.numCycles 67779631 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11770700 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32037426 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6009414 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3589257 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7522750 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1459790 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 61665 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 20761422 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 4873 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 52782 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 85653 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 212 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4222584 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 157713 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2319 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 41308500 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.002087 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.382378 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11746060 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 31992288 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 5998436 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3585033 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7509031 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1449341 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 60597 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 20626968 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 4901 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 47542 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 85433 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 195 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4213506 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 157466 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2283 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 41121561 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.005038 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.385329 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33793144 81.81% 81.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 566641 1.37% 83.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 818694 1.98% 85.16% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 676082 1.64% 86.80% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 774764 1.88% 88.67% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 559890 1.36% 90.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 668973 1.62% 91.65% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 352395 0.85% 92.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3097917 7.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33620027 81.76% 81.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 564307 1.37% 83.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 815894 1.98% 85.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 676094 1.64% 86.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 772709 1.88% 88.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 559273 1.36% 90.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 668674 1.63% 91.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 351557 0.85% 92.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3093026 7.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 41308500 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.088449 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.471539 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12285141 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 20700852 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6822655 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 515208 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 984644 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 935535 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64887 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40031733 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 213257 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 984644 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12853776 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5827758 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12754498 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6718585 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2169239 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 38928303 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 2058 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 438319 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1238743 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 23 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39288298 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 175811025 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 175776420 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34605 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30930446 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8357851 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 411337 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 370395 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5357325 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7655234 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5687790 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1133384 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1222152 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 36851355 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 895739 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37254250 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 80693 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6299190 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13209610 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256967 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 41308500 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.901854 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.509387 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 41121561 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.088499 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.472004 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12250531 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 20568387 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6812697 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 512769 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 977177 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 933938 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64793 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 39972827 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 213127 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 977177 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12817507 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5739937 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12718334 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6708425 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2160181 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 38878118 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1834 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 434730 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1233458 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 20 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39234243 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 175587138 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 175552572 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34566 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30916046 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8318196 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 410984 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 370136 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5348015 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7641998 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5680264 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1129998 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1207028 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 36802265 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 895658 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37215076 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 80061 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6274404 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13150521 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 257091 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 41121561 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.905002 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.512830 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 26145285 63.29% 63.29% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5753076 13.93% 77.22% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3163283 7.66% 84.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2484845 6.02% 90.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2098538 5.08% 95.97% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 943313 2.28% 98.26% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 484190 1.17% 99.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 183544 0.44% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 52426 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 25997548 63.22% 63.22% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5725018 13.92% 77.14% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3161670 7.69% 84.83% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2471559 6.01% 90.84% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2093564 5.09% 95.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 947248 2.30% 98.24% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 486513 1.18% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 185061 0.45% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 53380 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 41308500 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 41121561 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 25686 2.41% 2.41% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 25811 2.41% 2.41% # attempts to use FU when none available system.cpu0.iq.fu_full::IntMult 454 0.04% 2.45% # attempts to use FU when none available system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.45% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.45% # attempts to use FU when none available @@ -838,13 +838,13 @@ system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.45% # at system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.45% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.45% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 841970 78.85% 81.30% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 199670 18.70% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 841861 78.66% 81.12% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 202059 18.88% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22338200 59.96% 60.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46968 0.13% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52149 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22315653 59.96% 60.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46928 0.13% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued @@ -857,11 +857,11 @@ system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.23% # Ty system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 17 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 14 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued @@ -870,363 +870,363 @@ system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.23% # Ty system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9368796 25.15% 85.38% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5447325 14.62% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9358800 25.15% 85.38% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5440823 14.62% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37254250 # Type of FU issued -system.cpu0.iq.rate 0.548322 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1067780 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028662 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 116996499 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44054105 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34350443 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8454 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4728 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3907 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38265398 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4418 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 307211 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37215076 # Type of FU issued +system.cpu0.iq.rate 0.549060 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1070185 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028757 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 116727564 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 43980171 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34315180 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8451 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4750 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3900 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38228693 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4419 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 306291 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1378796 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2415 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13078 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 537331 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1370106 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2445 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13123 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 533688 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2192757 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5650 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2192694 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5412 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 984644 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4190634 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 100027 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 37865226 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 85653 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7655234 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5687790 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 571722 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 40568 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3395 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13078 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 150532 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 118543 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 269075 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 36877414 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9226875 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 376836 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 977177 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4122288 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 97984 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 37816345 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 85218 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7641998 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5680264 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 571541 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39816 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 2781 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13123 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 149547 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 116915 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 266462 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 36841770 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9218382 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 373306 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 118132 # number of nop insts executed -system.cpu0.iew.exec_refs 14626534 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4859341 # Number of branches executed -system.cpu0.iew.exec_stores 5399659 # Number of stores executed -system.cpu0.iew.exec_rate 0.542775 # Inst execution rate -system.cpu0.iew.wb_sent 36683533 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34354350 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18308250 # num instructions producing a value -system.cpu0.iew.wb_consumers 35218685 # num instructions consuming a value +system.cpu0.iew.exec_nop 118422 # number of nop insts executed +system.cpu0.iew.exec_refs 14612857 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4852888 # Number of branches executed +system.cpu0.iew.exec_stores 5394475 # Number of stores executed +system.cpu0.iew.exec_rate 0.543552 # Inst execution rate +system.cpu0.iew.wb_sent 36648414 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34319080 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18273947 # num instructions producing a value +system.cpu0.iew.wb_consumers 35157700 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.505640 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.519845 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.506333 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.519771 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6121232 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 638772 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 232995 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 40323856 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.775878 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.738297 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6086541 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 638567 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 230552 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 40144384 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.778927 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.740713 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 28652168 71.06% 71.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5718960 14.18% 85.24% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1913940 4.75% 89.98% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 975658 2.42% 92.40% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 781823 1.94% 94.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 527081 1.31% 95.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 383426 0.95% 96.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 217091 0.54% 97.14% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1153709 2.86% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 28480985 70.95% 70.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5711149 14.23% 85.17% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1913332 4.77% 89.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 974787 2.43% 92.37% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 784907 1.96% 94.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 524754 1.31% 95.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 386537 0.96% 96.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 218696 0.54% 97.14% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1149237 2.86% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 40323856 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 23679897 # Number of instructions committed -system.cpu0.commit.committedOps 31286376 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 40144384 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23670531 # Number of instructions committed +system.cpu0.commit.committedOps 31269562 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11426897 # Number of memory references committed -system.cpu0.commit.loads 6276438 # Number of loads committed -system.cpu0.commit.membars 229667 # Number of memory barriers committed -system.cpu0.commit.branches 4245099 # Number of branches committed +system.cpu0.commit.refs 11418468 # Number of memory references committed +system.cpu0.commit.loads 6271892 # Number of loads committed +system.cpu0.commit.membars 229609 # Number of memory barriers committed +system.cpu0.commit.branches 4243643 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 27642973 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489349 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1153709 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 27627358 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489165 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1149237 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 75726635 # The number of ROB reads -system.cpu0.rob.rob_writes 75801988 # The number of ROB writes -system.cpu0.timesIdled 359866 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26633821 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2138121828 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23599155 # Number of Instructions Simulated -system.cpu0.committedOps 31205634 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23599155 # Number of Instructions Simulated -system.cpu0.cpi 2.879015 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.879015 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.347341 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.347341 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 171917289 # number of integer regfile reads -system.cpu0.int_regfile_writes 34107060 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3422 # number of floating regfile reads -system.cpu0.fp_regfile_writes 966 # number of floating regfile writes -system.cpu0.misc_regfile_reads 13053108 # number of misc regfile reads -system.cpu0.misc_regfile_writes 451057 # number of misc regfile writes -system.cpu0.icache.replacements 392744 # number of replacements -system.cpu0.icache.tagsinuse 511.016860 # Cycle average of tags in use -system.cpu0.icache.total_refs 3798516 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 393256 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.659143 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 75500320 # The number of ROB reads +system.cpu0.rob.rob_writes 75691570 # The number of ROB writes +system.cpu0.timesIdled 360084 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26658070 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2138053443 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23589789 # Number of Instructions Simulated +system.cpu0.committedOps 31188820 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23589789 # Number of Instructions Simulated +system.cpu0.cpi 2.873261 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.873261 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.348037 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.348037 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 171728285 # number of integer regfile reads +system.cpu0.int_regfile_writes 34072180 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3295 # number of floating regfile reads +system.cpu0.fp_regfile_writes 900 # number of floating regfile writes +system.cpu0.misc_regfile_reads 12998314 # number of misc regfile reads +system.cpu0.misc_regfile_writes 450987 # number of misc regfile writes +system.cpu0.icache.replacements 392135 # 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number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5803194996 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4222451 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4222451 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4222451 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4222451 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4222451 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4222451 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100400 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100400 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100400 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100400 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100400 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100400 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13688.879182 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13688.879182 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13688.879182 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13688.879182 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13688.879182 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13688.879182 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3086 # number of cycles access was blocked +system.cpu0.icache.occ_blocks::cpu0.inst 511.076170 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.998196 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.998196 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3790159 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3790159 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3790159 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3790159 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3790159 # number of overall hits +system.cpu0.icache.overall_hits::total 3790159 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 423214 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 423214 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 423214 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 423214 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 423214 # number of overall misses +system.cpu0.icache.overall_misses::total 423214 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5793685997 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5793685997 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5793685997 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5793685997 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5793685997 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5793685997 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4213373 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4213373 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4213373 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4213373 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4213373 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4213373 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100445 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100445 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100445 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100445 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100445 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100445 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13689.731429 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13689.731429 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13689.731429 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13689.731429 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13689.731429 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13689.731429 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2401 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 163 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 146 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.932515 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.445205 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30660 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 30660 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 30660 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 30660 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 30660 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 30660 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393275 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 393275 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 393275 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 393275 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 393275 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 393275 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4745687496 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4745687496 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4745687496 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4745687496 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4745687496 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4745687496 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30547 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 30547 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 30547 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 30547 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 30547 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 30547 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 392667 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 392667 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 392667 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 392667 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 392667 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 392667 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4739152997 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4739152997 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4739152997 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4739152997 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4739152997 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4739152997 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7900500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7900500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7900500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 7900500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093139 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093139 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093139 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093139 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093139 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093139 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12067.096805 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12067.096805 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12067.096805 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12067.096805 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12067.096805 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12067.096805 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093195 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093195 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093195 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093195 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093195 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093195 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12069.140002 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12069.140002 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12069.140002 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12069.140002 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12069.140002 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12069.140002 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 275861 # number of replacements -system.cpu0.dcache.tagsinuse 459.614904 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9266976 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 276373 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.530685 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 43517000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 459.614904 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.897685 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.897685 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5785932 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5785932 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3160921 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3160921 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139137 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 139137 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137051 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 137051 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8946853 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8946853 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8946853 # number of overall hits -system.cpu0.dcache.overall_hits::total 8946853 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 390976 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 390976 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1582272 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1582272 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8775 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8775 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7484 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7484 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1973248 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1973248 # 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miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051780 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.180699 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.180699 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.180699 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.180699 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13899.798197 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13899.798197 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38119.281243 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38119.281243 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10051.566952 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10051.566952 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6235.970069 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6235.970069 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33320.474097 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33320.474097 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33320.474097 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33320.474097 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 8364 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 5666 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 593 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 81 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.104553 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 69.950617 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 276137 # number of replacements +system.cpu0.dcache.tagsinuse 461.136878 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9254727 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 276649 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.452957 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 43495000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 461.136878 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.900658 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.900658 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5777010 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5777010 # 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number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 60618366371 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 87499000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 87499000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46786000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 46786000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 66091685871 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 66091685871 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 66091685871 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 66091685871 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6169919 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6169919 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4739646 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4739646 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147827 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 147827 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144519 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144519 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10909565 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10909565 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10909565 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10909565 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063681 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063681 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333714 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.333714 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059346 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059346 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051959 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051959 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.180997 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.180997 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.180997 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.180997 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13930.247207 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13930.247207 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38325.158325 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38325.158325 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9973.669212 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9973.669212 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6230.656545 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6230.656545 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33471.008420 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33471.008420 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33471.008420 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33471.008420 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 9022 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 2690 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 641 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 80 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.074883 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 33.625000 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 256398 # number of writebacks -system.cpu0.dcache.writebacks::total 256398 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202708 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 202708 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1451928 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1451928 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 451 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 451 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1654636 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1654636 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1654636 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1654636 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188268 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188268 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130344 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 130344 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8324 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8324 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7483 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7483 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 318612 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 318612 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 318612 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 318612 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2372133500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2372133500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4018964492 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4018964492 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66568500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66568500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31704000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31704000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6391097992 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6391097992 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6391097992 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6391097992 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13514906500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13514906500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180228378 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180228378 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14695134878 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14695134878 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030479 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030479 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027480 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027480 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056277 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056277 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051773 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051773 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029177 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029177 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029177 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029177 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12599.770009 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12599.770009 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30833.521236 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30833.521236 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7997.176838 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7997.176838 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4236.803421 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4236.803421 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20059.187953 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20059.187953 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20059.187953 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20059.187953 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 256527 # number of writebacks +system.cpu0.dcache.writebacks::total 256527 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 204116 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 204116 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1451395 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1451395 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 471 # 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number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7505 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7505 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 319084 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 319084 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 319084 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 319084 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2371443000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2371443000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4036122491 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4036122491 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 65692500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 65692500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31776000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31776000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6407565491 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6407565491 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6407565491 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6407565491 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13513513000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13513513000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180350378 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180350378 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14693863378 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14693863378 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030599 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030599 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027490 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027490 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056160 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056160 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051931 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051931 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029248 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029248 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029248 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029248 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12561.074828 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12561.074828 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30977.753575 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30977.753575 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7912.852325 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7912.852325 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4233.977348 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4233.977348 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20081.124378 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20081.124378 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20081.124378 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20081.124378 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1234,38 +1234,38 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 9060826 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7443379 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 410189 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 6060421 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 5228505 # Number of BTB hits +system.cpu1.branchPred.lookups 9086614 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7469023 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 411441 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 6087298 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 5252816 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 86.272967 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 772521 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 43024 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 86.291422 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 771111 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 43004 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42893856 # DTB read hits -system.cpu1.dtb.read_misses 41286 # DTB read misses -system.cpu1.dtb.write_hits 6825448 # DTB write hits -system.cpu1.dtb.write_misses 11345 # DTB write misses +system.cpu1.dtb.read_hits 42908069 # DTB read hits +system.cpu1.dtb.read_misses 37093 # DTB read misses +system.cpu1.dtb.write_hits 6828111 # DTB write hits +system.cpu1.dtb.write_misses 10566 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2300 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2725 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 348 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2002 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2479 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 308 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 636 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 42935142 # DTB read accesses -system.cpu1.dtb.write_accesses 6836793 # DTB write accesses +system.cpu1.dtb.perms_faults 658 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 42945162 # DTB read accesses +system.cpu1.dtb.write_accesses 6838677 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49719304 # DTB hits -system.cpu1.dtb.misses 52631 # DTB misses -system.cpu1.dtb.accesses 49771935 # DTB accesses -system.cpu1.itb.inst_hits 8340296 # ITB inst hits -system.cpu1.itb.inst_misses 5581 # ITB inst misses +system.cpu1.dtb.hits 49736180 # DTB hits +system.cpu1.dtb.misses 47659 # DTB misses +system.cpu1.dtb.accesses 49783839 # DTB accesses +system.cpu1.itb.inst_hits 8400139 # ITB inst hits +system.cpu1.itb.inst_misses 5511 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1274,114 +1274,114 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1543 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1527 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1561 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1516 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8345877 # ITB inst accesses -system.cpu1.itb.hits 8340296 # DTB hits -system.cpu1.itb.misses 5581 # DTB misses -system.cpu1.itb.accesses 8345877 # DTB accesses -system.cpu1.numCycles 408908787 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8405650 # ITB inst accesses +system.cpu1.itb.hits 8400139 # DTB hits +system.cpu1.itb.misses 5511 # DTB misses +system.cpu1.itb.accesses 8405650 # DTB accesses +system.cpu1.numCycles 408778710 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 19741855 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 65652351 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9060826 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6001026 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 14075401 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3918937 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 65639 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 77552970 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 4686 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 46851 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 129796 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 89 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8338330 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 726090 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3044 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 114288783 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.696009 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.038635 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 19802343 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 66108771 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9086614 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6023927 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 14149480 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3968467 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 63429 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 77260462 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 4652 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 42943 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 130023 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 107 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 8398224 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 741385 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2977 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 114156752 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.701240 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.046062 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 100220679 87.69% 87.69% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 798295 0.70% 88.39% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 938778 0.82% 89.21% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1873808 1.64% 90.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1510998 1.32% 92.17% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 574008 0.50% 92.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2116066 1.85% 94.53% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 410869 0.36% 94.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5845282 5.11% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 100014473 87.61% 87.61% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 796994 0.70% 88.31% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 939704 0.82% 89.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1889255 1.65% 90.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1506031 1.32% 92.11% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 574931 0.50% 92.61% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2131854 1.87% 94.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 410857 0.36% 94.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5892653 5.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 114288783 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022159 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.160555 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 21260604 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 77197159 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12728983 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 527252 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2574785 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1107873 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 98231 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 74815491 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 327601 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2574785 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 22637961 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 32138028 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 40746993 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11784015 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4407001 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 69468156 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 19628 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 681075 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3151682 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 32928 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 73408550 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 319754725 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 319695969 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 58756 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 49044244 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 24364306 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 444465 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 387610 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7946566 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 13166209 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8131289 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1039797 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1544280 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 63306558 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1157694 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 89041269 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 96485 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 16034557 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 45010776 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 277192 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 114288783 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.779090 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.516652 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 114156752 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022229 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.161723 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 21320888 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 76914540 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12790943 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 524179 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2606202 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1106995 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 98605 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 75226388 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 330391 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2606202 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 22704982 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 31945118 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 40735326 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11835422 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4329702 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 69763643 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 18779 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 668299 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3087296 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 338 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 73772994 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 321197839 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 321138769 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59070 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49056932 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 24716062 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 445445 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 388435 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7877150 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 13206045 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8148691 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1035919 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1598177 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 63545873 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1154873 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 89160933 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 94911 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 16250476 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 45782181 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 274059 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 114156752 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.781040 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.519067 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 83847546 73.36% 73.36% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8475969 7.42% 80.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4322490 3.78% 84.56% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3758453 3.29% 87.85% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10560015 9.24% 97.09% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1959947 1.71% 98.81% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1018953 0.89% 99.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 271832 0.24% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 73578 0.06% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 83738528 73.35% 73.35% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8425243 7.38% 80.73% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4289902 3.76% 84.49% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3781770 3.31% 87.81% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10587758 9.27% 97.08% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1962324 1.72% 98.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1024618 0.90% 99.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 272656 0.24% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 73953 0.06% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 114288783 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 114156752 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29343 0.37% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 994 0.01% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29608 0.38% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 998 0.01% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available @@ -1409,395 +1409,399 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.39% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7546096 95.87% 96.25% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 294849 3.75% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7547947 95.93% 96.32% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 289296 3.68% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 313932 0.35% 0.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 37546524 42.17% 42.52% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59182 0.07% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1504 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43946850 49.36% 91.94% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7173254 8.06% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 313997 0.35% 0.35% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 37637940 42.21% 42.57% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59271 0.07% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 10 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1510 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43972305 49.32% 91.95% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7175883 8.05% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 89041269 # Type of FU issued -system.cpu1.iq.rate 0.217753 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7871282 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.088400 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 300376626 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 80507257 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 53605393 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14907 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8010 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6781 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 96590759 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7860 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 340884 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 89160933 # Type of FU issued +system.cpu1.iq.rate 0.218115 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7867849 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.088243 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 300473883 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 80959646 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 53671142 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14975 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8034 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6858 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 96706888 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7897 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 342362 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3415033 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3561 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17027 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1294633 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3450901 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3895 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17010 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1308558 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31913246 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 874031 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31911884 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 888923 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2574785 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 24237525 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 363690 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 64568060 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 112440 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 13166209 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8131289 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 869125 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 67667 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3747 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17027 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 202949 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 155576 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 358525 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 86656974 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43263445 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2384295 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2606202 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 24177339 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 360038 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 64805263 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 113338 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 13206045 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8148691 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 865764 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 64951 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3491 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17010 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 203575 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 156879 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 360454 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 86736990 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43278008 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2423943 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 103808 # number of nop insts executed -system.cpu1.iew.exec_refs 50374669 # number of memory reference insts executed -system.cpu1.iew.exec_branches 6998395 # Number of branches executed -system.cpu1.iew.exec_stores 7111224 # Number of stores executed -system.cpu1.iew.exec_rate 0.211923 # Inst execution rate -system.cpu1.iew.wb_sent 85695257 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 53612174 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 29896757 # num instructions producing a value -system.cpu1.iew.wb_consumers 53335024 # num instructions consuming a value +system.cpu1.iew.exec_nop 104517 # number of nop insts executed +system.cpu1.iew.exec_refs 50391999 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7007502 # Number of branches executed +system.cpu1.iew.exec_stores 7113991 # Number of stores executed +system.cpu1.iew.exec_rate 0.212186 # Inst execution rate +system.cpu1.iew.wb_sent 85759457 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 53678000 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 29917161 # num instructions producing a value +system.cpu1.iew.wb_consumers 53364078 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.131110 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.560546 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.131313 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.560624 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 15938596 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 880502 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 313478 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 111713998 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.430926 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.399973 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 16174786 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 880814 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 314330 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 111550550 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.431692 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.400024 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 94998150 85.04% 85.04% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8214546 7.35% 92.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2111823 1.89% 94.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1251354 1.12% 95.40% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1240107 1.11% 96.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 568335 0.51% 97.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 995989 0.89% 97.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 499347 0.45% 98.36% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1834347 1.64% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 94808427 84.99% 84.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8234297 7.38% 92.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2114478 1.90% 94.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1250833 1.12% 95.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1245005 1.12% 96.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 571421 0.51% 97.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1000699 0.90% 97.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 504697 0.45% 98.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1820693 1.63% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 111713998 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38056856 # Number of instructions committed -system.cpu1.commit.committedOps 48140496 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 111550550 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38064892 # Number of instructions committed +system.cpu1.commit.committedOps 48155494 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16587832 # Number of memory references committed -system.cpu1.commit.loads 9751176 # Number of loads committed -system.cpu1.commit.membars 190071 # Number of memory barriers committed -system.cpu1.commit.branches 5966416 # Number of branches committed -system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 42676497 # Number of committed integer instructions. -system.cpu1.commit.function_calls 534458 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1834347 # number cycles where commit BW limit reached +system.cpu1.commit.refs 16595277 # Number of memory references committed +system.cpu1.commit.loads 9755144 # Number of loads committed +system.cpu1.commit.membars 190149 # Number of memory barriers committed +system.cpu1.commit.branches 5967637 # Number of branches committed +system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 42690457 # Number of committed integer instructions. +system.cpu1.commit.function_calls 534638 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1820693 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 172914942 # The number of ROB reads -system.cpu1.rob.rob_writes 130824932 # The number of ROB writes -system.cpu1.timesIdled 1407670 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 294620004 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 1796556351 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 37987217 # Number of Instructions Simulated -system.cpu1.committedOps 48070857 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 37987217 # Number of Instructions Simulated -system.cpu1.cpi 10.764379 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.764379 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.092899 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.092899 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 387772369 # number of integer regfile reads -system.cpu1.int_regfile_writes 56145305 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4887 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2320 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18518507 # number of misc regfile reads -system.cpu1.misc_regfile_writes 405334 # number of misc regfile writes -system.cpu1.icache.replacements 597077 # number of replacements -system.cpu1.icache.tagsinuse 480.917703 # Cycle average of tags in use -system.cpu1.icache.total_refs 7696282 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 597589 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 12.878888 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74223543500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 480.917703 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.939292 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.939292 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 7696282 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7696282 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7696282 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7696282 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7696282 # number of overall hits -system.cpu1.icache.overall_hits::total 7696282 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 641998 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 641998 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 641998 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 641998 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 641998 # number of overall misses -system.cpu1.icache.overall_misses::total 641998 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8633779496 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8633779496 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8633779496 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8633779496 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8633779496 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8633779496 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 8338280 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8338280 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8338280 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8338280 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8338280 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8338280 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076994 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.076994 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076994 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.076994 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076994 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.076994 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13448.296562 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13448.296562 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13448.296562 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13448.296562 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13448.296562 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13448.296562 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1927 # number of cycles access was blocked +system.cpu1.rob.rob_reads 173015978 # The number of ROB reads +system.cpu1.rob.rob_writes 131360292 # The number of ROB writes +system.cpu1.timesIdled 1408221 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 294621958 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 1796461003 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 37995253 # Number of Instructions Simulated +system.cpu1.committedOps 48085855 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 37995253 # Number of Instructions Simulated +system.cpu1.cpi 10.758678 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.758678 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.092948 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.092948 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 388090475 # number of integer regfile reads +system.cpu1.int_regfile_writes 56232580 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4956 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2332 # number of floating regfile writes +system.cpu1.misc_regfile_reads 18472941 # number of misc regfile reads +system.cpu1.misc_regfile_writes 405527 # number of misc regfile writes +system.cpu1.icache.replacements 597992 # number of replacements +system.cpu1.icache.tagsinuse 480.750463 # Cycle average of tags in use +system.cpu1.icache.total_refs 7754983 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 598504 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 12.957278 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74232640500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 480.750463 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.938966 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.938966 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 7754983 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7754983 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7754983 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7754983 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7754983 # number of overall hits +system.cpu1.icache.overall_hits::total 7754983 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 643188 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 643188 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 643188 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 643188 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 643188 # number of overall misses +system.cpu1.icache.overall_misses::total 643188 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8662129496 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8662129496 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8662129496 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8662129496 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8662129496 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8662129496 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 8398171 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8398171 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 8398171 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 8398171 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 8398171 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 8398171 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076587 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.076587 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076587 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.076587 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076587 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.076587 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13467.492391 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13467.492391 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13467.492391 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13467.492391 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13467.492391 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13467.492391 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 2692 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 172 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 184 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.203488 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.630435 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44386 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 44386 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 44386 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 44386 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 44386 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 44386 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 597612 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 597612 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 597612 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 597612 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 597612 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 597612 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7074093496 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7074093496 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7074093496 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7074093496 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7074093496 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7074093496 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3068500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3068500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3068500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 3068500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071671 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071671 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071671 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.071671 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071671 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.071671 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11837.268154 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11837.268154 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11837.268154 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11837.268154 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11837.268154 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11837.268154 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44654 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 44654 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 44654 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 44654 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 44654 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 44654 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 598534 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 598534 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 598534 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 598534 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 598534 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 598534 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7093435997 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7093435997 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7093435997 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7093435997 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7093435997 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7093435997 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3098500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3098500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3098500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 3098500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071270 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071270 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071270 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.071270 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071270 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.071270 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11851.350127 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11851.350127 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11851.350127 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11851.350127 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11851.350127 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11851.350127 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 360159 # number of replacements -system.cpu1.dcache.tagsinuse 474.597840 # Cycle average of tags in use -system.cpu1.dcache.total_refs 12677942 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 360527 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 35.165028 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 70354983000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 474.597840 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.926949 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.926949 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8310534 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8310534 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4138624 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4138624 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97469 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 97469 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94858 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 94858 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12449158 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12449158 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12449158 # number of overall hits -system.cpu1.dcache.overall_hits::total 12449158 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 397542 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 397542 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1554744 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1554744 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13907 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 13907 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10598 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10598 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1952286 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1952286 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1952286 # number of overall misses -system.cpu1.dcache.overall_misses::total 1952286 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6044984000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6044984000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61833185511 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 61833185511 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129279000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 129279000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53828000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 53828000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 67878169511 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 67878169511 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 67878169511 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 67878169511 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 8708076 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 8708076 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5693368 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5693368 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111376 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 111376 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105456 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 105456 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14401444 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14401444 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14401444 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14401444 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045652 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.045652 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273080 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.273080 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124865 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124865 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100497 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100497 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135562 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.135562 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135562 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.135562 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15205.900257 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15205.900257 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39770.653890 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 39770.653890 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9295.966060 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9295.966060 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5079.071523 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5079.071523 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34768.558250 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 34768.558250 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34768.558250 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 34768.558250 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 26588 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 13412 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3258 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 162 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.160835 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 82.790123 # average number of cycles each access was blocked +system.cpu1.dcache.replacements 360685 # number of replacements +system.cpu1.dcache.tagsinuse 474.635478 # Cycle average of tags in use +system.cpu1.dcache.total_refs 12674649 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 361036 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 35.106330 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 70356699000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 474.635478 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.927022 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.927022 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8306809 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8306809 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4139176 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4139176 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97757 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 97757 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94875 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 94875 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12445985 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12445985 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12445985 # number of overall hits +system.cpu1.dcache.overall_hits::total 12445985 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 399972 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 399972 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1557467 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1557467 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14022 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 14022 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10623 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10623 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1957439 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1957439 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1957439 # number of overall misses +system.cpu1.dcache.overall_misses::total 1957439 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6115655000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6115655000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61487432499 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 61487432499 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129927000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 129927000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53882500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 53882500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 67603087499 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 67603087499 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 67603087499 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 67603087499 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8706781 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8706781 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5696643 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5696643 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111779 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 111779 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105498 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 105498 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14403424 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14403424 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14403424 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14403424 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045938 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045938 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273401 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.273401 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125444 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125444 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100694 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100694 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135901 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.135901 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135901 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.135901 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15290.207815 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15290.207815 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39479.123795 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 39479.123795 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9265.939238 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9265.939238 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5072.248894 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5072.248894 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34536.497689 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 34536.497689 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34536.497689 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 34536.497689 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 30853 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 12637 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3329 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 157 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.267948 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 80.490446 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 324224 # number of writebacks -system.cpu1.dcache.writebacks::total 324224 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 169594 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 169594 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1393339 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1393339 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1447 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1447 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1562933 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1562933 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1562933 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1562933 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 227948 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 227948 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161405 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 161405 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12460 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12460 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10596 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10596 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 389353 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 389353 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 389353 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 389353 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2844990000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2844990000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5144127207 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5144127207 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88536000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88536000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32636000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32636000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7989117207 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 7989117207 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7989117207 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 7989117207 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168989822500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168989822500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35094178017 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35094178017 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204084000517 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204084000517 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026177 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026177 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028350 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028350 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111873 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111873 # 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average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7105.617978 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7105.617978 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3080.030200 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3080.030200 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20518.956338 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20518.956338 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20518.956338 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20518.956338 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 324651 # number of writebacks +system.cpu1.dcache.writebacks::total 324651 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171732 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 171732 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1395801 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1395801 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1444 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1444 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1567533 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1567533 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1567533 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1567533 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228240 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 228240 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161666 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 161666 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12578 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12578 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10618 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10618 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 389906 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 389906 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 389906 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 389906 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2856522500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2856522500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5131083207 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5131083207 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89046000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89046000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32648500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32648500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7987605707 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 7987605707 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7987605707 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 7987605707 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168990252000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168990252000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35686741676 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35686741676 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204676993676 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204676993676 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026214 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026214 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028379 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028379 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112526 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112526 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100646 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100646 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027070 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027070 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027070 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027070 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12515.433316 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12515.433316 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31738.789894 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31738.789894 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7079.503896 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7079.503896 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3074.825768 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3074.825768 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20485.977920 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20485.977920 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20485.977920 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20485.977920 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1819,18 +1823,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 539953604456 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 539953604456 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 539953604456 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 539953604456 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540120016505 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 540120016505 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540120016505 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 540120016505 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 41721 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 41707 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 48838 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 48866 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index d2fe18e1e..814bf6bde 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/projects/pd/randd/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 dtb_filename= @@ -19,7 +19,7 @@ enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -65,7 +65,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img read_only=true [system.cpu] @@ -550,6 +550,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -600,6 +601,7 @@ children=badaddr_responder block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio @@ -625,25 +627,27 @@ pio=system.membus.default [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 clock=1000 conf_table_reported=true in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false @@ -773,7 +777,7 @@ warn_access= pio=system.iobus.master[24] [system.realview.gic] -type=Gic +type=Pl390 clock=1000 cpu_addr=520093952 cpu_pio_delay=10000 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index 0c9f602b9..cc635c8e8 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simout -Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 19:43:25 -gem5 started Jan 23 2013 21:42:21 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Feb 13 2013 11:38:19 +gem5 started Feb 13 2013 20:56:17 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2523204701000 because m5_exit instruction encountered +Exiting @ tick 2533147650000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 406114ee2..5e631440d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,114 +1,126 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.533245 # Number of seconds simulated -sim_ticks 2533245380500 # Number of ticks simulated -final_tick 2533245380500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.533148 # Number of seconds simulated +sim_ticks 2533147650000 # Number of ticks simulated +final_tick 2533147650000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 67317 # Simulator instruction rate (inst/s) -host_op_rate 86618 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2827634962 # Simulator tick rate (ticks/s) -host_mem_usage 409784 # Number of bytes of host memory used -host_seconds 895.89 # Real time elapsed on the host -sim_insts 60308251 # Number of instructions simulated -sim_ops 77599937 # Number of ops (including micro ops) simulated +host_inst_rate 66149 # Simulator instruction rate (inst/s) +host_op_rate 85115 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2778505291 # Simulator tick rate (ticks/s) +host_mem_usage 406592 # Number of bytes of host memory used +host_seconds 911.69 # Real time elapsed on the host +sim_insts 60307315 # Number of instructions simulated +sim_ops 77598799 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 797824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9094032 # Number of bytes read from this memory -system.physmem.bytes_read::total 129432592 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 797824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 797824 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784128 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 795840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093648 # Number of bytes read from this memory +system.physmem.bytes_read::total 129429904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 795840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 795840 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3782016 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800200 # Number of bytes written to this memory +system.physmem.bytes_written::total 6798088 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 46 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12466 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142128 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096850 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59127 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12435 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142122 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096808 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59094 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813145 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47187558 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1162 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813112 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47189379 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314941 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3589874 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51093587 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314941 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314941 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1493787 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190596 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2684383 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1493787 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47187558 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1162 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314170 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3589861 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51094497 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314170 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314170 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493010 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190642 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2683652 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493010 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47189379 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314941 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4780470 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53777969 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096850 # Total number of read requests seen -system.physmem.writeReqs 813145 # Total number of write requests seen -system.physmem.cpureqs 218417 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966198400 # Total number of bytes read from memory -system.physmem.bytesWritten 52041280 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129432592 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6800200 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 331 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed +system.physmem.bw_total::cpu.inst 314170 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4780503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53778149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096808 # Total number of read requests seen +system.physmem.writeReqs 813112 # Total number of write requests seen +system.physmem.cpureqs 218335 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966195712 # Total number of bytes read from memory +system.physmem.bytesWritten 52039168 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129429904 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6798088 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 295 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4677 # Reqs where no action is needed system.physmem.perBankRdReqs::0 943938 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943448 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943393 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943447 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943391 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 944192 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943987 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943149 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943276 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943874 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943803 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943307 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943198 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943602 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943695 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943079 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 942979 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943599 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50829 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50415 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50439 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51156 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50914 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50181 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50283 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50861 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51365 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50905 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50799 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51242 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50716 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50629 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51227 # Track writes on a per bank basis +system.physmem.perBankRdReqs::4 943982 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943143 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943273 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943872 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943781 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943299 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943231 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 943609 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943694 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943087 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 942964 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943610 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50827 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50416 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50443 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51149 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50907 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50180 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50280 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50862 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51358 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50899 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50801 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51187 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51246 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50710 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50619 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51228 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2173038 # Number of times wr buffer was full causing retry -system.physmem.totGap 2533244279000 # Total gap between requests +system.physmem.numWrRetry 2236976 # Number of times wr buffer was full causing retry +system.physmem.totGap 2533146526000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154606 # Categorize read packet sizes +system.physmem.readPktSize::6 154564 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 2927056 # categorize write packet sizes +system.physmem.writePktSize::2 2990994 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 59127 # categorize write packet sizes +system.physmem.writePktSize::6 59094 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -117,29 +129,29 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4684 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4677 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1040308 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 981234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 950339 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3550137 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2675999 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2688015 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2649233 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60810 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59292 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 108760 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 157649 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 108311 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 16828 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16678 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 21784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 11013 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1039969 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 980923 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 950073 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3550359 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2676584 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2688258 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2649649 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60661 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 108720 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 157659 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 108272 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 16731 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16591 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 21899 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 10876 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -153,110 +165,98 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3024 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32629 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32035 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 31926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 31872 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2580 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2817 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32773 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32611 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32536 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32521 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 393028587393 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 485428123643 # Sum of mem lat for all requests -system.physmem.totBusLat 75482595000 # Total cycles spent in databus access -system.physmem.totBankLat 16916941250 # Total cycles spent in bank access -system.physmem.avgQLat 26034.38 # Average queueing delay per request -system.physmem.avgBankLat 1120.59 # Average bank access latency per request +system.physmem.totQLat 393223278963 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 485615648963 # Sum of mem lat for all requests +system.physmem.totBusLat 75482565000 # Total cycles spent in databus access +system.physmem.totBankLat 16909805000 # Total cycles spent in bank access +system.physmem.avgQLat 26047.29 # Average queueing delay per request +system.physmem.avgBankLat 1120.11 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32154.97 # Average memory access latency -system.physmem.avgRdBW 381.41 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 32167.41 # Average memory access latency +system.physmem.avgRdBW 381.42 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.14 # Data bus utilization in percentage system.physmem.avgRdQLen 0.19 # Average read queue length over time -system.physmem.avgWrQLen 12.52 # Average write queue length over time -system.physmem.readRowHits 15020214 # Number of row buffer hits during reads -system.physmem.writeRowHits 793069 # Number of row buffer hits during writes +system.physmem.avgWrQLen 11.48 # Average write queue length over time +system.physmem.readRowHits 15020221 # Number of row buffer hits during reads +system.physmem.writeRowHits 793131 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.53 # Row buffer hit rate for writes -system.physmem.avgGap 159223.45 # Average gap between requests -system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.writeRowHitRate 97.54 # Row buffer hit rate for writes +system.physmem.avgGap 159218.06 # Average gap between requests system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu.branchPred.lookups 14667589 # Number of BP lookups -system.cpu.branchPred.condPredicted 11748926 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 705805 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9784798 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7931964 # Number of BTB hits +system.cpu.branchPred.lookups 14676489 # Number of BP lookups +system.cpu.branchPred.condPredicted 11762878 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 704619 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9800840 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7950249 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.064157 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1398744 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72667 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.118037 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1398960 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72172 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51389080 # DTB read hits -system.cpu.dtb.read_misses 73326 # DTB read misses -system.cpu.dtb.write_hits 11702658 # DTB write hits -system.cpu.dtb.write_misses 17128 # DTB write misses +system.cpu.dtb.read_hits 51394402 # DTB read hits +system.cpu.dtb.read_misses 64202 # DTB read misses +system.cpu.dtb.write_hits 11700782 # DTB write hits +system.cpu.dtb.write_misses 15842 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4257 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2506 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 491 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3565 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2475 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1337 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51462406 # DTB read accesses -system.cpu.dtb.write_accesses 11719786 # DTB write accesses +system.cpu.dtb.perms_faults 1357 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51458604 # DTB read accesses +system.cpu.dtb.write_accesses 11716624 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63091738 # DTB hits -system.cpu.dtb.misses 90454 # DTB misses -system.cpu.dtb.accesses 63182192 # DTB accesses -system.cpu.itb.inst_hits 12277036 # ITB inst hits -system.cpu.itb.inst_misses 11490 # ITB inst misses +system.cpu.dtb.hits 63095184 # DTB hits +system.cpu.dtb.misses 80044 # DTB misses +system.cpu.dtb.accesses 63175228 # DTB accesses +system.cpu.itb.inst_hits 12330326 # ITB inst hits +system.cpu.itb.inst_misses 11351 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -265,518 +265,518 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2578 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2478 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2988 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2994 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 12288526 # ITB inst accesses -system.cpu.itb.hits 12277036 # DTB hits -system.cpu.itb.misses 11490 # DTB misses -system.cpu.itb.accesses 12288526 # DTB accesses -system.cpu.numCycles 472097236 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 12341677 # ITB inst accesses +system.cpu.itb.hits 12330326 # DTB hits +system.cpu.itb.misses 11351 # DTB misses +system.cpu.itb.accesses 12341677 # DTB accesses +system.cpu.numCycles 471833351 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30535145 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 95659606 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14667589 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9330708 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21094710 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5261516 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 125902 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 95951841 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2603 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 94532 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 195374 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 334 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 12273314 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 886277 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5889 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151614227 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.781014 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.145237 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30572359 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 96029601 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14676489 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9349209 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21156129 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5298120 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 120373 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 95586316 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2531 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87050 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 195749 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 271 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12326631 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 900507 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5718 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 151357354 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.785025 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.150266 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130534830 86.10% 86.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1304262 0.86% 86.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1711991 1.13% 88.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2483160 1.64% 89.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2210564 1.46% 91.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1108348 0.73% 91.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2746367 1.81% 93.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 744764 0.49% 94.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8769941 5.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130216652 86.03% 86.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1302204 0.86% 86.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1711626 1.13% 88.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2495193 1.65% 89.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2215033 1.46% 91.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1107976 0.73% 91.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2757688 1.82% 93.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 745754 0.49% 94.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8805228 5.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151614227 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031069 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.202627 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32507875 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95564460 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19109346 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 988199 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3444347 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1959915 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171959 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 112281673 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 569222 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3444347 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34437159 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36947144 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52554741 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18109845 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6120991 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 105853391 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21725 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1011282 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4135399 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 28413 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 110224508 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 484220176 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 484129547 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90629 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78390630 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 31833877 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830294 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 736801 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12261174 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20294238 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13503315 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1968797 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2454387 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97750102 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983216 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124244624 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 169680 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21546848 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 56327140 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 500803 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151614227 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.819479 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.532560 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 151357354 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031105 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.203524 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32536934 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95207461 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19182239 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 963280 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3467440 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1956290 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171623 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 112620131 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 567256 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3467440 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34479585 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36699027 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52520178 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18147266 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6043858 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 106106757 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20523 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1005521 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4063485 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 592 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 110532069 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 485468581 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 485377824 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90757 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78389582 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 32142486 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830463 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 737014 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12171984 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20324763 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13518088 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1981188 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2478536 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97936678 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983499 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124321529 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167156 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21750573 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 57066044 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501117 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151357354 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.821378 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.534899 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 107320603 70.79% 70.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13614389 8.98% 79.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7121261 4.70% 84.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5900322 3.89% 88.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12601828 8.31% 96.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2772948 1.83% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1691791 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 464731 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 126354 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 107117235 70.77% 70.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13550856 8.95% 79.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7067177 4.67% 84.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5940673 3.92% 88.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12604400 8.33% 96.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2784028 1.84% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1701066 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 465188 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 126731 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151614227 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151357354 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 59822 0.68% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8365800 94.71% 95.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 407388 4.61% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 61039 0.69% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 3 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8364044 94.63% 95.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 413790 4.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58568271 47.14% 47.43% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93243 0.08% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 14 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52895196 42.57% 90.08% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12322086 9.92% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58631158 47.16% 47.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93232 0.07% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 20 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 15 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52911235 42.56% 90.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12320074 9.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124244624 # Type of FU issued -system.cpu.iq.rate 0.263176 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8833017 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071094 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 409173362 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 121296699 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85947126 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 22922 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12496 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10285 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132701824 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12151 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 625056 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124321529 # Type of FU issued +system.cpu.iq.rate 0.263486 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8838876 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071097 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 409062941 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 121687155 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85967434 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23205 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12488 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10289 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 132784424 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12315 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 622437 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4639526 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6246 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30083 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1771107 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4670323 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6258 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30023 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1786078 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107778 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 879356 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107730 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 893047 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3444347 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28046391 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 438374 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 99953895 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 200970 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20294238 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13503315 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1410324 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 116022 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3795 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30083 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 349489 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 270440 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 619929 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121508078 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52074968 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2736546 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3467440 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27945377 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 433355 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100140842 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 200439 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20324763 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13518088 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1411116 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 112674 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3579 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30023 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 350481 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 268612 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 619093 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121545908 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52081707 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2775621 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 220577 # number of nop insts executed -system.cpu.iew.exec_refs 64289334 # number of memory reference insts executed -system.cpu.iew.exec_branches 11563754 # Number of branches executed -system.cpu.iew.exec_stores 12214366 # Number of stores executed -system.cpu.iew.exec_rate 0.257379 # Inst execution rate -system.cpu.iew.wb_sent 120366152 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85957411 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47207424 # num instructions producing a value -system.cpu.iew.wb_consumers 88142728 # num instructions consuming a value +system.cpu.iew.exec_nop 220665 # number of nop insts executed +system.cpu.iew.exec_refs 64294282 # number of memory reference insts executed +system.cpu.iew.exec_branches 11561887 # Number of branches executed +system.cpu.iew.exec_stores 12212575 # Number of stores executed +system.cpu.iew.exec_rate 0.257603 # Inst execution rate +system.cpu.iew.wb_sent 120387103 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85977723 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47219839 # num instructions producing a value +system.cpu.iew.wb_consumers 88163371 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182076 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535579 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182221 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535595 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 21297531 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482413 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 536366 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 148169880 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.524738 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.515080 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 21484846 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482382 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 535483 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147889914 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.525723 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.514974 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120738862 81.49% 81.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13327822 8.99% 90.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3883611 2.62% 93.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2123257 1.43% 94.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1920888 1.30% 95.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 968544 0.65% 96.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1598005 1.08% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 699927 0.47% 98.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2908964 1.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120439692 81.44% 81.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13316642 9.00% 90.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3906186 2.64% 93.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2120970 1.43% 94.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1946250 1.32% 95.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 970441 0.66% 96.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1598227 1.08% 97.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 701359 0.47% 98.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2890147 1.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 148169880 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60458632 # Number of instructions committed -system.cpu.commit.committedOps 77750318 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 147889914 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60457696 # Number of instructions committed +system.cpu.commit.committedOps 77749180 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386920 # Number of memory references committed -system.cpu.commit.loads 15654712 # Number of loads committed -system.cpu.commit.membars 403607 # Number of memory barriers committed -system.cpu.commit.branches 9961406 # Number of branches committed +system.cpu.commit.refs 27386450 # Number of memory references committed +system.cpu.commit.loads 15654440 # Number of loads committed +system.cpu.commit.membars 403595 # Number of memory barriers committed +system.cpu.commit.branches 9961299 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68855494 # Number of committed integer instructions. -system.cpu.commit.function_calls 991273 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2908964 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68854449 # Number of committed integer instructions. +system.cpu.commit.function_calls 991256 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2890147 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 242460133 # The number of ROB reads -system.cpu.rob.rob_writes 201635862 # The number of ROB writes -system.cpu.timesIdled 1769557 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320483009 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4594310480 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60308251 # Number of Instructions Simulated -system.cpu.committedOps 77599937 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60308251 # Number of Instructions Simulated -system.cpu.cpi 7.828070 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.828070 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127745 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.127745 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 550197994 # number of integer regfile reads -system.cpu.int_regfile_writes 88410647 # number of integer regfile writes -system.cpu.fp_regfile_reads 8198 # number of floating regfile reads -system.cpu.fp_regfile_writes 2906 # number of floating regfile writes -system.cpu.misc_regfile_reads 30226423 # number of misc regfile reads -system.cpu.misc_regfile_writes 831902 # number of misc regfile writes -system.cpu.icache.replacements 980802 # number of replacements -system.cpu.icache.tagsinuse 511.577289 # Cycle average of tags in use -system.cpu.icache.total_refs 11213050 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 981314 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11.426567 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6406924000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.577289 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999174 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999174 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11213050 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11213050 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11213050 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11213050 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11213050 # 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number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14001105997 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12273188 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12273188 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12273188 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12273188 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12273188 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12273188 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086378 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.086378 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.086378 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.086378 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.086378 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.086378 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13206.871178 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13206.871178 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13206.871178 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13206.871178 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13206.871178 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13206.871178 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4476 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 4 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 295 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 15.172881 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 4 # average number of cycles each access was blocked +system.cpu.rob.rob_reads 242385214 # The number of ROB reads +system.cpu.rob.rob_writes 202032533 # The number of ROB writes +system.cpu.timesIdled 1770643 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320475997 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4594378908 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60307315 # Number of Instructions Simulated +system.cpu.committedOps 77598799 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60307315 # Number of Instructions Simulated +system.cpu.cpi 7.823816 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.823816 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127815 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127815 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 550300281 # number of integer regfile reads +system.cpu.int_regfile_writes 88460223 # number of integer regfile writes +system.cpu.fp_regfile_reads 8330 # number of floating regfile reads +system.cpu.fp_regfile_writes 2914 # number of floating regfile writes +system.cpu.misc_regfile_reads 30137587 # number of misc regfile reads +system.cpu.misc_regfile_writes 831885 # number of misc regfile writes +system.cpu.icache.replacements 979919 # number of replacements +system.cpu.icache.tagsinuse 511.615669 # Cycle average of tags in use +system.cpu.icache.total_refs 11266751 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 980431 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11.491631 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6426355000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.615669 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999249 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999249 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11266751 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11266751 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11266751 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11266751 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11266751 # number of overall hits +system.cpu.icache.overall_hits::total 11266751 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1059755 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1059755 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1059755 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1059755 # 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number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12326506 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12326506 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12326506 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085974 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.085974 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.085974 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.085974 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.085974 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.085974 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13207.831523 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13207.831523 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13207.831523 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13207.831523 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13207.831523 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13207.831523 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4420 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 292 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 15.136986 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11381703997 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11381703997 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7553500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7553500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7553500 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 7553500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079959 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079959 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079959 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.079959 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079959 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.079959 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11613.325336 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11613.325336 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11613.325336 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11613.325336 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11613.325336 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11613.325336 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079541 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079541 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079541 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.079541 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079541 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.079541 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11608.522926 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11608.522926 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11608.522926 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11608.522926 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11608.522926 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11608.522926 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 64377 # number of replacements -system.cpu.l2cache.tagsinuse 51361.576516 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1911659 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129770 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 14.731132 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2498200145000 # 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Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6226.042472 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.563329 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000500 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 8156.882895 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6232.574061 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.563492 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000384 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.124884 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.095002 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.783715 # 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number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248984 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12173 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12173 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 10 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 10 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634627 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634627 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634627 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634627 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4807486000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4807486000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8182883413 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8182883413 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 140770000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 140770000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 146000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 146000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12990369413 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12990369413 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12990369413 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12990369413 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395639500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395639500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36729406082 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36729406082 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219125045582 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 219125045582 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026617 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026617 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047424 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047424 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12466.156523 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12466.156523 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32865.097408 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32865.097408 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11564.117309 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11564.117309 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14600 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14600 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20469.298364 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20469.298364 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20469.298364 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20469.298364 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1073,16 +1073,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229394161981 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1229394161981 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229394161981 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1229394161981 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229589046447 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1229589046447 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229589046447 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1229589046447 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83046 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83042 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini index 454a21a12..a9a41c46d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 cpu2 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/projects/pd/randd/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 dtb_filename= @@ -19,7 +19,7 @@ enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic @@ -65,7 +65,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img read_only=true [system.cpu0] @@ -744,6 +744,7 @@ children=badaddr_responder block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio @@ -769,25 +770,27 @@ pio=system.membus.default [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 clock=1000 conf_table_reported=true in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false @@ -917,7 +920,7 @@ warn_access= pio=system.iobus.master[24] [system.realview.gic] -type=Gic +type=Pl390 clock=1000 cpu_addr=520093952 cpu_pio_delay=10000 @@ -1196,6 +1199,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=8 master=system.l2c.cpu_side diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr index d34d93526..151c69fa7 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr @@ -22,7 +22,5 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR +gem5.opt: build/ARM/cpu/o3/fetch_impl.hh:432: void DefaultFetch<Impl>::drainSanityCheck() const [with Impl = O3CPUImpl]: Assertion `!memReq[i]' failed. +Program aborted at cycle 2395768530500 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 49d5a4463..e69de29bb 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,1536 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 2.401347 # Number of seconds simulated -sim_ticks 2401347058000 # Number of ticks simulated -final_tick 2401347058000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 247220 # Simulator instruction rate (inst/s) -host_op_rate 317493 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9839599535 # Simulator tick rate (ticks/s) -host_mem_usage 400552 # Number of bytes of host memory used -host_seconds 244.05 # Real time elapsed on the host -sim_insts 60333921 # Number of instructions simulated -sim_ops 77484019 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 501472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7131280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 85632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 677504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 176960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1269180 # Number of bytes read from this memory -system.physmem.bytes_read::total 124661740 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 501472 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 85632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 176960 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 764064 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3746368 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1495356 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 199456 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1321004 # Number of bytes written to this memory -system.physmem.bytes_written::total 6762184 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14038 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 111460 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1338 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10586 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2765 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 19845 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512426 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58537 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 373839 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 49864 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 330251 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812491 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47814443 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 208829 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2969700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 35660 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 282135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 73692 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 528528 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51913254 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 208829 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 35660 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 73692 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 318181 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1560111 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 622715 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 83060 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 550110 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2815996 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1560111 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47814443 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 208829 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3592415 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 35660 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 365195 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 73692 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1078638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54729250 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 12617453 # Total number of read requests seen -system.physmem.writeReqs 397526 # Total number of write requests seen -system.physmem.cpureqs 54288 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 807516992 # Total number of bytes read from memory -system.physmem.bytesWritten 25441664 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 102873020 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2634764 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 1 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 2351 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 789108 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 788757 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 788840 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 789165 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 789011 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 788682 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 788876 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 788949 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 788591 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 787997 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 788008 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 788277 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 788205 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 788031 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 788257 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 788698 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 24964 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 24832 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 24781 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 25063 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 24852 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 25063 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 25253 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 25236 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 24651 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 24325 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 24263 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 24366 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 24934 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 24846 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 24965 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 25132 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 749984 # Number of times wr buffer was full causing retry -system.physmem.totGap 2400311882000 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 15 # Categorize read packet sizes -system.physmem.readPktSize::3 12582912 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 34526 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 1130099 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 17411 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 2351 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 815640 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 791627 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 797680 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2998199 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2260925 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2261235 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2249585 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 49266 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 49185 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 91366 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 133537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 91353 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 6968 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 6962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 6960 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 6958 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 17292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 17287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 17285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 17280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 17275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 17269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 17264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 17259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 14298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 14254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 14208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 14055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 14034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 14010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 13970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 13934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 13913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 277194471582 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 353012127832 # Sum of mem lat for all requests -system.physmem.totBusLat 63087260000 # Total cycles spent in databus access -system.physmem.totBankLat 12730396250 # Total cycles spent in bank access -system.physmem.avgQLat 21969.13 # Average queueing delay per request -system.physmem.avgBankLat 1008.95 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27978.08 # Average memory access latency -system.physmem.avgRdBW 336.28 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 10.59 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 42.84 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.10 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.71 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 0.39 # Average write queue length over time -system.physmem.readRowHits 12562851 # Number of row buffer hits during reads -system.physmem.writeRowHits 391169 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.57 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 98.40 # Row buffer hit rate for writes -system.physmem.avgGap 184426.87 # Average gap between requests -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 63262 # number of replacements -system.l2c.tagsinuse 50352.279574 # Cycle average of tags in use -system.l2c.total_refs 1759649 # Total number of references to valid blocks. -system.l2c.sampled_refs 128652 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.677588 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2374416909500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36834.025606 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5156.727312 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3775.205663 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 795.394812 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 755.555046 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.dtb.walker 5.900240 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 1436.095715 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 1592.381720 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.562043 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.078685 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.057605 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.012137 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.011529 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.dtb.walker 0.000090 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.021913 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.024298 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.768315 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 8915 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3218 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 460985 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 169797 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 2555 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1118 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 134527 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 65561 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 28959 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 4314 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 283968 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 137931 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1301848 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 597795 # number of Writeback hits -system.l2c.Writeback_hits::total 597795 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 15 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 32 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 4 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 61039 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 19134 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 33458 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113631 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 8915 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3218 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 460985 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 230836 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 2555 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1118 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 134527 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 84695 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 28959 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 4314 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 283968 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 171389 # number of demand (read+write) hits -system.l2c.demand_hits::total 1415479 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 8915 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3218 # number of overall hits -system.l2c.overall_hits::cpu0.inst 460985 # number of overall hits -system.l2c.overall_hits::cpu0.data 230836 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 2555 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1118 # number of overall hits -system.l2c.overall_hits::cpu1.inst 134527 # number of overall hits -system.l2c.overall_hits::cpu1.data 84695 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 28959 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 4314 # number of overall hits -system.l2c.overall_hits::cpu2.inst 283968 # number of overall hits -system.l2c.overall_hits::cpu2.data 171389 # number of overall hits -system.l2c.overall_hits::total 1415479 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7422 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6360 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1338 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1211 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 6 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 2765 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 2571 # number of ReadReq misses -system.l2c.ReadReq_misses::total 21677 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1420 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 501 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 985 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2906 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu2.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 105862 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 9648 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 17858 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133368 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7422 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 112222 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1338 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 10859 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 6 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 2765 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 20429 # number of demand (read+write) misses -system.l2c.demand_misses::total 155045 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7422 # number of overall misses -system.l2c.overall_misses::cpu0.data 112222 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1338 # number of overall misses -system.l2c.overall_misses::cpu1.data 10859 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 6 # number of overall misses -system.l2c.overall_misses::cpu2.inst 2765 # number of overall misses -system.l2c.overall_misses::cpu2.data 20429 # number of overall misses -system.l2c.overall_misses::total 155045 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 69000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 74977000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 69909500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 412500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 180415500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 156598499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 482381999 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 92000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 113500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 205500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 432219000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 946210000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1378429000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 69000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 74977000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 502128500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 412500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 180415500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 1102808499 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 1860810999 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 69000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 74977000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 502128500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 412500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 180415500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 1102808499 # number of overall miss cycles -system.l2c.overall_miss_latency::total 1860810999 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 8916 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 3220 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 468407 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 176157 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 2556 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 1118 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 135865 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 66772 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 28965 # 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average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33785.920803 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 56252 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 52784.752260 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41512.063513 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40100.018791 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56252 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 43495.439462 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33785.920803 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 56252 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 52784.752260 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41512.063513 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40100.018791 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.dtb.inst_hits 0 # ITB inst hits -system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8069329 # DTB read hits -system.cpu0.dtb.read_misses 6237 # DTB read misses -system.cpu0.dtb.write_hits 6635324 # DTB write hits -system.cpu0.dtb.write_misses 2059 # DTB write misses -system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 709 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5724 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 124 # Number of TLB faults due to prefetch -system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 219 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8075566 # DTB read accesses -system.cpu0.dtb.write_accesses 6637383 # DTB write accesses -system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14704653 # DTB hits -system.cpu0.dtb.misses 8296 # DTB misses -system.cpu0.dtb.accesses 14712949 # DTB accesses -system.cpu0.itb.inst_hits 32681523 # ITB inst hits -system.cpu0.itb.inst_misses 3486 # ITB inst misses -system.cpu0.itb.read_hits 0 # DTB read hits -system.cpu0.itb.read_misses 0 # DTB read misses -system.cpu0.itb.write_hits 0 # DTB write hits -system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 279 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 709 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2595 # Number of entries that have been flushed from TLB -system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu0.itb.read_accesses 0 # DTB read accesses -system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32685009 # ITB inst accesses -system.cpu0.itb.hits 32681523 # DTB hits -system.cpu0.itb.misses 3486 # DTB misses -system.cpu0.itb.accesses 32685009 # DTB accesses -system.cpu0.numCycles 114009309 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 32183346 # Number of instructions committed -system.cpu0.committedOps 42389974 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37541413 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5201 # Number of float alu accesses -system.cpu0.num_func_calls 1186772 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4235639 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37541413 # number of integer instructions -system.cpu0.num_fp_insts 5201 # number of float instructions -system.cpu0.num_int_register_reads 191262498 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39620034 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3719 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1484 # number of times the floating registers were written -system.cpu0.num_mem_refs 15366811 # number of memory refs -system.cpu0.num_load_insts 8436504 # Number of load instructions -system.cpu0.num_store_insts 6930307 # Number of store instructions -system.cpu0.num_idle_cycles 13418269361.007845 # Number of idle cycles -system.cpu0.num_busy_cycles -13304260052.007845 # Number of busy cycles -system.cpu0.not_idle_fraction -116.694507 # Percentage of non-idle cycles -system.cpu0.idle_fraction 117.694507 # Percentage of idle cycles -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 82896 # number of quiesce instructions executed -system.cpu0.icache.replacements 892035 # number of replacements -system.cpu0.icache.tagsinuse 511.603883 # Cycle average of tags in use -system.cpu0.icache.total_refs 44343596 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 892547 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 49.682085 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 8110895000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 479.105953 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 18.181823 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu2.inst 14.316107 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.935754 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.035511 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu2.inst 0.027961 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999226 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 32215079 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 8406427 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3722090 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 44343596 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 32215079 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 8406427 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3722090 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 44343596 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 32215079 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 8406427 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 3722090 # number of overall hits -system.cpu0.icache.overall_hits::total 44343596 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 469123 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 136142 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 311123 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 916388 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 469123 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 136142 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 311123 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 916388 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 469123 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 136142 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 311123 # number of overall misses -system.cpu0.icache.overall_misses::total 916388 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1835025000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4152863490 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5987888490 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1835025000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4152863490 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5987888490 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1835025000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4152863490 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5987888490 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 32684202 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 8542569 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 4033213 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 45259984 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 32684202 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 8542569 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 4033213 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 45259984 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 32684202 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 8542569 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 4033213 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 45259984 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014353 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015937 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.077140 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.020247 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014353 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015937 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.077140 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.020247 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014353 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015937 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.077140 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.020247 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13478.757474 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13347.979706 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6534.228395 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13478.757474 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13347.979706 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6534.228395 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13478.757474 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13347.979706 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6534.228395 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3311 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 199 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.638191 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 23827 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 23827 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 23827 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 23827 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 23827 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 23827 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 136142 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 287296 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 423438 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 136142 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 287296 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 423438 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 136142 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 287296 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 423438 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1562741000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3387046990 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4949787990 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1562741000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3387046990 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4949787990 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1562741000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3387046990 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4949787990 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015937 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.071233 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009356 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015937 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.071233 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009356 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015937 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.071233 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009356 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11478.757474 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11789.398356 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11689.522409 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11478.757474 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11789.398356 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11689.522409 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11478.757474 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11789.398356 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11689.522409 # average overall mshr miss latency -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 629918 # number of replacements -system.cpu0.dcache.tagsinuse 511.997116 # Cycle average of tags in use -system.cpu0.dcache.total_refs 23229670 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 630430 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 36.847342 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 495.731477 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 9.808064 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu2.data 6.457575 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.968226 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.019156 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu2.data 0.012612 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6949961 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1913340 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4445734 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13309035 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5955328 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1354459 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2121705 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9431492 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 130986 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 34187 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 73575 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 238748 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137363 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 35914 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 74119 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247396 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12905289 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 3267799 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 6567439 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 22740527 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12905289 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 3267799 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 6567439 # number of overall hits -system.cpu0.dcache.overall_hits::total 22740527 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 169780 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 65045 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 280934 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 515759 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 168334 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 29287 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 587324 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 784945 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6377 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1727 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3901 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 12005 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 5 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 338114 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 94332 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 868258 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1300704 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 338114 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 94332 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 868258 # number of overall misses -system.cpu0.dcache.overall_misses::total 1300704 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 907672500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 4047585000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4955257500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 722890500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 17770037899 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 18492928399 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 22607500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 52022500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 74630000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 77000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 77000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 1630563000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 21817622899 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 23448185899 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 1630563000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 21817622899 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 23448185899 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7119741 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1978385 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4726668 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13824794 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 6123662 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1383746 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2709029 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10216437 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 137363 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 35914 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 77476 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 250753 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137363 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 35914 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 74124 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247401 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13243403 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 3362131 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7435697 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24041231 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13243403 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 3362131 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7435697 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24041231 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.023846 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.032878 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.059436 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.037307 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027489 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021165 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.216802 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.076832 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046424 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.048087 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050351 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047876 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000067 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000020 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025531 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028057 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.116769 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.054103 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.025531 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028057 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.116769 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.054103 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13954.531478 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14407.601074 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 9607.699526 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 24682.982211 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30255.936926 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 23559.521239 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13090.619572 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13335.683158 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6216.576426 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 15400 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15400 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17285.364457 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25128.041318 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 18027.303598 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17285.364457 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25128.041318 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 18027.303598 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 9913 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 3463 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 1094 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 45 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.061243 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 76.955556 # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 597795 # number of writebacks -system.cpu0.dcache.writebacks::total 597795 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 143860 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 143860 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 535045 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 535045 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 436 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 436 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 678905 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 678905 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 678905 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 678905 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 65045 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 137074 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 202119 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29287 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 52279 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 81566 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1727 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3465 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5192 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 5 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 94332 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 189353 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 283685 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 94332 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 189353 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 283685 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 777582500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1781362000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2558944500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 664316500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1392170991 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2056487491 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19153500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 40164500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 59318000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 67000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 67000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1441899000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3173532991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 4615431991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1441899000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3173532991 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 4615431991 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27472084500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 29005064000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56477148500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1280597500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13851108534 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15131706034 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28752682000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42856172534 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71608854534 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032878 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.029000 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014620 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021165 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019298 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007984 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048087 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.044724 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020706 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000067 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000020 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028057 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025465 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011800 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028057 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025465 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011800 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11954.531478 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12995.622802 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12660.583617 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22682.982211 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26629.640793 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25212.557818 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11090.619572 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11591.486291 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11424.884438 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 13400 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13400 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15285.364457 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16759.877007 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16269.566565 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15285.364457 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16759.877007 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16269.566565 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dtb.inst_hits 0 # ITB inst hits -system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2193182 # DTB read hits -system.cpu1.dtb.read_misses 2113 # DTB read misses -system.cpu1.dtb.write_hits 1470431 # DTB write hits -system.cpu1.dtb.write_misses 386 # DTB write misses -system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 231 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1737 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 39 # Number of TLB faults due to prefetch -system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 73 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2195295 # DTB read accesses -system.cpu1.dtb.write_accesses 1470817 # DTB write accesses -system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3663613 # DTB hits -system.cpu1.dtb.misses 2499 # DTB misses -system.cpu1.dtb.accesses 3666112 # DTB accesses -system.cpu1.itb.inst_hits 8542569 # ITB inst hits -system.cpu1.itb.inst_misses 1142 # ITB inst misses -system.cpu1.itb.read_hits 0 # DTB read hits -system.cpu1.itb.read_misses 0 # DTB read misses -system.cpu1.itb.write_hits 0 # DTB write hits -system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 277 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 231 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 843 # Number of entries that have been flushed from TLB -system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu1.itb.read_accesses 0 # DTB read accesses -system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8543711 # ITB inst accesses -system.cpu1.itb.hits 8542569 # DTB hits -system.cpu1.itb.misses 1142 # DTB misses -system.cpu1.itb.accesses 8543711 # DTB accesses -system.cpu1.numCycles 574622770 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 8323313 # Number of instructions committed -system.cpu1.committedOps 10568521 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9455667 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 2078 # Number of float alu accesses -system.cpu1.num_func_calls 319891 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1162179 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9455667 # number of integer instructions -system.cpu1.num_fp_insts 2078 # number of float instructions -system.cpu1.num_int_register_reads 54536858 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10267786 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1565 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 514 # number of times the floating registers were written -system.cpu1.num_mem_refs 3838385 # number of memory refs -system.cpu1.num_load_insts 2289184 # Number of load instructions -system.cpu1.num_store_insts 1549201 # Number of store instructions -system.cpu1.num_idle_cycles 539990839.742371 # Number of idle cycles -system.cpu1.num_busy_cycles 34631930.257629 # Number of busy cycles -system.cpu1.not_idle_fraction 0.060269 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.939731 # Percentage of idle cycles -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4693263 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3812182 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 221977 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3118720 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2512857 # Number of BTB hits -system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 80.573344 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 412180 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21663 # Number of incorrect RAS predictions. -system.cpu2.dtb.inst_hits 0 # ITB inst hits -system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10844301 # DTB read hits -system.cpu2.dtb.read_misses 26001 # DTB read misses -system.cpu2.dtb.write_hits 3253591 # DTB write hits -system.cpu2.dtb.write_misses 6154 # DTB write misses -system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed -system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 499 # Number of times TLB was flushed by MVA & ASID -system.cpu2.dtb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 3046 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 667 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch -system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 434 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10870302 # DTB read accesses -system.cpu2.dtb.write_accesses 3259745 # DTB write accesses -system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14097892 # DTB hits -system.cpu2.dtb.misses 32155 # DTB misses -system.cpu2.dtb.accesses 14130047 # DTB accesses -system.cpu2.itb.inst_hits 4034633 # ITB inst hits -system.cpu2.itb.inst_misses 4571 # ITB inst misses -system.cpu2.itb.read_hits 0 # DTB read hits -system.cpu2.itb.read_misses 0 # DTB read misses -system.cpu2.itb.write_hits 0 # DTB write hits -system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 276 # Number of times complete TLB was flushed -system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 499 # Number of times TLB was flushed by MVA & ASID -system.cpu2.itb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1620 # Number of entries that have been flushed from TLB -system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 986 # Number of TLB faults due to permissions restrictions -system.cpu2.itb.read_accesses 0 # DTB read accesses -system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4039204 # ITB inst accesses -system.cpu2.itb.hits 4034633 # DTB hits -system.cpu2.itb.misses 4571 # DTB misses -system.cpu2.itb.accesses 4039204 # DTB accesses -system.cpu2.numCycles 88320298 # number of cpu cycles simulated -system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9410725 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32093241 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4693263 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2925037 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6776745 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1793565 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 51693 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 19502883 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 204 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 972 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 35787 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 57273 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 283 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4033217 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 303741 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2092 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 37067906 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.039760 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.425875 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30296325 81.73% 81.73% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 382563 1.03% 82.76% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 507321 1.37% 84.13% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 805393 2.17% 86.31% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 652342 1.76% 88.07% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 346651 0.94% 89.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 996850 2.69% 91.69% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 239087 0.64% 92.33% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2841374 7.67% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 37067906 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.053139 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.363373 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10025306 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19435128 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6133360 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 293839 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1179201 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 610191 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 53369 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36416807 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 180085 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1179201 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10595473 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6672537 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11193536 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5837719 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1588398 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34213134 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2954 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 427229 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 898663 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 11044 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 36672264 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 156364458 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 156337893 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 26565 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 25643428 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 11028835 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 232388 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 208734 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3368643 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6480999 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3820565 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 539245 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 769553 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 31495381 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 514788 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34101978 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 55239 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7293710 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19517466 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 157489 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 37067906 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.919987 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.574944 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24513061 66.13% 66.13% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3940276 10.63% 76.76% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2351629 6.34% 83.10% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 1969211 5.31% 88.42% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2763009 7.45% 95.87% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 888704 2.40% 98.27% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 473497 1.28% 99.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 133879 0.36% 99.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 34640 0.09% 100.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 37067906 # Number of insts issued each cycle -system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 16450 1.07% 1.07% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 1.07% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.07% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.07% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.07% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.07% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.07% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.07% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.07% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.07% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.07% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.07% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.07% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.07% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.07% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.07% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.07% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.07% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.07% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.07% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.07% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.07% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.07% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.07% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.07% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.07% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.07% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.07% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.07% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1406460 91.72% 92.80% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 110474 7.20% 100.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 61347 0.18% 0.18% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19254237 56.46% 56.64% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 25603 0.08% 56.72% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.72% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.72% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.72% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.72% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.72% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.72% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.72% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.72% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.72% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.72% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.72% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.72% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 8 0.00% 56.72% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.72% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.72% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.72% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 8 0.00% 56.72% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.72% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.72% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.72% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.72% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.72% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.72% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 363 0.00% 56.72% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.72% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 56.72% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.72% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11339596 33.25% 89.97% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3420808 10.03% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34101978 # Type of FU issued -system.cpu2.iq.rate 0.386117 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1533384 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.044965 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 106886012 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39309169 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 27255453 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 6518 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3637 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3015 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 35570601 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 3414 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 207005 # Number of loads that had data forwarded from stores -system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1561439 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1810 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9237 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 573725 # Number of stores squashed -system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5369512 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 345439 # Number of times an access to memory failed due to the cache being blocked -system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1179201 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 4914537 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 93208 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32084127 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 61095 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6480999 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3820565 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 371831 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 32634 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2570 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9237 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 106581 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 88238 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 194819 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33130261 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11055368 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 971717 # Number of squashed instructions skipped in execute -system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 73958 # number of nop insts executed -system.cpu2.iew.exec_refs 14443007 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3675866 # Number of branches executed -system.cpu2.iew.exec_stores 3387639 # Number of stores executed -system.cpu2.iew.exec_rate 0.375115 # Inst execution rate -system.cpu2.iew.wb_sent 32719575 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 27258468 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 15578435 # num instructions producing a value -system.cpu2.iew.wb_consumers 28336805 # num instructions consuming a value -system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.308632 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.549760 # average fanout of values written-back -system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7236388 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 357299 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 169355 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 35888560 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.684756 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.712853 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27290790 76.04% 76.04% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4165435 11.61% 87.65% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1253109 3.49% 91.14% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 644489 1.80% 92.94% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 571851 1.59% 94.53% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 314297 0.88% 95.41% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 396110 1.10% 96.51% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 285595 0.80% 97.31% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 966884 2.69% 100.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 35888560 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 19876644 # Number of instructions committed -system.cpu2.commit.committedOps 24574906 # Number of ops (including micro ops) committed -system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8166400 # Number of memory references committed -system.cpu2.commit.loads 4919560 # Number of loads committed -system.cpu2.commit.membars 94646 # Number of memory barriers committed -system.cpu2.commit.branches 3146883 # Number of branches committed -system.cpu2.commit.fp_insts 2975 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 21821277 # Number of committed integer instructions. -system.cpu2.commit.function_calls 294032 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 966884 # number cycles where commit BW limit reached -system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 66205278 # The number of ROB reads -system.cpu2.rob.rob_writes 64842405 # The number of ROB writes -system.cpu2.timesIdled 359398 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 51252392 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3567238209 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 19827262 # Number of Instructions Simulated -system.cpu2.committedOps 24525524 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 19827262 # Number of Instructions Simulated -system.cpu2.cpi 4.454488 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.454488 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.224493 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.224493 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 153057849 # number of integer regfile reads -system.cpu2.int_regfile_writes 29069811 # number of integer regfile writes -system.cpu2.fp_regfile_reads 22288 # number of floating regfile reads -system.cpu2.fp_regfile_writes 20782 # number of floating regfile writes -system.cpu2.misc_regfile_reads 9001591 # number of misc regfile reads -system.cpu2.misc_regfile_writes 241415 # number of misc regfile writes -system.iocache.replacements 0 # number of replacements -system.iocache.tagsinuse 0 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.avg_refs nan # Average number of references to valid blocks. -system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 981127238281 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 981127238281 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 981127238281 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 981127238281 # number of overall MSHR uncacheable cycles -system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency -system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.kern.inst.arm 0 # number of arm instructions executed -system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed - ----------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini index 85470f003..9fab0b34a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/projects/pd/randd/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 dtb_filename= @@ -19,7 +19,7 @@ enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -65,7 +65,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img read_only=true [system.cpu0] @@ -1000,6 +1000,7 @@ children=badaddr_responder block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio @@ -1025,25 +1026,27 @@ pio=system.membus.default [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 clock=1000 conf_table_reported=true in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false @@ -1173,7 +1176,7 @@ warn_access= pio=system.iobus.master[24] [system.realview.gic] -type=Gic +type=Pl390 clock=1000 cpu_addr=520093952 cpu_pio_delay=10000 @@ -1452,6 +1455,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=8 master=system.l2c.cpu_side diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr index 4d4ac5cf7..5a85b4fca 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr @@ -14,3 +14,7 @@ warn: instruction 'mcr icimvau' unimplemented warn: LCD dual screen mode not supported warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr bpiallis' unimplemented +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 5746894a9..1af17ec8e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,131 +1,127 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.542409 # Number of seconds simulated -sim_ticks 2542409356000 # Number of ticks simulated -final_tick 2542409356000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.542296 # Number of seconds simulated +sim_ticks 2542295570500 # Number of ticks simulated +final_tick 2542295570500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 77322 # Simulator instruction rate (inst/s) -host_op_rate 99492 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3259551931 # Simulator tick rate (ticks/s) -host_mem_usage 413868 # Number of bytes of host memory used -host_seconds 779.99 # Real time elapsed on the host -sim_insts 60310148 # Number of instructions simulated -sim_ops 77602492 # Number of ops (including micro ops) simulated +host_inst_rate 70655 # Simulator instruction rate (inst/s) +host_op_rate 90914 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2978397497 # Simulator tick rate (ticks/s) +host_mem_usage 409668 # Number of bytes of host memory used +host_seconds 853.58 # Real time elapsed on the host +sim_insts 60309877 # Number of instructions simulated +sim_ops 77602149 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1280 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 506624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4283408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 292928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4810268 # Number of bytes read from this memory -system.physmem.bytes_read::total 131006892 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 506624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 292928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799552 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu0.inst 504448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4169680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 296128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4925148 # Number of bytes read from this memory +system.physmem.bytes_read::total 131008300 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 504448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 296128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 800576 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 3787072 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1340604 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1675508 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1346312 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1669800 # Number of bytes written to this memory system.physmem.bytes_written::total 6803184 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 25 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 20 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7916 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 66962 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 21 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4577 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 75167 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293487 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 7882 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 65185 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4627 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 76962 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293509 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 59173 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 335151 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 418877 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 336578 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 417450 # Number of write requests responded to by this memory system.physmem.num_writes::total 813201 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47636124 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 629 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.clcd 47638256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 503 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 199269 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1684783 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 529 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 115217 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1892012 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51528638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 199269 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 115217 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314486 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1489560 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 527297 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 659024 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2675881 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1489560 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47636124 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 629 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 198422 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1640124 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 378 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 116481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1937284 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51531498 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 198422 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 116481 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314903 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1489627 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 529565 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 656808 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2676000 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1489627 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47638256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 503 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 199269 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2212080 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 529 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 115217 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2551035 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54204519 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293487 # Total number of read requests seen +system.physmem.bw_total::cpu0.inst 198422 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2169689 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 378 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 116481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2594092 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54207499 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293509 # Total number of read requests seen system.physmem.writeReqs 813201 # Total number of write requests seen -system.physmem.cpureqs 218488 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 978783168 # Total number of bytes read from memory +system.physmem.cpureqs 218507 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 978784576 # Total number of bytes read from memory system.physmem.bytesWritten 52044864 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131006892 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 131008300 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 6803184 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 10 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4687 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 956241 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 955734 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 955678 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 956495 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 956264 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 955436 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 955557 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 956169 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 956091 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 955615 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 955522 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 955928 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956030 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 955423 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 955313 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955981 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50841 # Track writes on a per bank basis +system.physmem.servicedByWrQ 14 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 956235 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 955738 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 955673 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 956489 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 956267 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 955445 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 955564 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 956162 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 956093 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 955609 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 955524 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 955926 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 956035 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 955433 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 955318 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 955984 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50833 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 50416 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50438 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50906 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50278 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50865 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51363 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50911 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50805 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51195 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51248 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50723 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50636 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51230 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50435 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50911 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50191 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50281 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50860 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51366 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50906 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50808 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51188 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51253 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50731 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50630 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51233 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1790732 # Number of times wr buffer was full causing retry -system.physmem.totGap 2542408198000 # Total gap between requests +system.physmem.numWrRetry 1856479 # Number of times wr buffer was full causing retry +system.physmem.totGap 2542294418500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 43 # Categorize read packet sizes system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154628 # Categorize read packet sizes +system.physmem.readPktSize::6 154650 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 2544760 # categorize write packet sizes +system.physmem.writePktSize::2 2610507 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes @@ -138,31 +134,31 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4687 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4684 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1054866 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 991514 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 961470 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3604976 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2718322 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2722144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2700252 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60049 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59439 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 110004 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 160498 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 109966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 10070 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 9996 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 10911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8954 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1054657 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 991834 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 961504 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3604952 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2718225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2722186 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2700242 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60067 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59423 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 110017 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 160496 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 109935 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 10065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 9993 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 11014 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8845 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -174,60 +170,60 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2915 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3785 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2748 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2931 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35358 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35230 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 35223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32404 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 31921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 31858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 31803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 31723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 31647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 31605 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32606 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32532 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32485 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 346733530557 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 439908911807 # Sum of mem lat for all requests -system.physmem.totBusLat 76467385000 # Total cycles spent in databus access -system.physmem.totBankLat 16707996250 # Total cycles spent in bank access -system.physmem.avgQLat 22671.99 # Average queueing delay per request -system.physmem.avgBankLat 1092.49 # Average bank access latency per request +system.physmem.totQLat 346840685210 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 440008538960 # Sum of mem lat for all requests +system.physmem.totBusLat 76467475000 # Total cycles spent in databus access +system.physmem.totBankLat 16700378750 # Total cycles spent in bank access +system.physmem.avgQLat 22678.97 # Average queueing delay per request +system.physmem.avgBankLat 1091.99 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28764.48 # Average memory access latency -system.physmem.avgRdBW 384.98 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 28770.96 # Average memory access latency +system.physmem.avgRdBW 385.00 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.47 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.53 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.17 # Data bus utilization in percentage system.physmem.avgRdQLen 0.17 # Average read queue length over time -system.physmem.avgWrQLen 1.11 # Average write queue length over time -system.physmem.readRowHits 15218342 # Number of row buffer hits during reads -system.physmem.writeRowHits 794645 # Number of row buffer hits during writes +system.physmem.avgWrQLen 1.14 # Average write queue length over time +system.physmem.readRowHits 15218397 # Number of row buffer hits during reads +system.physmem.writeRowHits 794710 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.72 # Row buffer hit rate for writes -system.physmem.avgGap 157847.98 # Average gap between requests +system.physmem.writeRowHitRate 97.73 # Row buffer hit rate for writes +system.physmem.avgGap 157840.70 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory @@ -240,239 +236,225 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 64396 # number of replacements -system.l2c.tagsinuse 51411.059605 # Cycle average of tags in use -system.l2c.total_refs 1936288 # Total number of references to valid blocks. -system.l2c.sampled_refs 129787 # Sample count of references to valid blocks. -system.l2c.avg_refs 14.918967 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2506346605000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36969.089517 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 15.370678 # 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mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.091642 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000618 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000264 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015557 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.195830 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000492 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009544 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.253417 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091642 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 55339.400000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42800.530460 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44398.583251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 79120.857143 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 56252 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 46348.315490 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 46287.086671 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 44663.967196 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10068.681646 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42838.515909 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44601.319314 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 53068.533333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 46101.216123 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 46302.841888 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 44663.031012 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10060.224093 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10037.748110 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39996.972474 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 36779.206178 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 38271.613142 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 55521.920000 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10032.380233 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39775.018281 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37292.993425 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 38412.050085 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 55339.400000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42800.530460 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40389.705841 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79120.857143 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 56252 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 46348.315490 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37350.714703 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39214.232388 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 55521.920000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42838.515909 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40217.548424 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 53068.533333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 46101.216123 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37825.820219 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39335.413644 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 55339.400000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42800.530460 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40389.705841 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79120.857143 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 56252 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 46348.315490 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37350.714703 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39214.232388 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42838.515909 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40217.548424 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 53068.533333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 46101.216123 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37825.820219 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39335.413644 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -667,680 +637,680 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 7548901 # Number of BP lookups -system.cpu0.branchPred.condPredicted 6013590 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 377467 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4898170 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4008296 # Number of BTB hits +system.cpu0.branchPred.lookups 7620138 # Number of BP lookups +system.cpu0.branchPred.condPredicted 6076880 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 380507 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4965064 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4053585 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 81.832521 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 726547 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 38944 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 81.642150 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 731859 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 39538 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25977003 # DTB read hits -system.cpu0.dtb.read_misses 44168 # DTB read misses -system.cpu0.dtb.write_hits 5905544 # DTB write hits -system.cpu0.dtb.write_misses 10435 # DTB write misses +system.cpu0.dtb.read_hits 26058653 # DTB read hits +system.cpu0.dtb.read_misses 40101 # DTB read misses +system.cpu0.dtb.write_hits 5895373 # DTB write hits +system.cpu0.dtb.write_misses 9447 # DTB write misses system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 753 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 8487 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1476 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 307 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 771 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 5619 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1431 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 273 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 629 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 26021171 # DTB read accesses -system.cpu0.dtb.write_accesses 5915979 # DTB write accesses +system.cpu0.dtb.perms_faults 647 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 26098754 # DTB read accesses +system.cpu0.dtb.write_accesses 5904820 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31882547 # DTB hits -system.cpu0.dtb.misses 54603 # DTB misses -system.cpu0.dtb.accesses 31937150 # DTB accesses -system.cpu0.itb.inst_hits 6053570 # ITB inst hits -system.cpu0.itb.inst_misses 7437 # ITB inst misses +system.cpu0.dtb.hits 31954026 # DTB hits +system.cpu0.dtb.misses 49548 # DTB misses +system.cpu0.dtb.accesses 32003574 # DTB accesses +system.cpu0.itb.inst_hits 6112115 # ITB inst hits +system.cpu0.itb.inst_misses 7637 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 753 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2703 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 771 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2623 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1556 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1579 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 6061007 # ITB inst accesses -system.cpu0.itb.hits 6053570 # DTB hits -system.cpu0.itb.misses 7437 # DTB misses -system.cpu0.itb.accesses 6061007 # DTB accesses -system.cpu0.numCycles 238938486 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 6119752 # ITB inst accesses +system.cpu0.itb.hits 6112115 # DTB hits +system.cpu0.itb.misses 7637 # DTB misses +system.cpu0.itb.accesses 6119752 # DTB accesses +system.cpu0.numCycles 239063312 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15394391 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 47363199 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7548901 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4734843 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10514679 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2521350 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 88217 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 49746520 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1647 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1973 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 54986 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 100350 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 256 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6051440 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 388609 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3416 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 77647495 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.755624 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.112120 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15490963 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 47835555 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7620138 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4785444 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10608217 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2561094 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 89115 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 49527666 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1654 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1892 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 49952 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 101088 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 226 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6110008 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 396628 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3581 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 77642580 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.762278 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.119818 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 67140338 86.47% 86.47% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 685224 0.88% 87.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 881384 1.14% 88.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1215413 1.57% 90.05% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1119001 1.44% 91.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 577018 0.74% 92.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1310230 1.69% 93.92% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 395483 0.51% 94.43% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4323404 5.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67041875 86.35% 86.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 689016 0.89% 87.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 885560 1.14% 88.37% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1228014 1.58% 89.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1141359 1.47% 91.43% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 577108 0.74% 92.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1324549 1.71% 93.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 398041 0.51% 94.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4357058 5.61% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77647495 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.031593 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.198223 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16447301 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 49466389 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9519649 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 555058 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1656976 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1018880 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 89951 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 55851060 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 301878 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1656976 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17376198 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 19158247 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 27017971 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9071618 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3364444 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 53098048 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 14247 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 629745 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2187800 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 13035 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 55196889 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 241870306 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 241822297 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 48009 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 40273759 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 14923130 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 426834 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 378971 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6800028 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10269000 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6780798 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1063277 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1318043 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 49318736 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1023913 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 62924434 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 96522 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10293246 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 26052938 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 249929 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77647495 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.810386 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.515841 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77642580 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.031875 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.200096 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16540886 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 49255967 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9607571 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 552371 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1683667 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1024811 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 90579 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 56316085 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 302289 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1683667 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17475063 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 18984775 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 27019953 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9154130 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3322955 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 53494037 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 13484 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 621738 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2157353 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 548 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 55660367 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 243519467 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 243471355 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 48112 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 40417937 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 15242430 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 429833 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 381699 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6758508 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10355148 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6782314 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1058612 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1316675 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 49644359 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1043369 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 63195717 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 96260 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10515144 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 26542188 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 266673 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77642580 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.813931 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.519230 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 54849449 70.64% 70.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 7244024 9.33% 79.97% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3688560 4.75% 84.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3114192 4.01% 88.73% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6252852 8.05% 96.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1400137 1.80% 98.59% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 804405 1.04% 99.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 228817 0.29% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 65059 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 54792876 70.57% 70.57% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 7218069 9.30% 79.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3694351 4.76% 84.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3145323 4.05% 88.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6277418 8.09% 96.76% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1407401 1.81% 98.57% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 809465 1.04% 99.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 231906 0.30% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 65771 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77647495 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77642580 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 28907 0.65% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 5 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4221672 94.79% 95.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 203228 4.56% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 29563 0.66% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 4 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4229523 94.72% 95.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 206294 4.62% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 196078 0.31% 0.31% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29762339 47.30% 47.61% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 47254 0.08% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1214 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.69% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26685508 42.41% 90.10% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6232016 9.90% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 195578 0.31% 0.31% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29951554 47.39% 47.70% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46938 0.07% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 6 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1212 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26776565 42.37% 90.15% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6223855 9.85% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 62924434 # Type of FU issued -system.cpu0.iq.rate 0.263350 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4453812 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.070780 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 208088796 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 60644934 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 43952872 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12311 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6553 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5522 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 67175656 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6512 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 321336 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 63195717 # Type of FU issued +system.cpu0.iq.rate 0.264347 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4465384 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.070660 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 208632682 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 61211746 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 44166006 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12339 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6563 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5520 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 67458994 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6529 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 322005 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2241404 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3447 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 16174 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 877395 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2276398 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3543 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 16033 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 889328 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17145295 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 358927 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17163737 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 367898 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1656976 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 14313344 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 236698 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 50458165 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 105115 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10269000 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6780798 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 724480 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 58024 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3552 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 16174 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 184745 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 145643 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 330388 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 61778089 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26333265 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1146345 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1683667 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 14223209 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 234272 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 50804503 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 105344 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10355148 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6782314 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 742198 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 56887 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3242 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 16033 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 187141 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 147345 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 334486 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 62025172 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26418520 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1170545 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 115516 # number of nop insts executed -system.cpu0.iew.exec_refs 32508411 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5980040 # Number of branches executed -system.cpu0.iew.exec_stores 6175146 # Number of stores executed -system.cpu0.iew.exec_rate 0.258552 # Inst execution rate -system.cpu0.iew.wb_sent 61260719 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 43958394 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24186405 # num instructions producing a value -system.cpu0.iew.wb_consumers 44536826 # num instructions consuming a value +system.cpu0.iew.exec_nop 116775 # number of nop insts executed +system.cpu0.iew.exec_refs 32585401 # number of memory reference insts executed +system.cpu0.iew.exec_branches 6028949 # Number of branches executed +system.cpu0.iew.exec_stores 6166881 # Number of stores executed +system.cpu0.iew.exec_rate 0.259451 # Inst execution rate +system.cpu0.iew.wb_sent 61495183 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 44171526 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24314220 # num instructions producing a value +system.cpu0.iew.wb_consumers 44686636 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.183974 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.543065 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.184769 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.544105 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 10181243 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 773984 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 288739 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75990519 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.523900 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.505441 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 10365934 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 776696 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 291216 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75958913 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.525792 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.508136 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 61812445 81.34% 81.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6884323 9.06% 90.40% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2031918 2.67% 93.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1127942 1.48% 94.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1041381 1.37% 95.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 554423 0.73% 96.66% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 699295 0.92% 97.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 364332 0.48% 98.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1474460 1.94% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 61730922 81.27% 81.27% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6914068 9.10% 90.37% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2040925 2.69% 93.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1133695 1.49% 94.55% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1039727 1.37% 95.92% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 547660 0.72% 96.64% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 699909 0.92% 97.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 371161 0.49% 98.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1480846 1.95% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75990519 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 31157319 # Number of instructions committed -system.cpu0.commit.committedOps 39811398 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75958913 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 31284581 # Number of instructions committed +system.cpu0.commit.committedOps 39938560 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13930999 # Number of memory references committed -system.cpu0.commit.loads 8027596 # Number of loads committed -system.cpu0.commit.membars 211461 # Number of memory barriers committed -system.cpu0.commit.branches 5178005 # Number of branches committed +system.cpu0.commit.refs 13971736 # Number of memory references committed +system.cpu0.commit.loads 8078750 # Number of loads committed +system.cpu0.commit.membars 212403 # Number of memory barriers committed +system.cpu0.commit.branches 5205711 # Number of branches committed system.cpu0.commit.fp_insts 5497 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 35182368 # Number of committed integer instructions. -system.cpu0.commit.function_calls 511213 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1474460 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 35286774 # Number of committed integer instructions. +system.cpu0.commit.function_calls 514203 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1480846 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 123547695 # The number of ROB reads -system.cpu0.rob.rob_writes 101683929 # The number of ROB writes -system.cpu0.timesIdled 881879 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 161290991 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2289851507 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 31079277 # Number of Instructions Simulated -system.cpu0.committedOps 39733356 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 31079277 # Number of Instructions Simulated -system.cpu0.cpi 7.688032 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 7.688032 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.130072 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.130072 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 279629599 # number of integer regfile reads -system.cpu0.int_regfile_writes 45168223 # number of integer regfile writes -system.cpu0.fp_regfile_reads 22746 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19898 # number of floating regfile writes -system.cpu0.misc_regfile_reads 15538839 # number of misc regfile reads -system.cpu0.misc_regfile_writes 427973 # number of misc regfile writes -system.cpu0.icache.replacements 984670 # number of replacements -system.cpu0.icache.tagsinuse 511.607871 # Cycle average of tags in use -system.cpu0.icache.total_refs 10994375 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 985182 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 11.159740 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6536916000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 357.062519 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 154.545352 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.697388 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.301846 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999234 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5513374 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5481001 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 10994375 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5513374 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5481001 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 10994375 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5513374 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5481001 # number of overall hits -system.cpu0.icache.overall_hits::total 10994375 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 537943 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 527405 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1065348 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 537943 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 527405 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1065348 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 537943 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 527405 # number of overall misses -system.cpu0.icache.overall_misses::total 1065348 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7287778496 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 7022356993 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14310135489 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7287778496 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 7022356993 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14310135489 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7287778496 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 7022356993 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14310135489 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6051317 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 6008406 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 12059723 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6051317 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 6008406 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 12059723 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6051317 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 6008406 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 12059723 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088897 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087778 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.088339 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088897 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087778 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.088339 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.088897 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087778 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.088339 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13547.492013 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13314.923053 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13432.357773 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13547.492013 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13314.923053 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13432.357773 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13547.492013 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13314.923053 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13432.357773 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4400 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 1635 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 334 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.173653 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 1635 # average number of cycles each access was blocked +system.cpu0.rob.rob_reads 123805555 # The number of ROB reads +system.cpu0.rob.rob_writes 102335061 # The number of ROB writes +system.cpu0.timesIdled 884089 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 161420732 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2289699870 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 31205252 # Number of Instructions Simulated +system.cpu0.committedOps 39859231 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 31205252 # Number of Instructions Simulated +system.cpu0.cpi 7.660996 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 7.660996 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.130531 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.130531 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 280760557 # number of integer regfile reads +system.cpu0.int_regfile_writes 45445732 # number of integer regfile writes +system.cpu0.fp_regfile_reads 22770 # number of floating regfile reads +system.cpu0.fp_regfile_writes 19806 # number of floating regfile writes +system.cpu0.misc_regfile_reads 15502985 # number of misc regfile reads +system.cpu0.misc_regfile_writes 430013 # number of misc regfile writes +system.cpu0.icache.replacements 984427 # number of replacements +system.cpu0.icache.tagsinuse 510.429233 # Cycle average of tags in use +system.cpu0.icache.total_refs 11039860 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 984939 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 11.208674 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 6522889000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 356.685952 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 153.743281 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.696652 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.300280 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.996932 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5569328 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 5470532 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 11039860 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5569328 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 5470532 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 11039860 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5569328 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 5470532 # number of overall hits +system.cpu0.icache.overall_hits::total 11039860 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 540556 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 524651 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1065207 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 540556 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 524651 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1065207 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 540556 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 524651 # number of overall misses +system.cpu0.icache.overall_misses::total 1065207 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7319258495 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6971682996 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14290941491 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7319258495 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 6971682996 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14290941491 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7319258495 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 6971682996 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14290941491 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6109884 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 5995183 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 12105067 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6109884 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 5995183 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 12105067 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6109884 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 5995183 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 12105067 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088472 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087512 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.087997 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088472 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087512 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.087997 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.088472 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087512 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.087997 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13540.240965 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13288.229692 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13416.116765 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13540.240965 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13288.229692 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13416.116765 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13540.240965 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13288.229692 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13416.116765 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4720 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 314 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.031847 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 40608 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39535 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 80143 # 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mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.080959 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.081368 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.081769 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.080959 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.081368 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.081769 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.080959 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.081368 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11958.162269 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11717.678442 # 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Average percentage of cache occupancy +system.cpu0.dcache.replacements 643954 # number of replacements +system.cpu0.dcache.tagsinuse 511.992718 # Cycle average of tags in use +system.cpu0.dcache.total_refs 21537903 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 644466 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.419766 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 43205000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 318.437002 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 193.555716 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.621947 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.378039 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7070467 # 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number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 125418 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 257293 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 127193 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 120434 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247627 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12671942 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 12086672 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24758614 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12671942 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 12086672 # 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number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 364769 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1269356 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1442834 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 2712190 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 679 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 700 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1379 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1491128 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1585831 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 3076959 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1491128 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1585831 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3076959 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 213739 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 172519 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 386258 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 119339 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 129584 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 248923 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6145 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 6087 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12232 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 4 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 6 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 10 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 333078 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 302103 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 635181 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 333078 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 302103 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 635181 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2903093500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2321765000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5224858500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3977310493 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4483624933 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8460935426 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 71679000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74936000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 146615000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 44000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 66000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 110000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6880403993 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6805389933 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13685793926 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6880403993 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6805389933 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13685793926 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91929858500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90426612500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182356471000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 14888104285 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 18626460302 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 33514564587 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106449564738 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 108906204622 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215355769360 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028155 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024825 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026543 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023127 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025607 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024352 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046279 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048510 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047366 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000024 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000042 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000032 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026102 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025152 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025638 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026102 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025152 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025638 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13584.124901 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13500.237496 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13546.131735 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33993.064715 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33818.242173 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33902.288204 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11660.740619 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12150.147929 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11905.062772 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106817962785 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109053072802 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215871035587 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028309 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024707 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026578 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023125 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025599 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024350 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046319 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048895 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047566 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000031 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000050 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026204 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025082 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025658 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026204 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025082 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025658 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13582.422955 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13458.024913 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13526.861580 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33327.834932 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34600.143019 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33990.171362 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11664.605370 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12310.826351 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11986.183780 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20968.742984 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22139.514867 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21529.455070 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20968.742984 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22139.514867 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21529.455070 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20657.035268 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22526.720797 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21546.289839 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20657.035268 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22526.720797 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21546.289839 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1355,324 +1325,324 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7102253 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5695769 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 349355 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4570648 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3841672 # Number of BTB hits +system.cpu1.branchPred.lookups 7047379 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5653088 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 345044 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4644809 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3819502 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 84.050927 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 676938 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 35276 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 82.231627 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 672042 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 34964 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25380131 # DTB read hits -system.cpu1.dtb.read_misses 40834 # DTB read misses -system.cpu1.dtb.write_hits 5811015 # DTB write hits -system.cpu1.dtb.write_misses 9771 # DTB write misses +system.cpu1.dtb.read_hits 25308350 # DTB read hits +system.cpu1.dtb.read_misses 36279 # DTB read misses +system.cpu1.dtb.write_hits 5820677 # DTB write hits +system.cpu1.dtb.write_misses 9386 # DTB write misses system.cpu1.dtb.flush_tlb 254 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 686 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 8065 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1494 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 315 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 668 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 5518 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1305 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 250 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 637 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25420965 # DTB read accesses -system.cpu1.dtb.write_accesses 5820786 # DTB write accesses +system.cpu1.dtb.perms_faults 636 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25344629 # DTB read accesses +system.cpu1.dtb.write_accesses 5830063 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31191146 # DTB hits -system.cpu1.dtb.misses 50605 # DTB misses -system.cpu1.dtb.accesses 31241751 # DTB accesses -system.cpu1.itb.inst_hits 6010554 # ITB inst hits -system.cpu1.itb.inst_misses 6924 # ITB inst misses +system.cpu1.dtb.hits 31129027 # DTB hits +system.cpu1.dtb.misses 45665 # DTB misses +system.cpu1.dtb.accesses 31174692 # DTB accesses +system.cpu1.itb.inst_hits 5997294 # ITB inst hits +system.cpu1.itb.inst_misses 6928 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 254 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 686 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2690 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 668 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2607 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1453 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1462 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 6017478 # ITB inst accesses -system.cpu1.itb.hits 6010554 # DTB hits -system.cpu1.itb.misses 6924 # DTB misses -system.cpu1.itb.accesses 6017478 # DTB accesses -system.cpu1.numCycles 234669310 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 6004222 # ITB inst accesses +system.cpu1.itb.hits 5997294 # DTB hits +system.cpu1.itb.misses 6928 # DTB misses +system.cpu1.itb.accesses 6004222 # DTB accesses +system.cpu1.numCycles 234192897 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 15209580 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 46712783 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7102253 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4518610 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 10317375 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2619576 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 83943 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 47843149 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1067 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 2062 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 49108 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 95676 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 186 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 6008408 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 439180 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3193 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 75397416 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.769986 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.133362 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 15145693 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 46615728 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7047379 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4491544 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 10277592 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2615595 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 81100 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 47506260 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 991 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 2050 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 43629 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 94802 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 132 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5995185 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 443145 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3161 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 74942742 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.773391 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.139188 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 65087895 86.33% 86.33% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 627947 0.83% 87.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 837408 1.11% 88.27% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1205044 1.60% 89.87% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1066340 1.41% 91.28% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 537838 0.71% 92.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1370888 1.82% 93.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 355288 0.47% 94.29% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4308768 5.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 64672921 86.30% 86.30% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 620255 0.83% 87.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 831184 1.11% 88.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1205105 1.61% 89.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1036791 1.38% 91.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 535666 0.71% 91.94% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1369144 1.83% 93.77% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 351637 0.47% 94.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4320039 5.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 75397416 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.030265 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.199058 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 16234163 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 47629419 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9365333 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 455355 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1710994 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 954633 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 86850 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 54991941 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 289065 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1710994 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 17174187 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 18737860 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 25818505 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8802452 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3151356 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 51852963 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 7784 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 495819 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2156102 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 16790 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 53921236 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 237794819 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 237752758 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 42061 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 38119457 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 15801778 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 406275 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 360043 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6312412 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9898501 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6682455 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 887681 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1092966 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 47793867 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 962748 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 60992947 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 83561 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10588710 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 27790687 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 254225 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 75397416 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.808953 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.518534 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 74942742 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.030092 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.199048 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 16159158 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 47296340 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9320957 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 457304 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1706877 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 946060 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 86144 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 54858013 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 286862 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1706877 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 17095317 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 18544880 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 25731919 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8763106 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3098607 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 51692102 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 7152 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 482288 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2118635 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 58 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 53768769 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 237295359 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 237252975 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 42384 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 37974901 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 15793867 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 403461 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 357400 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6244351 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9843526 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6693253 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 891235 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1110531 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 47673025 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 943085 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 60813772 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 81704 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10584682 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 28040387 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 237278 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 74942742 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.811470 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.521589 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 53544512 71.02% 71.02% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6720979 8.91% 79.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3575565 4.74% 84.67% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2884458 3.83% 88.50% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6227948 8.26% 96.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1437657 1.91% 98.67% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 736271 0.98% 99.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 210447 0.28% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 59579 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 53203952 70.99% 70.99% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6663470 8.89% 79.88% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3519082 4.70% 84.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2892768 3.86% 88.44% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6218608 8.30% 96.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1439258 1.92% 98.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 735883 0.98% 99.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 209954 0.28% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 59767 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 75397416 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 74942742 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 24253 0.55% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 3 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4149284 94.86% 95.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 200652 4.59% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 24319 0.56% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.56% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4142702 94.84% 95.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 201068 4.60% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 167588 0.27% 0.27% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28559163 46.82% 47.10% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46488 0.08% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 5 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 897 0.00% 47.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 47.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.18% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26112884 42.81% 89.99% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6105909 10.01% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 168088 0.28% 0.28% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 28444166 46.77% 47.05% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46611 0.08% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 900 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.13% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26040619 42.82% 89.95% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6113365 10.05% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 60992947 # Type of FU issued -system.cpu1.iq.rate 0.259910 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4374192 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.071716 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 201880877 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 59353845 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 41952881 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 10603 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 5821 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 4743 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 65193949 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 5602 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 306044 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 60813772 # Type of FU issued +system.cpu1.iq.rate 0.259674 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4368089 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.071827 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 201054983 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 59209073 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 41787342 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 10574 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 5911 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 4752 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 65008196 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 5577 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 302847 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2270775 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2267035 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3168 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 14837 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 853246 # Number of stores squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 14674 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 853664 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 16957357 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 451019 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 16940133 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 457083 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1710994 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 14077639 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 237686 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48863462 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 99358 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9898501 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6682455 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 687943 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 54116 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 4064 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 14837 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 169399 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 135230 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 304629 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 59633634 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25710347 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1359313 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1706877 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 13961840 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 229523 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 48721689 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 98782 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9843526 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6693253 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 669936 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 49642 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3791 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 14674 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 166878 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 133542 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 300420 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 59454145 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25635874 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1359627 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 106847 # number of nop insts executed -system.cpu1.iew.exec_refs 31763994 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5570991 # Number of branches executed -system.cpu1.iew.exec_stores 6053647 # Number of stores executed -system.cpu1.iew.exec_rate 0.254118 # Inst execution rate -system.cpu1.iew.wb_sent 59059835 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 41957624 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 22877560 # num instructions producing a value -system.cpu1.iew.wb_consumers 41856848 # num instructions consuming a value +system.cpu1.iew.exec_nop 105579 # number of nop insts executed +system.cpu1.iew.exec_refs 31697240 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5530994 # Number of branches executed +system.cpu1.iew.exec_stores 6061366 # Number of stores executed +system.cpu1.iew.exec_rate 0.253868 # Inst execution rate +system.cpu1.iew.wb_sent 58875000 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 41792094 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 22753184 # num instructions producing a value +system.cpu1.iew.wb_consumers 41716740 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.178795 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.546567 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.178452 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.545421 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 10488461 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 708523 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 263786 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 73686422 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.514905 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.496046 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 10509796 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 705807 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 260176 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 73235865 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.516331 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.496791 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 60141742 81.62% 81.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6665026 9.05% 90.66% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1916982 2.60% 93.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1022287 1.39% 94.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 952512 1.29% 95.95% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 518669 0.70% 96.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 704589 0.96% 97.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 372223 0.51% 98.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1392392 1.89% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 59723279 81.55% 81.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6657456 9.09% 90.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1906988 2.60% 93.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1010218 1.38% 94.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 959564 1.31% 95.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 524950 0.72% 96.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 702340 0.96% 97.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 373722 0.51% 98.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1377348 1.88% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 73686422 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 29303210 # Number of instructions committed -system.cpu1.commit.committedOps 37941475 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 73235865 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 29175677 # Number of instructions committed +system.cpu1.commit.committedOps 37813970 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13456935 # Number of memory references committed -system.cpu1.commit.loads 7627726 # Number of loads committed -system.cpu1.commit.membars 192181 # Number of memory barriers committed -system.cpu1.commit.branches 4783662 # Number of branches committed +system.cpu1.commit.refs 13416080 # Number of memory references committed +system.cpu1.commit.loads 7576491 # Number of loads committed +system.cpu1.commit.membars 191234 # Number of memory barriers committed +system.cpu1.commit.branches 4755917 # Number of branches committed system.cpu1.commit.fp_insts 4715 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 33675461 # Number of committed integer instructions. -system.cpu1.commit.function_calls 480108 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1392392 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 33570741 # Number of committed integer instructions. +system.cpu1.commit.function_calls 477112 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1377348 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 119835622 # The number of ROB reads -system.cpu1.rob.rob_writes 98622587 # The number of ROB writes -system.cpu1.timesIdled 873829 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 159271894 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2285541005 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 29230871 # Number of Instructions Simulated -system.cpu1.committedOps 37869136 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 29230871 # Number of Instructions Simulated -system.cpu1.cpi 8.028133 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 8.028133 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.124562 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.124562 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 270257014 # number of integer regfile reads -system.cpu1.int_regfile_writes 43086162 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22099 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19636 # number of floating regfile writes -system.cpu1.misc_regfile_reads 14849439 # number of misc regfile reads -system.cpu1.misc_regfile_writes 404495 # number of misc regfile writes +system.cpu1.rob.rob_reads 119309924 # The number of ROB reads +system.cpu1.rob.rob_writes 98406667 # The number of ROB writes +system.cpu1.timesIdled 873323 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 159250155 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2285809379 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 29104625 # Number of Instructions Simulated +system.cpu1.committedOps 37742918 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 29104625 # Number of Instructions Simulated +system.cpu1.cpi 8.046587 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 8.046587 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.124276 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.124276 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 269354983 # number of integer regfile reads +system.cpu1.int_regfile_writes 42881539 # number of integer regfile writes +system.cpu1.fp_regfile_reads 22070 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19722 # number of floating regfile writes +system.cpu1.misc_regfile_reads 14807942 # number of misc regfile reads +system.cpu1.misc_regfile_writes 402452 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1687,17 +1657,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192737213912 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1192737213912 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192737213912 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1192737213912 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192818443837 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1192818443837 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192818443837 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1192818443837 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83053 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83054 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed |