diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux')
12 files changed, 3734 insertions, 3624 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index f66d752af..219ef17ea 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -8,13 +8,14 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem -children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver +children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver atags_addr=256 boot_loader=/projects/pd/randd/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 -clock=1 +clock=1000 dtb_filename= early_kernel_symbols=false +enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 @@ -39,7 +40,7 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge -clock=1 +clock=1000 delay=50000 ranges=268435456:520093695 1073741824:1610612735 req_size=16 @@ -69,7 +70,7 @@ read_only=true [system.cpu] type=DerivO3CPU -children=checker dcache dtb fuPool icache interrupts itb tracer +children=checker dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -167,7 +168,7 @@ icache_port=system.cpu.icache.cpu_side type=O3Checker children=dtb itb tracer checker=Null -clock=1 +clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true @@ -200,10 +201,10 @@ walker=system.cpu.checker.dtb.walker [system.cpu.checker.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[5] +port=system.cpu.toL2Bus.slave[5] [system.cpu.checker.itb] type=ArmTLB @@ -213,10 +214,10 @@ walker=system.cpu.checker.itb.walker [system.cpu.checker.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[4] +port=system.cpu.toL2Bus.slave[4] [system.cpu.checker.tracer] type=ExeTracer @@ -226,10 +227,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -237,7 +238,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -246,7 +247,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.toL2Bus.slave[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -256,10 +257,10 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.fuPool] type=FUPool @@ -529,10 +530,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -540,7 +541,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -549,7 +550,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.toL2Bus.slave[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts @@ -562,10 +563,47 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[2] +port=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=8 +block_size=64 +clock=500 +forward_snoops=true +hash_delay=1 +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +response_latency=20 +size=4194304 +subblock_size=0 +system=system +tgts_per_mshr=12 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[2] + +[system.cpu.toL2Bus] +type=CoherentBus +block_size=64 +clock=500 +header_cycles=1 +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -589,18 +627,18 @@ type=BaseCache addr_ranges=0:268435455 assoc=8 block_size=64 -clock=1 +clock=1000 forward_snoops=false hash_delay=1 -hit_latency=50000 -is_top_level=false +hit_latency=50 +is_top_level=true max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=50000 +response_latency=50 size=1024 subblock_size=0 system=system @@ -611,33 +649,6 @@ write_buffers=8 cpu_side=system.iobus.master[25] mem_side=system.membus.slave[1] -[system.l2c] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=8 -block_size=64 -clock=1 -forward_snoops=true -hash_delay=1 -hit_latency=10000 -is_top_level=false -max_miss_count=0 -mshrs=92 -prefetch_on_access=false -prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=10000 -size=4194304 -subblock_size=0 -system=system -tgts_per_mshr=16 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[2] - [system.membus] type=CoherentBus children=badaddr_responder @@ -648,11 +659,11 @@ use_default_range=false width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio -slave=system.system_port system.iocache.mem_side system.l2c.mem_side +slave=system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side [system.membus.badaddr_responder] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=0 pio_latency=100000 @@ -668,15 +679,28 @@ warn_access=warn pio=system.membus.default [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=true in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[2] @@ -691,7 +715,7 @@ system=system [system.realview.a9scu] type=A9SCU -clock=1 +clock=1000 pio_addr=520093696 pio_latency=100000 system=system @@ -700,7 +724,7 @@ pio=system.membus.master[5] [system.realview.aaci_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -747,7 +771,7 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 -clock=1 +clock=1000 config_latency=20000 ctrl_offset=2 disks=system.cf0 @@ -778,7 +802,7 @@ pio=system.iobus.master[4] [system.realview.dmac_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -787,7 +811,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake -clock=1 +clock=1000 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -804,7 +828,7 @@ pio=system.iobus.master[24] [system.realview.gic] type=Gic -clock=1 +clock=1000 cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 @@ -818,7 +842,7 @@ pio=system.membus.master[3] [system.realview.gpio0_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -828,7 +852,7 @@ pio=system.iobus.master[16] [system.realview.gpio1_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -838,7 +862,7 @@ pio=system.iobus.master[17] [system.realview.gpio2_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -848,7 +872,7 @@ pio=system.iobus.master[18] [system.realview.kmi0] type=Pl050 amba_id=1314896 -clock=1 +clock=1000 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -862,7 +886,7 @@ pio=system.iobus.master[5] [system.realview.kmi1] type=Pl050 amba_id=1314896 -clock=1 +clock=1000 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -875,7 +899,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -904,7 +928,7 @@ pio=system.membus.master[6] [system.realview.mmc_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -914,7 +938,7 @@ pio=system.iobus.master[22] [system.realview.nvmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 @@ -926,7 +950,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl -clock=1 +clock=1000 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -938,7 +962,7 @@ pio=system.iobus.master[1] [system.realview.rtc] type=PL031 amba_id=3412017 -clock=1 +clock=1000 gic=system.realview.gic int_delay=100000 int_num=42 @@ -951,7 +975,7 @@ pio=system.iobus.master[23] [system.realview.sci_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -961,7 +985,7 @@ pio=system.iobus.master[20] [system.realview.smc_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -971,7 +995,7 @@ pio=system.iobus.master[13] [system.realview.sp810_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -981,7 +1005,7 @@ pio=system.iobus.master[14] [system.realview.ssp_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -991,7 +1015,7 @@ pio=system.iobus.master[19] [system.realview.timer0] type=Sp804 amba_id=1316868 -clock=1 +clock=1000 clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -1005,7 +1029,7 @@ pio=system.iobus.master[2] [system.realview.timer1] type=Sp804 amba_id=1316868 -clock=1 +clock=1000 clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -1018,7 +1042,7 @@ pio=system.iobus.master[3] [system.realview.uart] type=Pl011 -clock=1 +clock=1000 end_on_eot=false gic=system.realview.gic int_delay=100000 @@ -1033,7 +1057,7 @@ pio=system.iobus.master[0] [system.realview.uart1_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -1043,7 +1067,7 @@ pio=system.iobus.master[10] [system.realview.uart2_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -1053,7 +1077,7 @@ pio=system.iobus.master[11] [system.realview.uart3_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -1063,7 +1087,7 @@ pio=system.iobus.master[12] [system.realview.watchdog_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -1077,16 +1101,6 @@ number=0 output=true port=3456 -[system.toL2Bus] -type=CoherentBus -block_size=64 -clock=1000 -header_cycles=1 -use_default_range=false -width=8 -master=system.l2c.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port - [system.vncserver] type=VncServer frame_capture=false diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr index 3e85e4166..2082cdfd9 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr @@ -10,34 +10,27 @@ warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented -warn: 6471379000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748 -warn: 6479236500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 -warn: 6488789500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 -warn: 6527432500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 -warn: 6543641500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 -warn: 7089434000: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 -warn: 12809896500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc -warn: 12854316500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc -warn: 13169361500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc -warn: 14424922500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc -warn: 14474529500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc -warn: 15519752500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc -warn: 15669382500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc +warn: 5946987000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748 +warn: 5954355500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 +warn: 5963229500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 +warn: 5999905500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 +warn: 6015449500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 warn: LCD dual screen mode not supported -warn: 54391557500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 +warn: 51801575500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors -warn: 816692532000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1 warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr bpiallis' unimplemented -warn: 2486377425500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 -warn: 2500398254500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2501706856500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0 -warn: 2523057678500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2523647855500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2529994034500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 -warn: 2530576345500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0 -warn: 2531219324500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 -warn: 2531220454500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 +warn: 2473940227500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 +warn: 2487729164500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2488940395000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0 +warn: 2503139484500: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0 +warn: 2510001697500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2510516362000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2516240346500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 +warn: 2516753495000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0 +warn: 2517315503000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 +warn: 2517316610000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 +warn: 2517867351500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0 hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout index 5011d2336..a3de8bb34 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 12:35:22 +gem5 compiled Nov 1 2012 15:18:10 +gem5 started Nov 2 2012 01:09:00 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker Global frequency set at 1000000000000 ticks per second info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2537929870500 because m5_exit instruction encountered +Exiting @ tick 2523500318000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 3725b6e15..a24f5a985 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,114 +1,114 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.523629 # Number of seconds simulated -sim_ticks 2523629285500 # Number of ticks simulated -final_tick 2523629285500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.523500 # Number of seconds simulated +sim_ticks 2523500318000 # Number of ticks simulated +final_tick 2523500318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 68763 # Simulator instruction rate (inst/s) -host_op_rate 88448 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2863680529 # Simulator tick rate (ticks/s) -host_mem_usage 399792 # Number of bytes of host memory used -host_seconds 881.25 # Real time elapsed on the host -sim_insts 60597236 # Number of instructions simulated -sim_ops 77945371 # Number of ops (including micro ops) simulated +host_inst_rate 54734 # Simulator instruction rate (inst/s) +host_op_rate 70403 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2279341302 # Simulator tick rate (ticks/s) +host_mem_usage 401036 # Number of bytes of host memory used +host_seconds 1107.12 # Real time elapsed on the host +sim_insts 60596849 # Number of instructions simulated +sim_ops 77944928 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 799232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9095696 # Number of bytes read from this memory -system.physmem.bytes_read::total 129436176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 799232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799232 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784448 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 2752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 798592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094096 # Number of bytes read from this memory +system.physmem.bytes_read::total 129433232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 798592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798592 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784064 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800520 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800136 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 55 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12488 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142154 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096906 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59132 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 43 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12478 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142129 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096860 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59126 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813150 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47367363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1395 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 316699 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3604212 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51289695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 316699 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 316699 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1499605 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1195133 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2694738 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1499605 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47367363 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 316699 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4799345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53984433 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096906 # Total number of read requests seen -system.physmem.writeReqs 813150 # Total number of write requests seen -system.physmem.cpureqs 218484 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966201984 # Total number of bytes read from memory -system.physmem.bytesWritten 52041600 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129436176 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6800520 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 390 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4690 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943619 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943957 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943433 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 943463 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943389 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943250 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943110 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943289 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943778 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943634 # Track reads on a per bank basis +system.physmem.num_writes::total 813144 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47369784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1091 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 316462 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3603763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51291149 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 316462 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 316462 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1499530 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1195194 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2694724 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1499530 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47369784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 316462 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4798956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53985873 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096860 # Total number of read requests seen +system.physmem.writeReqs 813144 # Total number of write requests seen +system.physmem.cpureqs 218421 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966199040 # Total number of bytes read from memory +system.physmem.bytesWritten 52041216 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129433232 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6800136 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 334 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4679 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943626 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943958 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943414 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 943465 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943376 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943238 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943099 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943292 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943771 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943641 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 943712 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943686 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943739 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943592 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 943646 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943219 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50102 # Track writes on a per bank basis +system.physmem.perBankRdReqs::11 943689 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943743 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943611 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 943653 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943238 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50107 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 50378 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 49977 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50030 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50914 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50821 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50673 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50817 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51140 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51219 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51127 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 49961 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50027 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50912 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50814 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50662 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50821 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51143 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51225 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51129 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 51111 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51352 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51299 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51032 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51353 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51175 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51296 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51030 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1156336 # Number of times wr buffer was full causing retry -system.physmem.totGap 2523628152000 # Total gap between requests +system.physmem.numWrRetry 1153879 # Number of times wr buffer was full causing retry +system.physmem.totGap 2523499110500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154662 # Categorize read packet sizes +system.physmem.readPktSize::6 154616 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 1910354 # categorize write packet sizes +system.physmem.writePktSize::2 1907897 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 59132 # categorize write packet sizes +system.physmem.writePktSize::6 59126 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -117,28 +117,28 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4690 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4679 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 14955823 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 89957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2881 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2059 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1873 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1682 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 14954842 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 89676 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6568 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2998 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2443 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2395 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1858 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1270 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 6283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 9566 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 13077 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 563 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 50 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1236 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 6388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 9595 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 13055 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 48 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 31 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -153,15 +153,15 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2950 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4040 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see @@ -176,37 +176,37 @@ system.physmem.wrQLenPdf::19 35354 # Wh system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 31809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 31595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 31423 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 31264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 31840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 31628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 31465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 31314 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 46839255594 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 317495505594 # Sum of mem lat for all requests -system.physmem.totBusLat 60386064000 # Total cycles spent in databus access -system.physmem.totBankLat 210270186000 # Total cycles spent in bank access -system.physmem.avgQLat 3102.65 # Average queueing delay per request -system.physmem.avgBankLat 13928.39 # Average bank access latency per request +system.physmem.totQLat 47052553851 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 317720785851 # Sum of mem lat for all requests +system.physmem.totBusLat 60386104000 # Total cycles spent in databus access +system.physmem.totBankLat 210282128000 # Total cycles spent in bank access +system.physmem.avgQLat 3116.78 # Average queueing delay per request +system.physmem.avgBankLat 13929.17 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 21031.04 # Average memory access latency -system.physmem.avgRdBW 382.86 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 21045.95 # Average memory access latency +system.physmem.avgRdBW 382.88 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.29 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.52 # Data bus utilization in percentage system.physmem.avgRdQLen 0.13 # Average read queue length over time -system.physmem.avgWrQLen 13.20 # Average write queue length over time -system.physmem.readRowHits 15050623 # Number of row buffer hits during reads -system.physmem.writeRowHits 784578 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.70 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 96.49 # Row buffer hit rate for writes -system.physmem.avgGap 158618.43 # Average gap between requests +system.physmem.avgWrQLen 11.37 # Average write queue length over time +system.physmem.readRowHits 15049962 # Number of row buffer hits during reads +system.physmem.writeRowHits 784769 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.69 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 96.51 # Row buffer hit rate for writes +system.physmem.avgGap 158610.84 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -227,9 +227,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 15048943 # DTB read hits -system.cpu.checker.dtb.read_misses 7309 # DTB read misses -system.cpu.checker.dtb.write_hits 11294215 # DTB write hits +system.cpu.checker.dtb.read_hits 15048842 # DTB read hits +system.cpu.checker.dtb.read_misses 7308 # DTB read misses +system.cpu.checker.dtb.write_hits 11294147 # DTB write hits system.cpu.checker.dtb.write_misses 2189 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -240,13 +240,13 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 15056252 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11296404 # DTB write accesses +system.cpu.checker.dtb.read_accesses 15056150 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11296336 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26343158 # DTB hits -system.cpu.checker.dtb.misses 9498 # DTB misses -system.cpu.checker.dtb.accesses 26352656 # DTB accesses -system.cpu.checker.itb.inst_hits 61775988 # ITB inst hits +system.cpu.checker.dtb.hits 26342989 # DTB hits +system.cpu.checker.dtb.misses 9497 # DTB misses +system.cpu.checker.dtb.accesses 26352486 # DTB accesses +system.cpu.checker.itb.inst_hits 61775601 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -263,36 +263,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61780459 # ITB inst accesses -system.cpu.checker.itb.hits 61775988 # DTB hits +system.cpu.checker.itb.inst_accesses 61780072 # ITB inst accesses +system.cpu.checker.itb.hits 61775601 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61780459 # DTB accesses -system.cpu.checker.numCycles 78235930 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61780072 # DTB accesses +system.cpu.checker.numCycles 78235487 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51393832 # DTB read hits -system.cpu.dtb.read_misses 77273 # DTB read misses -system.cpu.dtb.write_hits 11807513 # DTB write hits -system.cpu.dtb.write_misses 17284 # DTB write misses +system.cpu.dtb.read_hits 51279526 # DTB read hits +system.cpu.dtb.read_misses 73667 # DTB read misses +system.cpu.dtb.write_hits 11753863 # DTB write hits +system.cpu.dtb.write_misses 17234 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 7715 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2923 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 497 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 7683 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2376 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 510 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1303 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51471105 # DTB read accesses -system.cpu.dtb.write_accesses 11824797 # DTB write accesses +system.cpu.dtb.perms_faults 1366 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51353193 # DTB read accesses +system.cpu.dtb.write_accesses 11771097 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63201345 # DTB hits -system.cpu.dtb.misses 94557 # DTB misses -system.cpu.dtb.accesses 63295902 # DTB accesses -system.cpu.itb.inst_hits 11866090 # ITB inst hits -system.cpu.itb.inst_misses 12256 # ITB inst misses +system.cpu.dtb.hits 63033389 # DTB hits +system.cpu.dtb.misses 90901 # DTB misses +system.cpu.dtb.accesses 63124290 # DTB accesses +system.cpu.itb.inst_hits 11603865 # ITB inst hits +system.cpu.itb.inst_misses 11359 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -301,538 +301,538 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 5202 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 5142 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3056 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2961 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11878346 # ITB inst accesses -system.cpu.itb.hits 11866090 # DTB hits -system.cpu.itb.misses 12256 # DTB misses -system.cpu.itb.accesses 11878346 # DTB accesses -system.cpu.numCycles 471617242 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11615224 # ITB inst accesses +system.cpu.itb.hits 11603865 # DTB hits +system.cpu.itb.misses 11359 # DTB misses +system.cpu.itb.accesses 11615224 # DTB accesses +system.cpu.numCycles 470951029 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14707934 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11701482 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 783806 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 9735591 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7867248 # Number of BTB hits +system.cpu.BPredUnit.lookups 14482147 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11548936 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 711590 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 9469344 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7720983 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1454059 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 82839 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 30177247 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 91949952 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14707934 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9321307 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20604105 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4981007 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 133002 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 96623906 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2605 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 100214 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 208761 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 353 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11862293 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 731589 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6461 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151283915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.758817 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.115765 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1413907 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 72813 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 29880342 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90834905 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14482147 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9134890 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20280806 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4750716 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 122594 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 96709258 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2560 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 94111 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 205295 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 281 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11600179 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 700998 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5704 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 150571175 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.752471 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.109183 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130696614 86.39% 86.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1382439 0.91% 87.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1755242 1.16% 88.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2339470 1.55% 90.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2142585 1.42% 91.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1134296 0.75% 92.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2618835 1.73% 93.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 784869 0.52% 94.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8429565 5.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130305873 86.54% 86.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1344979 0.89% 87.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1685836 1.12% 88.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2306234 1.53% 90.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2113026 1.40% 91.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1118544 0.74% 92.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2593877 1.72% 93.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 765442 0.51% 94.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8337364 5.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151283915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031186 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.194967 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32009474 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96255861 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18724959 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1031397 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3262224 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2019817 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174593 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 109260478 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 576218 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3262224 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33806773 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36827261 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 53335707 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17902220 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6149730 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 104066052 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21507 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1015259 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4119258 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 31916 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 107817309 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 475022232 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 474932056 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90176 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78731209 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 29086099 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 892462 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 797997 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12333143 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20063520 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13521808 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1973034 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2429271 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 96511584 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2058662 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 123961862 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 189585 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 20013916 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 50091772 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 514148 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151283915 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.819399 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.531663 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 150571175 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030751 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.192875 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31657449 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96342520 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18430846 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1034189 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3106171 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1969595 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172369 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107934392 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 571655 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3106171 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33426960 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36897380 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 53334301 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17638840 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6167523 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102924268 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21343 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1016075 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4132060 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 29183 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106686272 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 469883831 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 469792749 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 91082 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78730768 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27955503 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 879837 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 786100 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12323975 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19838005 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13393703 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1972033 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2410684 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95618817 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2046180 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 123387582 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 174864 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19151232 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 48036492 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501695 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 150571175 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.819463 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.532492 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 106904579 70.66% 70.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13863783 9.16% 79.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7099546 4.69% 84.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5863279 3.88% 88.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12474907 8.25% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2771705 1.83% 98.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1719952 1.14% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 458027 0.30% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128137 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 106455995 70.70% 70.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13758975 9.14% 79.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7009673 4.66% 84.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5842702 3.88% 88.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12442883 8.26% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2768710 1.84% 98.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1710517 1.14% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 450789 0.30% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 130931 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151283915 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 150571175 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 57031 0.64% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 3 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8373952 94.62% 95.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 418898 4.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 59954 0.68% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8366032 94.65% 95.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 413370 4.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58283800 47.02% 47.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95201 0.08% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52766411 42.57% 89.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12450621 10.04% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57926411 46.95% 47.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93267 0.08% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 17 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 17 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52616961 42.64% 89.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12385106 10.04% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 123961862 # Type of FU issued -system.cpu.iq.rate 0.262844 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8849884 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071392 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 408318037 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 118600535 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86285351 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23227 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12408 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10278 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132435732 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12348 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 629942 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 123387582 # Type of FU issued +system.cpu.iq.rate 0.261997 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8839360 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071639 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 406427994 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116832614 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85860436 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23103 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12565 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10308 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131851026 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12250 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624646 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4347483 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7997 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29897 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1723272 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4122070 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6381 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30063 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1595239 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34108218 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 695964 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107814 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 695818 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3262224 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27920683 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 435052 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 98794824 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 232558 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20063520 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13521808 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1467094 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 114012 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3652 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29897 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 410015 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 293518 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 703533 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121755337 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52081116 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2206525 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3106171 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27981842 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 438339 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97885744 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 205866 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19838005 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13393703 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1459318 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 116468 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3836 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30063 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 352690 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 272400 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 625090 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121269392 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51965419 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2118190 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 224578 # number of nop insts executed -system.cpu.iew.exec_refs 64400589 # number of memory reference insts executed -system.cpu.iew.exec_branches 11599904 # Number of branches executed -system.cpu.iew.exec_stores 12319473 # Number of stores executed -system.cpu.iew.exec_rate 0.258166 # Inst execution rate -system.cpu.iew.wb_sent 120729614 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86295629 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47354389 # num instructions producing a value -system.cpu.iew.wb_consumers 88420573 # num instructions consuming a value +system.cpu.iew.exec_nop 220747 # number of nop insts executed +system.cpu.iew.exec_refs 64230871 # number of memory reference insts executed +system.cpu.iew.exec_branches 11527542 # Number of branches executed +system.cpu.iew.exec_stores 12265452 # Number of stores executed +system.cpu.iew.exec_rate 0.257499 # Inst execution rate +system.cpu.iew.wb_sent 120289637 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85870744 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47162688 # num instructions producing a value +system.cpu.iew.wb_consumers 88075667 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182978 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535558 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182335 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535479 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 19868776 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1544514 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 612308 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 148104118 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.527303 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.512767 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18952599 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1544485 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 541833 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147547429 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.529290 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.517447 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120332893 81.25% 81.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13565443 9.16% 90.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3964002 2.68% 93.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2135941 1.44% 94.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1954116 1.32% 95.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 973664 0.66% 96.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1592335 1.08% 97.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 730104 0.49% 98.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2855620 1.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 119858518 81.23% 81.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13515143 9.16% 90.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3916529 2.65% 93.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2132463 1.45% 94.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1950760 1.32% 95.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 976387 0.66% 96.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1592516 1.08% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 731256 0.50% 98.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2873857 1.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 148104118 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60747617 # Number of instructions committed -system.cpu.commit.committedOps 78095752 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 147547429 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60747230 # Number of instructions committed +system.cpu.commit.committedOps 78095309 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27514573 # Number of memory references committed -system.cpu.commit.loads 15716037 # Number of loads committed -system.cpu.commit.membars 413105 # Number of memory barriers committed -system.cpu.commit.branches 10023091 # Number of branches committed +system.cpu.commit.refs 27514399 # Number of memory references committed +system.cpu.commit.loads 15715935 # Number of loads committed +system.cpu.commit.membars 413101 # Number of memory barriers committed +system.cpu.commit.branches 10023041 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69134185 # Number of committed integer instructions. -system.cpu.commit.function_calls 995980 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2855620 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69133795 # Number of committed integer instructions. +system.cpu.commit.function_calls 995976 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2873857 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 241297904 # The number of ROB reads -system.cpu.rob.rob_writes 199283253 # The number of ROB writes -system.cpu.timesIdled 1774711 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320333327 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575553300 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60597236 # Number of Instructions Simulated -system.cpu.committedOps 77945371 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60597236 # Number of Instructions Simulated -system.cpu.cpi 7.782818 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.782818 # CPI: Total CPI of All Threads -system.cpu.ipc 0.128488 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.128488 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 551506178 # number of integer regfile reads -system.cpu.int_regfile_writes 88407138 # number of integer regfile writes -system.cpu.fp_regfile_reads 8339 # number of floating regfile reads -system.cpu.fp_regfile_writes 2916 # number of floating regfile writes -system.cpu.misc_regfile_reads 124072221 # number of misc regfile reads -system.cpu.misc_regfile_writes 912903 # number of misc regfile writes -system.cpu.icache.replacements 990875 # number of replacements -system.cpu.icache.tagsinuse 510.405236 # Cycle average of tags in use -system.cpu.icache.total_refs 10787830 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 991387 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 10.881553 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6691567000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.405236 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996885 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996885 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10787830 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10787830 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10787830 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10787830 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10787830 # number of overall hits -system.cpu.icache.overall_hits::total 10787830 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1074333 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1074333 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1074333 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1074333 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1074333 # number of overall misses -system.cpu.icache.overall_misses::total 1074333 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14125562486 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14125562486 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14125562486 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14125562486 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14125562486 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14125562486 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11862163 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11862163 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11862163 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11862163 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11862163 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11862163 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.090568 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.090568 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.090568 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.090568 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.090568 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.090568 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13148.216136 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13148.216136 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13148.216136 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13148.216136 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13148.216136 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13148.216136 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4400 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 296 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 14.864865 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.rob.rob_reads 239806361 # The number of ROB reads +system.cpu.rob.rob_writes 197293644 # The number of ROB writes +system.cpu.timesIdled 1776983 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320379854 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575961583 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60596849 # Number of Instructions Simulated +system.cpu.committedOps 77944928 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60596849 # Number of Instructions Simulated +system.cpu.cpi 7.771873 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.771873 # CPI: Total CPI of All Threads +system.cpu.ipc 0.128669 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.128669 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 549353820 # number of integer regfile reads +system.cpu.int_regfile_writes 87979072 # number of integer regfile writes +system.cpu.fp_regfile_reads 8318 # number of floating regfile reads +system.cpu.fp_regfile_writes 2932 # number of floating regfile writes +system.cpu.misc_regfile_reads 122823412 # number of misc regfile reads +system.cpu.misc_regfile_writes 912865 # number of misc regfile writes +system.cpu.icache.replacements 980837 # number of replacements +system.cpu.icache.tagsinuse 511.007226 # Cycle average of tags in use +system.cpu.icache.total_refs 10539450 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 981349 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 10.739757 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6666804000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.007226 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.998061 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.998061 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 10539450 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10539450 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10539450 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10539450 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10539450 # number of overall hits +system.cpu.icache.overall_hits::total 10539450 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1060605 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1060605 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1060605 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1060605 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1060605 # number of overall misses +system.cpu.icache.overall_misses::total 1060605 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13961403491 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13961403491 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13961403491 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13961403491 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13961403491 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13961403491 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11600055 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11600055 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11600055 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11600055 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11600055 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11600055 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091431 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.091431 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.091431 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.091431 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.091431 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.091431 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13163.622169 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13163.622169 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13163.622169 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13163.622169 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13163.622169 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13163.622169 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5262 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 8 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 297 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 17.717172 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 8 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 82890 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 82890 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 82890 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 82890 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 82890 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 82890 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991443 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 991443 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 991443 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 991443 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 991443 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 991443 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11470045988 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11470045988 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11470045988 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11470045988 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11470045988 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11470045988 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7052500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7052500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7052500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 7052500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.083580 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.083580 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.083580 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.083580 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.083580 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.083580 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11569.042283 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11569.042283 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11569.042283 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11569.042283 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11569.042283 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11569.042283 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79214 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79214 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79214 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79214 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79214 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79214 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981391 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 981391 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 981391 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 981391 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 981391 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 981391 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11354795991 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11354795991 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11354795991 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11354795991 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11354795991 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11354795991 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6803000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6803000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6803000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 6803000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.084602 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.084602 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.084602 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.084602 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.084602 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.084602 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11570.104057 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11570.104057 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11570.104057 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11570.104057 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11570.104057 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11570.104057 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 645101 # number of replacements -system.cpu.dcache.tagsinuse 511.994184 # Cycle average of tags in use -system.cpu.dcache.total_refs 21772820 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 645613 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.724259 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 35202000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.994184 # Average occupied blocks per requestor +system.cpu.dcache.replacements 643459 # number of replacements +system.cpu.dcache.tagsinuse 511.994224 # Cycle average of tags in use +system.cpu.dcache.total_refs 21664123 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 643971 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.641457 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 35006000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.994224 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13909719 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13909719 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7289021 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7289021 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 285196 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 285196 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285739 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21198740 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21198740 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21198740 # number of overall hits -system.cpu.dcache.overall_hits::total 21198740 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 730115 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 730115 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2961662 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2961662 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13591 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13591 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 19 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 19 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3691777 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3691777 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3691777 # number of overall misses -system.cpu.dcache.overall_misses::total 3691777 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9540231500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9540231500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 104360444235 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 104360444235 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180814000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 180814000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 283000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 283000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 113900675735 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 113900675735 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 113900675735 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 113900675735 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14639834 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14639834 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10250683 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10250683 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 298787 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 298787 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285758 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285758 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24890517 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24890517 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24890517 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24890517 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049872 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.049872 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288923 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.288923 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045487 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045487 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000066 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000066 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.148321 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.148321 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.148321 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.148321 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13066.751813 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13066.751813 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35237.121669 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35237.121669 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13303.951144 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13303.951144 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 14894.736842 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 14894.736842 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30852.534087 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30852.534087 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30852.534087 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30852.534087 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29089 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 14501 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2531 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 252 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.493086 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 57.543651 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 13804735 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13804735 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7290056 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7290056 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 280491 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 280491 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285728 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285728 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21094791 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21094791 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21094791 # number of overall hits +system.cpu.dcache.overall_hits::total 21094791 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 731455 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 731455 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2960577 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2960577 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13626 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13626 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3692032 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3692032 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3692032 # number of overall misses +system.cpu.dcache.overall_misses::total 3692032 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9566755000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9566755000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 105515855226 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 105515855226 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181290500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 181290500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 192000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 192000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 115082610226 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 115082610226 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 115082610226 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 115082610226 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14536190 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14536190 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10250633 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10250633 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 294117 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 294117 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285740 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285740 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24786823 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24786823 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24786823 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24786823 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050320 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050320 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288819 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.288819 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046329 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046329 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000042 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000042 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.148951 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.148951 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.148951 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.148951 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13079.075268 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13079.075268 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35640.300937 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35640.300937 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13304.748275 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13304.748275 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31170.534336 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31170.534336 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 30622 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 13737 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2589 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 255 # number of cycles access was blocked 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LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3055404 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3055404 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3055404 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3055404 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387237 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 387237 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249136 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249136 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12226 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12226 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 19 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 19 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 636373 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 636373 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 636373 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 636373 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4781839500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4781839500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8147970920 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8147970920 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141479000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141479000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 245000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 245000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12929810420 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12929810420 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12929810420 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12929810420 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182356641500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182356641500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 28006523855 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 28006523855 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210363165355 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 210363165355 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026451 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026451 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024304 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024304 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.040919 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.040919 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000066 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000066 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025567 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025567 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025567 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025567 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12348.612090 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12348.612090 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32704.911855 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32704.911855 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11571.977752 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11571.977752 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12894.736842 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12894.736842 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20317.974553 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20317.974553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20317.974553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20317.974553 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607749 # number of writebacks +system.cpu.dcache.writebacks::total 607749 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345667 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 345667 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2711644 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2711644 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1415 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1415 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3057311 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3057311 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3057311 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3057311 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385788 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385788 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248933 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248933 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12211 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12211 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634721 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634721 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634721 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634721 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4768255000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4768255000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8227495919 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8227495919 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141520500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141520500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 168000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 168000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12995750919 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12995750919 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12995750919 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12995750919 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182357111500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182357111500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 27981839814 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 27981839814 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210338951314 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 210338951314 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026540 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026540 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024285 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024285 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041517 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041517 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000042 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000042 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025607 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025607 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12359.780501 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12359.780501 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33051.045538 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33051.045538 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11589.591352 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11589.591352 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -840,149 +840,149 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 64428 # number of replacements -system.cpu.l2cache.tagsinuse 51367.264734 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1930539 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129823 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 14.870547 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2488482557500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 36879.772922 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 44.022997 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000230 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 8192.461940 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6251.006645 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.562741 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000672 # Average percentage of cache occupancy +system.cpu.l2cache.replacements 64388 # number of replacements +system.cpu.l2cache.tagsinuse 51373.602635 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1911501 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 129780 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 14.728779 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2488431429000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 36915.014302 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 29.696477 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000348 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 8183.272105 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6245.619403 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.563278 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000453 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.125007 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.095383 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.783802 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 83028 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12007 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 977743 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 388649 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1461427 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 609133 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 609133 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 53 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 53 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 16 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 113031 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 113031 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 83028 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 12007 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 977743 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 501680 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1574458 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 83028 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 12007 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 977743 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 501680 # number of overall hits -system.cpu.l2cache.overall_hits::total 1574458 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 55 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12377 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10733 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 23166 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2933 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2933 # number of UpgradeReq misses +system.cpu.l2cache.occ_percent::cpu.inst 0.124867 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.095301 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.783899 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 79304 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10595 # number of ReadReq hits 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demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 967765 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 500060 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1557724 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 79304 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 10595 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 967765 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 500060 # number of overall hits +system.cpu.l2cache.overall_hits::total 1557724 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 43 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12372 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 10735 # number of ReadReq misses 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(read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 55 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12377 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143933 # number of overall misses -system.cpu.l2cache.overall_misses::total 156366 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3825000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 49000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 666073500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 589040998 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1258988498 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 478000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 478000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6695831998 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6695831998 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3825000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 49000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 666073500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7284872996 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7954820496 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3825000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 49000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 666073500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7284872996 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7954820496 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 83083 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12008 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 990120 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 399382 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1484593 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 609133 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 609133 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2986 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2986 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 19 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 19 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246231 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246231 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 83083 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 12008 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 990120 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 645613 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1730824 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 83083 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 12008 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 990120 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 645613 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1730824 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000662 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000083 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012501 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026874 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.015604 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.982251 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.982251 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.157895 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.157895 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.540955 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.540955 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000662 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000083 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012501 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.222940 # miss rate for demand accesses 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-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000083 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012487 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222846 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.090299 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000662 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000083 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012487 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222846 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.090299 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56820.181818 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 37000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41162.338968 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42221.082084 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41688.751819 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10005.258098 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10005.258098 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5125972608 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5125972608 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2368082 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 93002 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 503399135 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5578423976 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6084284195 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2368082 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 93002 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 503399135 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5578423976 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6084284195 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 4345155 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166963877530 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166968222685 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 18087556027 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 18087556027 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 4345155 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 185051433557 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 185055778712 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000542 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012610 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026828 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015722 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985478 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985478 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541227 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541227 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000542 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012610 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223381 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.091162 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000542 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012610 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223381 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.091162 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 55071.674419 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46501 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40728.085356 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42384.203091 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41521.299263 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10010.246744 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10010.246744 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37865.660886 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37865.660886 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56820.181818 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 37000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41162.338968 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38188.733166 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38430.519073 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56820.181818 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 37000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41162.338968 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38188.733166 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38430.519073 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38490.213011 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38490.213011 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 55071.674419 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46501 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40728.085356 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38779.181069 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38937.923632 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 55071.674419 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46501 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40728.085356 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38779.181069 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38937.923632 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1117,16 +1117,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1068163777856 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1068163777856 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1068163777856 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1068163777856 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1068305538529 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1068305538529 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1068305538529 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1068305538529 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88030 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88025 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index f00ea7875..966a7a822 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -12,9 +12,10 @@ children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview atags_addr=256 boot_loader=/projects/pd/randd/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 -clock=1 +clock=1000 dtb_filename= early_kernel_symbols=false +enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 @@ -23,7 +24,6 @@ load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing memories=system.physmem system.realview.nvmem -midr_regval=890224640 multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -39,7 +39,7 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge -clock=1 +clock=1000 delay=50000 ranges=268435456:520093695 1073741824:1610612735 req_size=16 @@ -69,7 +69,7 @@ read_only=true [system.cpu0] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb tracer +children=dcache dtb fuPool icache interrupts isa itb tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -117,6 +117,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu0.interrupts +isa=system.cpu0.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu0.itb @@ -168,10 +169,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -179,7 +180,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -198,7 +199,7 @@ walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -471,10 +472,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -482,7 +483,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -496,6 +497,23 @@ mem_side=system.toL2Bus.slave[0] [system.cpu0.interrupts] type=ArmInterrupts +[system.cpu0.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu0.itb] type=ArmTLB children=walker @@ -504,7 +522,7 @@ walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] @@ -514,7 +532,7 @@ type=ExeTracer [system.cpu1] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb tracer +children=dcache dtb fuPool icache interrupts isa itb tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -562,6 +580,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu1.interrupts +isa=system.cpu1.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu1.itb @@ -613,10 +632,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -624,7 +643,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -643,7 +662,7 @@ walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[7] @@ -916,10 +935,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -927,7 +946,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -941,6 +960,23 @@ mem_side=system.toL2Bus.slave[4] [system.cpu1.interrupts] type=ArmInterrupts +[system.cpu1.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu1.itb] type=ArmTLB children=walker @@ -949,7 +985,7 @@ walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[6] @@ -976,18 +1012,18 @@ type=BaseCache addr_ranges=0:268435455 assoc=8 block_size=64 -clock=1 +clock=1000 forward_snoops=false hash_delay=1 -hit_latency=50000 -is_top_level=false +hit_latency=50 +is_top_level=true max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=50000 +response_latency=50 size=1024 subblock_size=0 system=system @@ -1003,22 +1039,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=10000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=92 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=10000 +response_latency=20 size=4194304 subblock_size=0 system=system -tgts_per_mshr=16 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -1039,7 +1075,7 @@ slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=0 pio_latency=100000 @@ -1055,15 +1091,28 @@ warn_access=warn pio=system.membus.default [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=true in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[2] @@ -1078,7 +1127,7 @@ system=system [system.realview.a9scu] type=A9SCU -clock=1 +clock=1000 pio_addr=520093696 pio_latency=100000 system=system @@ -1087,7 +1136,7 @@ pio=system.membus.master[5] [system.realview.aaci_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -1134,7 +1183,7 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 -clock=1 +clock=1000 config_latency=20000 ctrl_offset=2 disks=system.cf0 @@ -1165,7 +1214,7 @@ pio=system.iobus.master[4] [system.realview.dmac_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -1174,7 +1223,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake -clock=1 +clock=1000 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -1191,7 +1240,7 @@ pio=system.iobus.master[24] [system.realview.gic] type=Gic -clock=1 +clock=1000 cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 @@ -1205,7 +1254,7 @@ pio=system.membus.master[3] [system.realview.gpio0_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -1215,7 +1264,7 @@ pio=system.iobus.master[16] [system.realview.gpio1_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -1225,7 +1274,7 @@ pio=system.iobus.master[17] [system.realview.gpio2_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -1235,7 +1284,7 @@ pio=system.iobus.master[18] [system.realview.kmi0] type=Pl050 amba_id=1314896 -clock=1 +clock=1000 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -1249,7 +1298,7 @@ pio=system.iobus.master[5] [system.realview.kmi1] type=Pl050 amba_id=1314896 -clock=1 +clock=1000 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -1262,7 +1311,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -1291,7 +1340,7 @@ pio=system.membus.master[6] [system.realview.mmc_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -1301,7 +1350,7 @@ pio=system.iobus.master[22] [system.realview.nvmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 @@ -1313,7 +1362,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl -clock=1 +clock=1000 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -1325,7 +1374,7 @@ pio=system.iobus.master[1] [system.realview.rtc] type=PL031 amba_id=3412017 -clock=1 +clock=1000 gic=system.realview.gic int_delay=100000 int_num=42 @@ -1338,7 +1387,7 @@ pio=system.iobus.master[23] [system.realview.sci_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -1348,7 +1397,7 @@ pio=system.iobus.master[20] [system.realview.smc_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -1358,7 +1407,7 @@ pio=system.iobus.master[13] [system.realview.sp810_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -1368,7 +1417,7 @@ pio=system.iobus.master[14] [system.realview.ssp_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -1378,7 +1427,7 @@ pio=system.iobus.master[19] [system.realview.timer0] type=Sp804 amba_id=1316868 -clock=1 +clock=1000 clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -1392,7 +1441,7 @@ pio=system.iobus.master[2] [system.realview.timer1] type=Sp804 amba_id=1316868 -clock=1 +clock=1000 clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -1405,7 +1454,7 @@ pio=system.iobus.master[3] [system.realview.uart] type=Pl011 -clock=1 +clock=1000 end_on_eot=false gic=system.realview.gic int_delay=100000 @@ -1420,7 +1469,7 @@ pio=system.iobus.master[0] [system.realview.uart1_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -1430,7 +1479,7 @@ pio=system.iobus.master[10] [system.realview.uart2_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -1440,7 +1489,7 @@ pio=system.iobus.master[11] [system.realview.uart3_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -1450,7 +1499,7 @@ pio=system.iobus.master[12] [system.realview.watchdog_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -1467,7 +1516,7 @@ port=3456 [system.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false width=8 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr index 04178bb32..e8e271d58 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr @@ -12,7 +12,6 @@ warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: instruction 'mcr bpiallis' unimplemented warn: LCD dual screen mode not supported -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr icialluis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index 4c598b20c..ac731cab9 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 12:18:35 +gem5 compiled Oct 30 2012 11:20:14 +gem5 started Oct 30 2012 21:14:52 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2616878893500 because m5_exit instruction encountered +Exiting @ tick 2593146078000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 30d23f9d7..2681ab283 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,131 +1,135 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.603317 # Number of seconds simulated -sim_ticks 2603316759000 # Number of ticks simulated -final_tick 2603316759000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.593146 # Number of seconds simulated +sim_ticks 2593146078000 # Number of ticks simulated +final_tick 2593146078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 64170 # Simulator instruction rate (inst/s) -host_op_rate 82590 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2648964509 # Simulator tick rate (ticks/s) -host_mem_usage 407980 # Number of bytes of host memory used -host_seconds 982.77 # Real time elapsed on the host -sim_insts 63063787 # Number of instructions simulated -sim_ops 81167171 # Number of ops (including micro ops) simulated +host_inst_rate 66425 # Simulator instruction rate (inst/s) +host_op_rate 85503 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2731005239 # Simulator tick rate (ticks/s) +host_mem_usage 409388 # Number of bytes of host memory used +host_seconds 949.52 # Real time elapsed on the host +sim_insts 63072130 # Number of instructions simulated +sim_ops 81187111 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 896 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 396352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4375860 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 425408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5260720 # Number of bytes read from this memory -system.physmem.bytes_read::total 131570852 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 396352 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 425408 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 821760 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4284288 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 395328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4376500 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 426752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5261232 # Number of bytes read from this memory +system.physmem.bytes_read::total 131572388 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 395328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 426752 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 822080 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4282048 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7313424 # Number of bytes written to this memory +system.physmem.bytes_written::total 7311184 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 14 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6193 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68445 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6647 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82225 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15302357 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66942 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6177 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68455 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6668 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82233 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15302381 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66907 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 824226 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46521626 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 320 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 824191 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46704090 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 346 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 152249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1680879 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 393 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 163410 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2020776 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50539702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 152249 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 163410 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315659 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1645704 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6530 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1157038 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2809272 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1645704 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46521626 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 320 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 152451 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1687718 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 370 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 164569 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2028899 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50738518 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 152451 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 164569 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317020 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1651295 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6556 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1161576 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2819426 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1651295 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46704090 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 346 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 152249 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1687409 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 393 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 163410 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3177814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53348973 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15302357 # Total number of read requests seen -system.physmem.writeReqs 824226 # Total number of write requests seen -system.physmem.cpureqs 284853 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 979350848 # Total number of bytes read from memory -system.physmem.bytesWritten 52750464 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131570852 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7313424 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 375 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 14171 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 956419 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 956744 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 956349 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 956561 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 956521 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 956118 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 955968 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 956063 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 957003 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 956395 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 956361 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 956664 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956312 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 956494 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 956128 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955882 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50798 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 51080 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50753 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50993 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51913 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51591 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51454 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51530 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 52149 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51821 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51633 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51817 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51736 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51833 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51645 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51480 # Track writes on a per bank basis +system.physmem.bw_total::cpu0.inst 152451 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1694274 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 370 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 164569 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3190475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53557944 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15302381 # Total number of read requests seen +system.physmem.writeReqs 824191 # Total number of write requests seen +system.physmem.cpureqs 284713 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 979352384 # Total number of bytes read from memory +system.physmem.bytesWritten 52748224 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 131572388 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7311184 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 335 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 14131 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 956528 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 956655 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 956404 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 956499 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 956473 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 956086 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 955879 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 956080 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 957009 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 956354 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 956393 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 956606 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 956350 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 956542 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 956247 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 955941 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50875 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 51001 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50801 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50933 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51869 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51569 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51383 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51546 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 52151 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51788 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51664 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51769 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51735 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51864 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51697 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51546 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1152088 # Number of times wr buffer was full causing retry -system.physmem.totGap 2603315545500 # Total gap between requests +system.physmem.numWrRetry 1150487 # Number of times wr buffer was full causing retry +system.physmem.totGap 2593144762500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 105 # Categorize read packet sizes system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 163436 # Categorize read packet sizes +system.physmem.readPktSize::6 163460 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 1909372 # categorize write packet sizes +system.physmem.writePktSize::2 1907771 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 66942 # categorize write packet sizes +system.physmem.writePktSize::6 66907 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -134,29 +138,29 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 14171 # categorize neither packet sizes +system.physmem.neitherpktsize::6 14131 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 15151636 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 94017 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8640 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3524 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2842 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2641 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2030 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1352 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 6499 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 9632 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 13082 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 603 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 15151641 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 94331 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8809 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3486 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2848 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2557 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2313 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1993 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1407 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 6472 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 9621 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 13063 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 592 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 97 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 54 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 23 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -170,60 +174,60 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3540 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3651 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4620 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 31828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 31605 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 31410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 31216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4027 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32002 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 31808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 31587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 31428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 31249 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 48061683883 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 322412499883 # Sum of mem lat for all requests -system.physmem.totBusLat 61207928000 # Total cycles spent in databus access -system.physmem.totBankLat 213142888000 # Total cycles spent in bank access -system.physmem.avgQLat 3140.88 # Average queueing delay per request -system.physmem.avgBankLat 13929.10 # Average bank access latency per request +system.physmem.totQLat 47868619345 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 322210199345 # Sum of mem lat for all requests +system.physmem.totBusLat 61208184000 # Total cycles spent in databus access +system.physmem.totBankLat 213133396000 # Total cycles spent in bank access +system.physmem.avgQLat 3128.25 # Average queueing delay per request +system.physmem.avgBankLat 13928.42 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 21069.98 # Average memory access latency -system.physmem.avgRdBW 376.19 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.26 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 50.54 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.81 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 21056.67 # Average memory access latency +system.physmem.avgRdBW 377.67 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 20.34 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 50.74 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 2.82 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.48 # Data bus utilization in percentage +system.physmem.busUtil 2.49 # Data bus utilization in percentage system.physmem.avgRdQLen 0.12 # Average read queue length over time -system.physmem.avgWrQLen 11.94 # Average write queue length over time -system.physmem.readRowHits 15253098 # Number of row buffer hits during reads -system.physmem.writeRowHits 789391 # Number of row buffer hits during writes +system.physmem.avgWrQLen 10.88 # Average write queue length over time +system.physmem.readRowHits 15253448 # Number of row buffer hits during reads +system.physmem.writeRowHits 789566 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 95.77 # Row buffer hit rate for writes -system.physmem.avgGap 161430.08 # Average gap between requests +system.physmem.writeRowHitRate 95.80 # Row buffer hit rate for writes +system.physmem.avgGap 160799.50 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -235,244 +239,258 @@ system.realview.nvmem.num_reads::cpu1.inst 6 # system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.inst 148 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 172 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 173 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu1.inst 148 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 172 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 173 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 148 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 73153 # number of replacements -system.l2c.tagsinuse 53083.361452 # Cycle average of tags in use -system.l2c.total_refs 1922203 # Total number of references to valid blocks. -system.l2c.sampled_refs 138333 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.895477 # Average number of references to valid blocks. +system.realview.nvmem.bw_total::total 173 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 73184 # number of replacements +system.l2c.tagsinuse 53096.266008 # Cycle average of tags in use +system.l2c.total_refs 1906265 # Total number of references to valid blocks. +system.l2c.sampled_refs 138351 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.778469 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 37742.975736 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 6.244346 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.876765 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4208.985983 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2954.129199 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 11.276001 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 4048.165548 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 4110.707874 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.575912 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000095 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000013 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.064224 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.045076 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000172 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.061770 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.062724 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.809988 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 35828 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 5516 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 398518 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 165446 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 53941 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6316 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 614017 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 202060 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1481642 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 584379 # number of Writeback hits -system.l2c.Writeback_hits::total 584379 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1214 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 738 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1952 # number of UpgradeReq hits +system.l2c.occ_blocks::writebacks 37733.790025 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 7.219153 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.000341 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4206.047810 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2960.317078 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 11.178862 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.966447 # Average occupied blocks per requestor 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average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10030.659355 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10033.649916 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10031.960641 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37836.216693 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 43056.611686 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40701.908583 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 59194.153846 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40279.149347 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 41581.881859 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56635.066667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 109502 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 43407.603774 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45433.619852 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 42739.057192 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10073.183673 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10162.641916 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10112.237411 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10042.377749 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10047.136752 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10044.427835 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37301.377525 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42974.593287 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40412.054677 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71287.500000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39746.945077 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38193.707585 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 55314.250000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42421.292790 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 43266.813890 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40973.515949 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 59194.153846 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40279.149347 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37687.956262 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56635.066667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 109502 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 43407.603774 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 43161.341742 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40767.502356 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71287.500000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46501 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39746.945077 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38193.707585 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 55314.250000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42421.292790 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 43266.813890 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40973.515949 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40279.149347 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37687.956262 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56635.066667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 109502 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 43407.603774 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 43161.341742 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40767.502356 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -665,27 +695,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9063545 # DTB read hits -system.cpu0.dtb.read_misses 36220 # DTB read misses -system.cpu0.dtb.write_hits 5280653 # DTB write hits -system.cpu0.dtb.write_misses 6480 # DTB write misses +system.cpu0.dtb.read_hits 9014303 # DTB read hits +system.cpu0.dtb.read_misses 34965 # DTB read misses +system.cpu0.dtb.write_hits 5253714 # DTB write hits +system.cpu0.dtb.write_misses 6399 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2158 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1224 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 336 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2155 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1094 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 321 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 569 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9099765 # DTB read accesses -system.cpu0.dtb.write_accesses 5287133 # DTB write accesses +system.cpu0.dtb.perms_faults 573 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 9049268 # DTB read accesses +system.cpu0.dtb.write_accesses 5260113 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14344198 # DTB hits -system.cpu0.dtb.misses 42700 # DTB misses -system.cpu0.dtb.accesses 14386898 # DTB accesses -system.cpu0.itb.inst_hits 4425189 # ITB inst hits -system.cpu0.itb.inst_misses 5562 # ITB inst misses +system.cpu0.dtb.hits 14268017 # DTB hits +system.cpu0.dtb.misses 41364 # DTB misses +system.cpu0.dtb.accesses 14309381 # DTB accesses +system.cpu0.itb.inst_hits 4294311 # ITB inst hits +system.cpu0.itb.inst_misses 5261 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -694,542 +724,538 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1395 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1385 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1518 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1364 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4430751 # ITB inst accesses -system.cpu0.itb.hits 4425189 # DTB hits -system.cpu0.itb.misses 5562 # DTB misses -system.cpu0.itb.accesses 4430751 # DTB accesses -system.cpu0.numCycles 69436793 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4299572 # ITB inst accesses +system.cpu0.itb.hits 4294311 # DTB hits +system.cpu0.itb.misses 5261 # DTB misses +system.cpu0.itb.accesses 4299572 # DTB accesses +system.cpu0.numCycles 69013505 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 6232893 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 4743306 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 327822 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 3788300 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 3047807 # Number of BTB hits +system.cpu0.BPredUnit.lookups 6123831 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 4675790 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 298271 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 3798227 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 2989296 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 701189 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 31986 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 12165372 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 33223009 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6232893 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3748996 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7801748 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1579515 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 70495 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 21773574 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5807 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 55458 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 92257 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 165 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4423471 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 173760 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2652 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 43098147 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.994806 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.374305 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 685728 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 28375 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 11998527 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32710943 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6123831 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3675024 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7667644 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1480146 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 66638 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 21758305 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5862 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 53793 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 90248 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 221 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4292744 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 155269 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2401 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 42704543 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.988603 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.369673 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 35304381 81.92% 81.92% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 609582 1.41% 83.33% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 823952 1.91% 85.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 710643 1.65% 86.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 795409 1.85% 88.74% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 570879 1.32% 90.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 720960 1.67% 91.73% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 375620 0.87% 92.61% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3186721 7.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 35044149 82.06% 82.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 606065 1.42% 83.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 793528 1.86% 85.34% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 689319 1.61% 86.95% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 781424 1.83% 88.78% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 567584 1.33% 90.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 711320 1.67% 91.78% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 364019 0.85% 92.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3147135 7.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 43098147 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.089764 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.478464 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12694368 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 21733151 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 7021973 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 580158 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1068497 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 974425 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 66014 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 41440720 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 216131 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1068497 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 13283568 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5811502 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 13763022 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6961604 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2209954 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 40230567 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 2204 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 441496 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1232571 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 70 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 40628697 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 181762207 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 181727693 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34514 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 31673882 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8954814 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 460934 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 417253 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5454618 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7893877 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5899231 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1129288 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1250491 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 37987189 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 942287 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 38211306 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 88088 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6766776 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 14417426 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 253739 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 43098147 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.886611 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.498890 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 42704543 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.088734 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.473979 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12497333 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 21726841 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6896095 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 584636 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 999638 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 951812 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64726 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40836330 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 213865 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 999638 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 13071648 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5812993 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13759259 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6855374 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2205631 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 39711904 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 2173 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 427558 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1242268 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 68 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 40116309 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 179435830 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 179401258 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34572 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31681024 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8435284 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 457771 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 414521 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5443309 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7819363 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5820332 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1146243 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1242216 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 37575405 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 946067 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37951575 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 82274 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6366228 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13456450 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 257591 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 42704543 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.888701 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.500077 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 27429044 63.64% 63.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6069688 14.08% 77.73% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3249267 7.54% 85.27% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2519397 5.85% 91.11% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2120550 4.92% 96.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 959758 2.23% 98.26% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 504062 1.17% 99.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 191517 0.44% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 54864 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 27159670 63.60% 63.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6000291 14.05% 77.65% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3232720 7.57% 85.22% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2489147 5.83% 91.05% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2132528 4.99% 96.04% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 950123 2.22% 98.27% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 497063 1.16% 99.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 188710 0.44% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 54291 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 43098147 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 42704543 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 25519 2.38% 2.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 464 0.04% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 839951 78.37% 80.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 205830 19.20% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 24659 2.31% 2.31% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 467 0.04% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 838061 78.41% 80.76% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 205631 19.24% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52084 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22953142 60.07% 60.21% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 49969 0.13% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 683 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.34% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9542960 24.97% 85.31% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5612439 14.69% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52344 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22793341 60.06% 60.20% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 48224 0.13% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9480747 24.98% 85.31% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5576214 14.69% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 38211306 # Type of FU issued -system.cpu0.iq.rate 0.550303 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1071764 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028048 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 120714498 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 45704259 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 35275992 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8506 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4731 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3909 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 39226540 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4446 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 323503 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37951575 # Type of FU issued +system.cpu0.iq.rate 0.549915 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1068818 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028163 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 119791525 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44895833 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 35071497 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8304 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4710 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3884 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38963714 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4335 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 318123 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1474665 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3677 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13402 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 626328 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1396327 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2506 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13403 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 544501 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2149439 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5367 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2149359 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5385 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1068497 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4177933 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 101495 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 39049116 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 95858 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7893877 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5899231 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 616112 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 40709 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3360 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13402 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 173604 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 128122 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 301726 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 37794024 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9381421 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 417282 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 999638 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4184428 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 103741 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 38639126 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 85944 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7819363 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5820332 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 614711 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 41414 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3290 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13403 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 151339 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 119425 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 270764 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 37563861 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9331167 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 387714 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 119640 # number of nop insts executed -system.cpu0.iew.exec_refs 14935051 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4997979 # Number of branches executed -system.cpu0.iew.exec_stores 5553630 # Number of stores executed -system.cpu0.iew.exec_rate 0.544294 # Inst execution rate -system.cpu0.iew.wb_sent 37576425 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 35279901 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18742857 # num instructions producing a value -system.cpu0.iew.wb_consumers 36023721 # num instructions consuming a value +system.cpu0.iew.exec_nop 117654 # number of nop insts executed +system.cpu0.iew.exec_refs 14857557 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4958494 # Number of branches executed +system.cpu0.iew.exec_stores 5526390 # Number of stores executed +system.cpu0.iew.exec_rate 0.544297 # Inst execution rate +system.cpu0.iew.wb_sent 37365472 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 35075381 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18655901 # num instructions producing a value +system.cpu0.iew.wb_consumers 35819655 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.508087 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.520292 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.508239 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.520829 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6624150 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 688548 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 263048 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 42066039 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.760422 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.715065 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6205381 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 688476 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 234604 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 41741265 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.766601 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.727877 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 29990291 71.29% 71.29% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5984334 14.23% 85.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1979513 4.71% 90.23% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1007903 2.40% 92.62% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 802639 1.91% 94.53% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 528288 1.26% 95.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 397543 0.95% 96.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 220589 0.52% 97.25% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1154939 2.75% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 29720457 71.20% 71.20% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5963123 14.29% 85.49% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1948324 4.67% 90.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1002440 2.40% 92.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 789371 1.89% 94.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 520489 1.25% 95.69% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 393953 0.94% 96.64% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 216687 0.52% 97.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1186421 2.84% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 42066039 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 24262669 # Number of instructions committed -system.cpu0.commit.committedOps 31987958 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 41741265 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 24264310 # Number of instructions committed +system.cpu0.commit.committedOps 31998915 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11692115 # Number of memory references committed -system.cpu0.commit.loads 6419212 # Number of loads committed -system.cpu0.commit.membars 234468 # Number of memory barriers committed -system.cpu0.commit.branches 4346825 # Number of branches committed +system.cpu0.commit.refs 11698867 # Number of memory references committed +system.cpu0.commit.loads 6423036 # Number of loads committed +system.cpu0.commit.membars 234373 # Number of memory barriers committed +system.cpu0.commit.branches 4346960 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 28256367 # Number of committed integer instructions. -system.cpu0.commit.function_calls 500017 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1154939 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 28266871 # Number of committed integer instructions. +system.cpu0.commit.function_calls 499893 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1186421 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 78638973 # The number of ROB reads -system.cpu0.rob.rob_writes 78294863 # The number of ROB writes -system.cpu0.timesIdled 365151 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26338646 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5137152930 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 24181927 # Number of Instructions Simulated -system.cpu0.committedOps 31907216 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 24181927 # Number of Instructions Simulated -system.cpu0.cpi 2.871433 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.871433 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.348258 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.348258 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 176324047 # number of integer regfile reads -system.cpu0.int_regfile_writes 35061690 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3352 # number of floating regfile reads -system.cpu0.fp_regfile_writes 912 # number of floating regfile writes -system.cpu0.misc_regfile_reads 47470625 # number of misc regfile reads -system.cpu0.misc_regfile_writes 527597 # number of misc regfile writes -system.cpu0.icache.replacements 404775 # number of replacements -system.cpu0.icache.tagsinuse 511.602715 # Cycle average of tags in use -system.cpu0.icache.total_refs 3985323 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 405287 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.833335 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6841145000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.602715 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.999224 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999224 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3985323 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3985323 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3985323 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3985323 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3985323 # number of overall hits -system.cpu0.icache.overall_hits::total 3985323 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 438012 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 438012 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 438012 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 438012 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 438012 # number of overall misses -system.cpu0.icache.overall_misses::total 438012 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5943655997 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5943655997 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5943655997 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5943655997 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5943655997 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5943655997 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4423335 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4423335 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4423335 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4423335 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4423335 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4423335 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099023 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.099023 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099023 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.099023 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099023 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.099023 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13569.619090 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13569.619090 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13569.619090 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13569.619090 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13569.619090 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13569.619090 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2262 # number of cycles access was blocked +system.cpu0.rob.rob_reads 77875275 # The number of ROB reads +system.cpu0.rob.rob_writes 77410136 # The number of ROB writes +system.cpu0.timesIdled 364830 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26308962 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5117234895 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 24183568 # Number of Instructions Simulated +system.cpu0.committedOps 31918173 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 24183568 # Number of Instructions Simulated +system.cpu0.cpi 2.853735 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.853735 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.350418 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.350418 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 175323075 # number of integer regfile reads +system.cpu0.int_regfile_writes 34853003 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3246 # number of floating regfile reads +system.cpu0.fp_regfile_writes 906 # number of floating regfile writes +system.cpu0.misc_regfile_reads 46878729 # number of misc regfile reads +system.cpu0.misc_regfile_writes 527371 # number of misc regfile writes +system.cpu0.icache.replacements 399233 # number of replacements +system.cpu0.icache.tagsinuse 511.592262 # Cycle average of tags in use +system.cpu0.icache.total_refs 3861943 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 399745 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.661016 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 6802423000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 511.592262 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.999204 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999204 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3861943 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3861943 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3861943 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3861943 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3861943 # number of overall hits +system.cpu0.icache.overall_hits::total 3861943 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 430668 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 430668 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 430668 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 430668 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 430668 # number of overall misses +system.cpu0.icache.overall_misses::total 430668 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5857521993 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5857521993 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5857521993 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5857521993 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5857521993 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5857521993 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4292611 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4292611 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4292611 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4292611 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4292611 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4292611 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100328 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100328 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100328 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100328 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100328 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100328 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13601.015151 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13601.015151 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13601.015151 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13601.015151 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13601.015151 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13601.015151 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2687 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 131 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 157 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.267176 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.114650 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 32710 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 32710 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 32710 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 32710 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 32710 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 32710 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 405302 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 405302 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 405302 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 405302 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 405302 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 405302 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4852452498 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4852452498 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4852452498 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4852452498 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4852452498 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4852452498 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7399000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7399000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7399000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 7399000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.091628 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.091628 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.091628 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.091628 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.091628 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.091628 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11972.436598 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11972.436598 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11972.436598 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11972.436598 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11972.436598 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11972.436598 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30901 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 30901 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 30901 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 30901 # number of demand (read+write) MSHR hits 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demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4790784994 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4790784994 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4790784994 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7139500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7139500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7139500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 7139500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093129 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093129 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093129 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093129 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093129 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093129 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11983.943132 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11983.943132 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11983.943132 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11983.943132 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11983.943132 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11983.943132 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 274922 # number of replacements -system.cpu0.dcache.tagsinuse 477.004191 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9558639 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 275434 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 34.703918 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 36505000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 477.004191 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.931649 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.931649 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5930824 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5930824 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3236437 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3236437 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174250 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 174250 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171562 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 171562 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9167261 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9167261 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9167261 # number of overall hits -system.cpu0.dcache.overall_hits::total 9167261 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 390293 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 390293 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1580955 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1580955 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8903 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8903 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7756 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7756 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1971248 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1971248 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1971248 # number of overall misses -system.cpu0.dcache.overall_misses::total 1971248 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5368045500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5368045500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 61391771868 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 61391771868 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88103500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 88103500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 50615000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 50615000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 66759817368 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 66759817368 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 66759817368 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 66759817368 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6321117 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6321117 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4817392 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4817392 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183153 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 183153 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179318 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 179318 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11138509 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11138509 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11138509 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11138509 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.061744 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.061744 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.328177 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.328177 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048610 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048610 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043253 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043253 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.176976 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.176976 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.176976 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.176976 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13753.886183 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13753.886183 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38832.080526 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38832.080526 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9895.933955 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9895.933955 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6525.915420 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6525.915420 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33866.777477 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33866.777477 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33866.777477 # average overall miss latency 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34.548160 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 36452000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 481.181813 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.939808 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.939808 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5887183 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5887183 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3238358 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3238358 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 173666 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 173666 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171542 # number of StoreCondReq hits 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cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 50475500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 50475500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 66258676847 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 66258676847 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 66258676847 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 66258676847 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6277949 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6277949 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4820379 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4820379 # number of WriteReq accesses(hits+misses) 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13760.831290 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13760.831290 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38483.314600 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38483.314600 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9943.924707 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9943.924707 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6518.855741 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6518.855741 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33586.330834 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33586.330834 # average overall miss latency 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-system.cpu0.dcache.writebacks::total 255626 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 201523 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 201523 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1449784 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1449784 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 468 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 468 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1651307 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1651307 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1651307 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1651307 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188770 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188770 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131171 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 131171 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8435 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8435 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7755 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7755 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 319941 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 319941 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 319941 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 319941 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2338858500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2338858500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4087753491 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4087753491 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66408500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66408500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 35107000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 35107000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6426611991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6426611991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6426611991 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6426611991 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13431962000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13431962000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1199718891 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1199718891 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14631680891 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14631680891 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029863 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029863 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027229 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027229 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046054 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046054 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043247 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043247 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028724 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028724 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028724 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028724 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12389.990465 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12389.990465 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31163.545990 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31163.545990 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7872.969769 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7872.969769 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4527.014829 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4527.014829 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20086.865988 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20086.865988 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20086.865988 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20086.865988 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 255577 # number of writebacks +system.cpu0.dcache.writebacks::total 255577 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202032 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 202032 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1450989 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1450989 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 498 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 498 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1653021 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1653021 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1653021 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1653021 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188734 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188734 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131032 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 131032 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8374 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8374 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7739 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7739 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 319766 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 319766 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 319766 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 319766 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2333622500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2333622500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4054127491 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4054127491 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66245000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66245000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34997500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34997500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6387749991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6387749991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6387749991 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6387749991 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13431600500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13431600500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1199905877 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1199905877 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14631506377 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14631506377 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030063 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030063 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027183 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027183 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045875 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045875 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043166 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043166 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028812 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028812 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028812 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028812 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12364.611040 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12364.611040 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30939.980241 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30939.980241 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7910.795319 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7910.795319 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4522.225094 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4522.225094 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19976.326411 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19976.326411 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19976.326411 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19976.326411 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1239,27 +1265,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 43093620 # DTB read hits -system.cpu1.dtb.read_misses 44212 # DTB read misses -system.cpu1.dtb.write_hits 7019560 # DTB write hits -system.cpu1.dtb.write_misses 11765 # DTB write misses +system.cpu1.dtb.read_hits 43030291 # DTB read hits +system.cpu1.dtb.read_misses 42638 # DTB read misses +system.cpu1.dtb.write_hits 6991861 # DTB write hits +system.cpu1.dtb.write_misses 11867 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2367 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 3591 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 309 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2362 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2846 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 322 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 679 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 43137832 # DTB read accesses -system.cpu1.dtb.write_accesses 7031325 # DTB write accesses +system.cpu1.dtb.perms_faults 690 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 43072929 # DTB read accesses +system.cpu1.dtb.write_accesses 7003728 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 50113180 # DTB hits -system.cpu1.dtb.misses 55977 # DTB misses -system.cpu1.dtb.accesses 50169157 # DTB accesses -system.cpu1.itb.inst_hits 7945263 # ITB inst hits -system.cpu1.itb.inst_misses 6054 # ITB inst misses +system.cpu1.dtb.hits 50022152 # DTB hits +system.cpu1.dtb.misses 54505 # DTB misses +system.cpu1.dtb.accesses 50076657 # DTB accesses +system.cpu1.itb.inst_hits 7786412 # ITB inst hits +system.cpu1.itb.inst_misses 5635 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1268,538 +1294,538 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1580 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1587 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1618 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1520 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7951317 # ITB inst accesses -system.cpu1.itb.hits 7945263 # DTB hits -system.cpu1.itb.misses 6054 # DTB misses -system.cpu1.itb.accesses 7951317 # DTB accesses -system.cpu1.numCycles 409430571 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7792047 # ITB inst accesses +system.cpu1.itb.hits 7786412 # DTB hits +system.cpu1.itb.misses 5635 # DTB misses +system.cpu1.itb.accesses 7792047 # DTB accesses +system.cpu1.numCycles 409024249 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 9152257 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 7432560 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 466867 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 6195424 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 5148293 # Number of BTB hits +system.cpu1.BPredUnit.lookups 9020667 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 7346445 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 421687 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 5902094 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 5066087 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 835215 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 50625 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 19713770 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 62254744 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9152257 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 5983508 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 13632356 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3573599 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 74747 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 78115877 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5836 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 48120 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 142516 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 165 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 7943235 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 563949 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3459 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 114180028 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.668662 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.999663 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 810235 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 44717 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 19548819 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 61628162 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9020667 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 5876322 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 13445282 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3432135 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 71958 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 78159434 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5756 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 48212 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 140837 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 164 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 7784486 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 545452 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3066 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 113770833 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.663645 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.994153 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 100555609 88.07% 88.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 838988 0.73% 88.80% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1011000 0.89% 89.69% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1744900 1.53% 91.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1443541 1.26% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 605100 0.53% 93.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1974563 1.73% 94.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 445551 0.39% 95.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5560776 4.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 100333102 88.19% 88.19% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 820750 0.72% 88.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 967014 0.85% 89.76% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1722421 1.51% 91.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1420935 1.25% 92.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 598048 0.53% 93.05% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1962596 1.73% 94.77% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 435893 0.38% 95.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5510074 4.84% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 114180028 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022354 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.152052 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 21120325 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 77740288 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12430171 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 543608 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2345636 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1176073 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 102892 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 72257305 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 341492 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2345636 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 22356190 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 32102348 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 41268894 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11643477 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4463483 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 68190005 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 19565 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 695237 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3171764 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 33722 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 71496605 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 312933263 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 312874076 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59187 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 50205657 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 21290948 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 480351 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 419670 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8129610 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 13049293 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8227563 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1078580 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1518105 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 62664777 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1204533 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 89464326 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 109059 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 14241211 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 38124625 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 284346 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 114180028 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.783537 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.520062 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 113770833 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022054 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.150671 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 20932611 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 77783544 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12260401 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 543319 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2250958 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1146967 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 100968 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 71503765 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 336196 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2250958 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 22152530 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 32126143 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 41276446 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11489660 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4475096 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 67542275 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 19496 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 697256 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3178756 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 32684 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 70870880 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 310023883 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 309964693 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59190 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 50213421 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 20657459 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 473589 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 413624 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8131877 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 12919526 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8160199 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1076421 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1515550 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 62172086 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1201080 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 89161848 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 100982 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 13762748 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 36926540 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 280453 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 113770833 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.783697 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.520241 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 83489742 73.12% 73.12% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8670086 7.59% 80.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4385231 3.84% 84.56% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3749968 3.28% 87.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10493751 9.19% 97.03% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1975559 1.73% 98.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1067200 0.93% 99.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 270053 0.24% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 78438 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 83205809 73.13% 73.13% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8622127 7.58% 80.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4341809 3.82% 84.53% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3750529 3.30% 87.83% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10472490 9.20% 97.03% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1973623 1.73% 98.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1061651 0.93% 99.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 265825 0.23% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 76970 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 114180028 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 113770833 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 28685 0.36% 0.36% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 990 0.01% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7576734 95.92% 96.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 292663 3.71% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29803 0.38% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 992 0.01% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7572506 95.90% 96.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 293239 3.71% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 314062 0.35% 0.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 37676817 42.11% 42.46% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 61442 0.07% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 2 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1698 0.00% 42.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.54% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 44006207 49.19% 91.72% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7404070 8.28% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 37491969 42.05% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 61148 0.07% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1700 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.47% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43923048 49.26% 91.73% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7369892 8.27% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 89464326 # Type of FU issued -system.cpu1.iq.rate 0.218509 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7899072 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.088293 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 301157769 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 78119517 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 54662771 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14827 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8100 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6807 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 97041573 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7763 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 356788 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 89161848 # Type of FU issued +system.cpu1.iq.rate 0.217987 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7896540 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.088564 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 300131429 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 77144913 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 54450273 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14948 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8092 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6814 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 96736439 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7887 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 357826 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3051550 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 4387 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17666 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1202172 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2919371 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 4089 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17660 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1133342 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31965367 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 692896 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31965401 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 692354 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2345636 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 24201399 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 366318 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 63975423 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 133542 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 13049293 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8227563 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 893848 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 67557 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3836 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17666 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 244185 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 171619 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 415804 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 87650825 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43476570 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1813501 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2250958 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 24192691 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 367138 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 63477454 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 113697 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 12919526 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8160199 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 893697 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 68960 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3858 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17660 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 208465 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 159370 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 367835 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 87401818 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43412086 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1760030 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 106113 # number of nop insts executed -system.cpu1.iew.exec_refs 50801692 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7123929 # Number of branches executed -system.cpu1.iew.exec_stores 7325122 # Number of stores executed -system.cpu1.iew.exec_rate 0.214080 # Inst execution rate -system.cpu1.iew.wb_sent 86821194 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 54669578 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 30455976 # num instructions producing a value -system.cpu1.iew.wb_consumers 54432612 # num instructions consuming a value +system.cpu1.iew.exec_nop 104288 # number of nop insts executed +system.cpu1.iew.exec_refs 50709476 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7088545 # Number of branches executed +system.cpu1.iew.exec_stores 7297390 # Number of stores executed +system.cpu1.iew.exec_rate 0.213684 # Inst execution rate +system.cpu1.iew.wb_sent 86601126 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 54457087 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 30364436 # num instructions producing a value +system.cpu1.iew.wb_consumers 54295656 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.133526 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.559517 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.133139 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.559242 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 14216299 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 920187 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 365862 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 111882823 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.440904 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.409715 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 13692554 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 920627 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 322274 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 111568344 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.442227 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.413238 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 94662436 84.61% 84.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8450873 7.55% 92.16% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2228797 1.99% 94.15% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1285384 1.15% 95.30% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1281795 1.15% 96.45% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 596967 0.53% 96.98% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1010034 0.90% 97.88% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 539540 0.48% 98.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1826997 1.63% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 94375668 84.59% 84.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8446118 7.57% 92.16% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2197127 1.97% 94.13% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1290727 1.16% 95.29% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1277171 1.14% 96.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 591366 0.53% 96.96% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1009730 0.91% 97.87% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 541366 0.49% 98.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1839071 1.65% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 111882823 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38951499 # Number of instructions committed -system.cpu1.commit.committedOps 49329594 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 111568344 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38958201 # Number of instructions committed +system.cpu1.commit.committedOps 49338577 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 17023134 # Number of memory references committed -system.cpu1.commit.loads 9997743 # Number of loads committed -system.cpu1.commit.membars 202380 # Number of memory barriers committed -system.cpu1.commit.branches 6138522 # Number of branches committed +system.cpu1.commit.refs 17027012 # Number of memory references committed +system.cpu1.commit.loads 10000155 # Number of loads committed +system.cpu1.commit.membars 202531 # Number of memory barriers committed +system.cpu1.commit.branches 6139960 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 43719778 # Number of committed integer instructions. -system.cpu1.commit.function_calls 556453 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1826997 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 43727423 # Number of committed integer instructions. +system.cpu1.commit.function_calls 556605 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1839071 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 172487010 # The number of ROB reads -system.cpu1.rob.rob_writes 129525616 # The number of ROB writes -system.cpu1.timesIdled 1423460 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 295250543 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4796554837 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38881860 # Number of Instructions Simulated -system.cpu1.committedOps 49259955 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 38881860 # Number of Instructions Simulated -system.cpu1.cpi 10.530118 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.530118 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.094966 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.094966 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 392568937 # number of integer regfile reads -system.cpu1.int_regfile_writes 56802865 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4926 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2332 # number of floating regfile writes -system.cpu1.misc_regfile_reads 81929191 # number of misc regfile reads -system.cpu1.misc_regfile_writes 429868 # number of misc regfile writes -system.cpu1.icache.replacements 620724 # number of replacements -system.cpu1.icache.tagsinuse 498.809985 # Cycle average of tags in use -system.cpu1.icache.total_refs 7273497 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 621236 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 11.708106 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74643061500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.809985 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.974238 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.974238 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 7273497 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7273497 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7273497 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7273497 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7273497 # number of overall hits -system.cpu1.icache.overall_hits::total 7273497 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 669686 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 669686 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 669686 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 669686 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 669686 # number of overall misses -system.cpu1.icache.overall_misses::total 669686 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8966780496 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8966780496 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8966780496 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8966780496 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8966780496 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8966780496 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 7943183 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 7943183 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 7943183 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 7943183 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 7943183 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 7943183 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084310 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.084310 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084310 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.084310 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084310 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.084310 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13389.529565 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13389.529565 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13389.529565 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13389.529565 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13389.529565 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13389.529565 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2782 # number of cycles access was blocked +system.cpu1.rob.rob_reads 171645222 # The number of ROB reads +system.cpu1.rob.rob_writes 128401309 # The number of ROB writes +system.cpu1.timesIdled 1423775 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 295253416 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4776625618 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38888562 # Number of Instructions Simulated +system.cpu1.committedOps 49268938 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 38888562 # Number of Instructions Simulated +system.cpu1.cpi 10.517855 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.517855 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.095076 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.095076 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 391481129 # number of integer regfile reads +system.cpu1.int_regfile_writes 56596470 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4905 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2328 # number of floating regfile writes +system.cpu1.misc_regfile_reads 81326805 # number of misc regfile reads +system.cpu1.misc_regfile_writes 430176 # number of misc regfile writes +system.cpu1.icache.replacements 614989 # number of replacements +system.cpu1.icache.tagsinuse 498.619037 # Cycle average of tags in use +system.cpu1.icache.total_refs 7122851 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 615501 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 11.572444 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74507010000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 498.619037 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.973865 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.973865 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 7122851 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7122851 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7122851 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7122851 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7122851 # number of overall hits +system.cpu1.icache.overall_hits::total 7122851 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 661583 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 661583 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 661583 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 661583 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 661583 # number of overall misses +system.cpu1.icache.overall_misses::total 661583 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8883357995 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8883357995 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8883357995 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8883357995 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8883357995 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8883357995 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 7784434 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 7784434 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 7784434 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 7784434 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 7784434 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 7784434 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084988 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.084988 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084988 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.084988 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084988 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.084988 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13427.427844 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13427.427844 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13427.427844 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13427.427844 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13427.427844 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13427.427844 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 3547 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 195 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 182 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.266667 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 19.489011 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 48404 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 48404 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 48404 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 48404 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 48404 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 48404 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 621282 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 621282 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 621282 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 621282 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 621282 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 621282 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7328304997 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7328304997 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7328304997 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7328304997 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7328304997 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7328304997 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2925000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2925000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2925000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 2925000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.078216 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.078216 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.078216 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.078216 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.078216 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.078216 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11795.456809 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11795.456809 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11795.456809 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11795.456809 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11795.456809 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11795.456809 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46050 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 46050 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 46050 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 46050 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 46050 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 46050 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 615533 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 615533 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 615533 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 615533 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 615533 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 615533 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7269169496 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7269169496 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7269169496 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7269169496 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7269169496 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7269169496 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2823500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2823500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2823500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 2823500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.079072 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.079072 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.079072 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.079072 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.079072 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.079072 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11809.552853 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11809.552853 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11809.552853 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11809.552853 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11809.552853 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11809.552853 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 363973 # number of replacements -system.cpu1.dcache.tagsinuse 487.193831 # Cycle average of tags in use -system.cpu1.dcache.total_refs 13149320 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 364327 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 36.092082 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 70722416000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 487.193831 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.951550 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.951550 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8614465 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8614465 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4290599 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4290599 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 105175 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 105175 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100810 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 100810 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12905064 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12905064 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12905064 # number of overall hits -system.cpu1.dcache.overall_hits::total 12905064 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 401162 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 401162 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1564756 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1564756 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14285 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 14285 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10913 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10913 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1965918 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1965918 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1965918 # number of overall misses -system.cpu1.dcache.overall_misses::total 1965918 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6004176000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6004176000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 64721170014 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 64721170014 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 132767500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 132767500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 58656500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 58656500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 70725346014 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 70725346014 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 70725346014 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 70725346014 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 9015627 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 9015627 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5855355 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5855355 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 119460 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 119460 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 111723 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 111723 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14870982 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14870982 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14870982 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14870982 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044496 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.044496 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.267235 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.267235 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119580 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119580 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097679 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097679 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.132198 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.132198 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.132198 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.132198 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14966.960978 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14966.960978 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41361.828946 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 41361.828946 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9294.189709 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9294.189709 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5374.919820 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5374.919820 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 35975.735516 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 35975.735516 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 35975.735516 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 35975.735516 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 27876 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 16218 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3195 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 164 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.724883 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 98.890244 # average number of cycles each access was blocked +system.cpu1.dcache.replacements 363437 # number of replacements +system.cpu1.dcache.tagsinuse 485.666262 # Cycle average of tags in use +system.cpu1.dcache.total_refs 13086846 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 363802 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 35.972441 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 70623957000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 485.666262 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.948567 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.948567 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8551806 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8551806 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4291461 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4291461 # 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accesses +system.cpu1.dcache.overall_accesses::total 14810427 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044876 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.044876 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.267271 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.267271 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120811 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120811 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097843 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097843 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.132823 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.132823 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.132823 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.132823 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14998.048790 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14998.048790 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41277.190277 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 41277.190277 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9254.903339 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9254.903339 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5381.191738 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5381.191738 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 35909.547784 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 35909.547784 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 35909.547784 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 35909.547784 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 28351 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 15005 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3227 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 168 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.785559 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 89.315476 # average number of cycles each access was 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MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1570937 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1570937 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231800 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 231800 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163181 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 163181 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12837 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12837 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10908 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10908 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 394981 # number of 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uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 26961622519 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 196224910019 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 196224910019 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025711 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025711 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027869 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027869 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.107459 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.107459 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097634 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097634 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026561 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026561 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026561 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026561 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12385.472390 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12385.472390 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32555.372323 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32555.372323 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7094.570382 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7094.570382 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3377.383572 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3377.383572 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20718.390786 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20718.390786 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20718.390786 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20718.390786 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 328383 # number of writebacks +system.cpu1.dcache.writebacks::total 328383 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 170419 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 170419 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1402227 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1402227 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1450 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1450 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1572646 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1572646 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1572646 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1572646 # number of overall MSHR hits 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394514 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 394514 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2870368000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2870368000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5301094210 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5301094210 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90117500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90117500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 37009000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 37009000 # number of StoreCondReq MSHR miss cycles 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overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 196211421394 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025842 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025842 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027853 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027853 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.108496 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.108496 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097790 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097790 # mshr miss rate for StoreCondReq accesses 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+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7054.207436 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3384.144111 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3384.144111 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20712.730626 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20712.730626 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20712.730626 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20712.730626 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1821,18 +1847,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1082331782222 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1082331782222 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1082331782222 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1082331782222 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1082174693399 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1082174693399 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1082174693399 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1082174693399 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 43796 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 43757 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 53932 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 53969 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index e428e398a..fbd26bc50 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -8,13 +8,14 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem -children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver +children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver atags_addr=256 boot_loader=/projects/pd/randd/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 -clock=1 +clock=1000 dtb_filename= early_kernel_symbols=false +enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 @@ -23,7 +24,6 @@ load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing memories=system.physmem system.realview.nvmem -midr_regval=890224640 multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -39,7 +39,7 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge -clock=1 +clock=1000 delay=50000 ranges=268435456:520093695 1073741824:1610612735 req_size=16 @@ -69,7 +69,7 @@ read_only=true [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb tracer +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -117,6 +117,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -168,10 +169,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -179,7 +180,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -188,7 +189,7 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.toL2Bus.slave[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -198,10 +199,10 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.fuPool] type=FUPool @@ -471,10 +472,10 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 @@ -482,7 +483,7 @@ prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=32768 subblock_size=0 system=system @@ -491,11 +492,28 @@ trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.toL2Bus.slave[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -504,10 +522,47 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[2] +port=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=8 +block_size=64 +clock=500 +forward_snoops=true +hash_delay=1 +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +response_latency=20 +size=4194304 +subblock_size=0 +system=system +tgts_per_mshr=12 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[2] + +[system.cpu.toL2Bus] +type=CoherentBus +block_size=64 +clock=500 +header_cycles=1 +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -531,18 +586,18 @@ type=BaseCache addr_ranges=0:268435455 assoc=8 block_size=64 -clock=1 +clock=1000 forward_snoops=false hash_delay=1 -hit_latency=50000 -is_top_level=false +hit_latency=50 +is_top_level=true max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=50000 +response_latency=50 size=1024 subblock_size=0 system=system @@ -553,33 +608,6 @@ write_buffers=8 cpu_side=system.iobus.master[25] mem_side=system.membus.slave[1] -[system.l2c] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=8 -block_size=64 -clock=1 -forward_snoops=true -hash_delay=1 -hit_latency=10000 -is_top_level=false -max_miss_count=0 -mshrs=92 -prefetch_on_access=false -prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=10000 -size=4194304 -subblock_size=0 -system=system -tgts_per_mshr=16 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[2] - [system.membus] type=CoherentBus children=badaddr_responder @@ -590,11 +618,11 @@ use_default_range=false width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio -slave=system.system_port system.iocache.mem_side system.l2c.mem_side +slave=system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side [system.membus.badaddr_responder] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=0 pio_latency=100000 @@ -610,15 +638,28 @@ warn_access=warn pio=system.membus.default [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=true in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[2] @@ -633,7 +674,7 @@ system=system [system.realview.a9scu] type=A9SCU -clock=1 +clock=1000 pio_addr=520093696 pio_latency=100000 system=system @@ -642,7 +683,7 @@ pio=system.membus.master[5] [system.realview.aaci_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -689,7 +730,7 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 -clock=1 +clock=1000 config_latency=20000 ctrl_offset=2 disks=system.cf0 @@ -720,7 +761,7 @@ pio=system.iobus.master[4] [system.realview.dmac_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -729,7 +770,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake -clock=1 +clock=1000 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -746,7 +787,7 @@ pio=system.iobus.master[24] [system.realview.gic] type=Gic -clock=1 +clock=1000 cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 @@ -760,7 +801,7 @@ pio=system.membus.master[3] [system.realview.gpio0_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -770,7 +811,7 @@ pio=system.iobus.master[16] [system.realview.gpio1_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -780,7 +821,7 @@ pio=system.iobus.master[17] [system.realview.gpio2_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -790,7 +831,7 @@ pio=system.iobus.master[18] [system.realview.kmi0] type=Pl050 amba_id=1314896 -clock=1 +clock=1000 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -804,7 +845,7 @@ pio=system.iobus.master[5] [system.realview.kmi1] type=Pl050 amba_id=1314896 -clock=1 +clock=1000 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -817,7 +858,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -846,7 +887,7 @@ pio=system.membus.master[6] [system.realview.mmc_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -856,7 +897,7 @@ pio=system.iobus.master[22] [system.realview.nvmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 @@ -868,7 +909,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl -clock=1 +clock=1000 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -880,7 +921,7 @@ pio=system.iobus.master[1] [system.realview.rtc] type=PL031 amba_id=3412017 -clock=1 +clock=1000 gic=system.realview.gic int_delay=100000 int_num=42 @@ -893,7 +934,7 @@ pio=system.iobus.master[23] [system.realview.sci_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -903,7 +944,7 @@ pio=system.iobus.master[20] [system.realview.smc_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -913,7 +954,7 @@ pio=system.iobus.master[13] [system.realview.sp810_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -923,7 +964,7 @@ pio=system.iobus.master[14] [system.realview.ssp_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -933,7 +974,7 @@ pio=system.iobus.master[19] [system.realview.timer0] type=Sp804 amba_id=1316868 -clock=1 +clock=1000 clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -947,7 +988,7 @@ pio=system.iobus.master[2] [system.realview.timer1] type=Sp804 amba_id=1316868 -clock=1 +clock=1000 clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -960,7 +1001,7 @@ pio=system.iobus.master[3] [system.realview.uart] type=Pl011 -clock=1 +clock=1000 end_on_eot=false gic=system.realview.gic int_delay=100000 @@ -975,7 +1016,7 @@ pio=system.iobus.master[0] [system.realview.uart1_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -985,7 +1026,7 @@ pio=system.iobus.master[10] [system.realview.uart2_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -995,7 +1036,7 @@ pio=system.iobus.master[11] [system.realview.uart3_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -1005,7 +1046,7 @@ pio=system.iobus.master[12] [system.realview.watchdog_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -1019,16 +1060,6 @@ number=0 output=true port=3456 -[system.toL2Bus] -type=CoherentBus -block_size=64 -clock=1000 -header_cycles=1 -use_default_range=false -width=8 -master=system.l2c.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port - [system.vncserver] type=VncServer frame_capture=false diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr index affb69ad6..3ee89fc27 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr @@ -11,8 +11,6 @@ warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: LCD dual screen mode not supported -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr bpiallis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index 304caa505..e4320499c 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 12:10:34 +gem5 compiled Oct 30 2012 11:20:14 +gem5 started Oct 30 2012 21:11:31 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2537929870500 because m5_exit instruction encountered +Exiting @ tick 2523500318000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 68a4a5e77..6a79df0e0 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,114 +1,114 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.523629 # Number of seconds simulated -sim_ticks 2523629285500 # Number of ticks simulated -final_tick 2523629285500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.523500 # Number of seconds simulated +sim_ticks 2523500318000 # Number of ticks simulated +final_tick 2523500318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 77702 # Simulator instruction rate (inst/s) -host_op_rate 99947 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3235958193 # Simulator tick rate (ticks/s) -host_mem_usage 399788 # Number of bytes of host memory used -host_seconds 779.87 # Real time elapsed on the host -sim_insts 60597236 # Number of instructions simulated -sim_ops 77945371 # Number of ops (including micro ops) simulated +host_inst_rate 66325 # Simulator instruction rate (inst/s) +host_op_rate 85314 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2762063576 # Simulator tick rate (ticks/s) +host_mem_usage 400896 # Number of bytes of host memory used +host_seconds 913.63 # Real time elapsed on the host +sim_insts 60596849 # Number of instructions simulated +sim_ops 77944928 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 799232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9095696 # Number of bytes read from this memory -system.physmem.bytes_read::total 129436176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 799232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799232 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784448 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 2752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 798592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094096 # Number of bytes read from this memory +system.physmem.bytes_read::total 129433232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 798592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798592 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784064 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800520 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800136 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 55 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12488 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142154 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096906 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59132 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 43 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12478 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142129 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096860 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59126 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813150 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47367363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1395 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 316699 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3604212 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51289695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 316699 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 316699 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1499605 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1195133 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2694738 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1499605 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47367363 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 316699 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4799345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53984433 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096906 # Total number of read requests seen -system.physmem.writeReqs 813150 # Total number of write requests seen -system.physmem.cpureqs 218484 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966201984 # Total number of bytes read from memory -system.physmem.bytesWritten 52041600 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129436176 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6800520 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 390 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4690 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943619 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943957 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943433 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 943463 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943389 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943250 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943110 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943289 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943778 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943634 # Track reads on a per bank basis +system.physmem.num_writes::total 813144 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47369784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1091 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 316462 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3603763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51291149 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 316462 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 316462 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1499530 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1195194 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2694724 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1499530 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47369784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 316462 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4798956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53985873 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096860 # Total number of read requests seen +system.physmem.writeReqs 813144 # Total number of write requests seen +system.physmem.cpureqs 218421 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966199040 # Total number of bytes read from memory +system.physmem.bytesWritten 52041216 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129433232 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6800136 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 334 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4679 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943626 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943958 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943414 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 943465 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943376 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943238 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943099 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943292 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943771 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943641 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 943712 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943686 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943739 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943592 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 943646 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943219 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50102 # Track writes on a per bank basis +system.physmem.perBankRdReqs::11 943689 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943743 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943611 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 943653 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943238 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50107 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 50378 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 49977 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50030 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50914 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50821 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50673 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50817 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51140 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51219 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51127 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 49961 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50027 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50912 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50814 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50662 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50821 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51143 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51225 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51129 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 51111 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51352 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51299 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51032 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51353 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51175 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51296 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51030 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1156336 # Number of times wr buffer was full causing retry -system.physmem.totGap 2523628152000 # Total gap between requests +system.physmem.numWrRetry 1153879 # Number of times wr buffer was full causing retry +system.physmem.totGap 2523499110500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154662 # Categorize read packet sizes +system.physmem.readPktSize::6 154616 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 1910354 # categorize write packet sizes +system.physmem.writePktSize::2 1907897 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 59132 # categorize write packet sizes +system.physmem.writePktSize::6 59126 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -117,28 +117,28 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4690 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4679 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 14955823 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 89957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2881 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2059 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1873 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1682 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 14954842 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 89676 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6568 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2998 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2443 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2395 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1858 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1270 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 6283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 9566 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 13077 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 563 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 50 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1236 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 6388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 9595 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 13055 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 48 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 31 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -153,15 +153,15 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2950 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4040 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see @@ -176,37 +176,37 @@ system.physmem.wrQLenPdf::19 35354 # Wh system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 31809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 31595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 31423 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 31264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32553 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 31840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 31628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 31465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 31314 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 46839255594 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 317495505594 # Sum of mem lat for all requests -system.physmem.totBusLat 60386064000 # Total cycles spent in databus access -system.physmem.totBankLat 210270186000 # Total cycles spent in bank access -system.physmem.avgQLat 3102.65 # Average queueing delay per request -system.physmem.avgBankLat 13928.39 # Average bank access latency per request +system.physmem.totQLat 47052553851 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 317720785851 # Sum of mem lat for all requests +system.physmem.totBusLat 60386104000 # Total cycles spent in databus access +system.physmem.totBankLat 210282128000 # Total cycles spent in bank access +system.physmem.avgQLat 3116.78 # Average queueing delay per request +system.physmem.avgBankLat 13929.17 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 21031.04 # Average memory access latency -system.physmem.avgRdBW 382.86 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 21045.95 # Average memory access latency +system.physmem.avgRdBW 382.88 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.29 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.52 # Data bus utilization in percentage system.physmem.avgRdQLen 0.13 # Average read queue length over time -system.physmem.avgWrQLen 13.20 # Average write queue length over time -system.physmem.readRowHits 15050623 # Number of row buffer hits during reads -system.physmem.writeRowHits 784578 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.70 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 96.49 # Row buffer hit rate for writes -system.physmem.avgGap 158618.43 # Average gap between requests +system.physmem.avgWrQLen 11.37 # Average write queue length over time +system.physmem.readRowHits 15049962 # Number of row buffer hits during reads +system.physmem.writeRowHits 784769 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.69 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 96.51 # Row buffer hit rate for writes +system.physmem.avgGap 158610.84 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -227,27 +227,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51393832 # DTB read hits -system.cpu.dtb.read_misses 77273 # DTB read misses -system.cpu.dtb.write_hits 11807513 # DTB write hits -system.cpu.dtb.write_misses 17284 # DTB write misses +system.cpu.dtb.read_hits 51279526 # DTB read hits +system.cpu.dtb.read_misses 73667 # DTB read misses +system.cpu.dtb.write_hits 11753863 # DTB write hits +system.cpu.dtb.write_misses 17234 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4230 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2923 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 497 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4224 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2376 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 510 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1303 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51471105 # DTB read accesses -system.cpu.dtb.write_accesses 11824797 # DTB write accesses +system.cpu.dtb.perms_faults 1366 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51353193 # DTB read accesses +system.cpu.dtb.write_accesses 11771097 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63201345 # DTB hits -system.cpu.dtb.misses 94557 # DTB misses -system.cpu.dtb.accesses 63295902 # DTB accesses -system.cpu.itb.inst_hits 11866090 # ITB inst hits -system.cpu.itb.inst_misses 12256 # ITB inst misses +system.cpu.dtb.hits 63033389 # DTB hits +system.cpu.dtb.misses 90901 # DTB misses +system.cpu.dtb.accesses 63124290 # DTB accesses +system.cpu.itb.inst_hits 11603865 # ITB inst hits +system.cpu.itb.inst_misses 11359 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -256,688 +256,526 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2603 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2573 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3056 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2961 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11878346 # ITB inst accesses -system.cpu.itb.hits 11866090 # DTB hits -system.cpu.itb.misses 12256 # DTB misses -system.cpu.itb.accesses 11878346 # DTB accesses -system.cpu.numCycles 471617242 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11615224 # ITB inst accesses +system.cpu.itb.hits 11603865 # DTB hits +system.cpu.itb.misses 11359 # DTB misses +system.cpu.itb.accesses 11615224 # DTB accesses +system.cpu.numCycles 470951029 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14707934 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11701482 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 783806 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 9735591 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7867248 # Number of BTB hits +system.cpu.BPredUnit.lookups 14482147 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11548936 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 711590 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 9469344 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7720983 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1454059 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 82839 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 30177247 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 91949952 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14707934 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9321307 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20604105 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4981007 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 133002 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 96623906 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2605 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 100214 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 208761 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 353 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11862293 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 731589 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6461 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151283915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.758817 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.115765 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1413907 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 72813 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 29880342 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90834905 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14482147 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9134890 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20280806 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4750716 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 122594 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 96709258 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2560 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 94111 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 205295 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 281 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11600179 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 700998 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5704 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 150571175 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.752471 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.109183 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130696614 86.39% 86.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1382439 0.91% 87.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1755242 1.16% 88.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2339470 1.55% 90.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2142585 1.42% 91.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1134296 0.75% 92.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2618835 1.73% 93.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 784869 0.52% 94.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8429565 5.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130305873 86.54% 86.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1344979 0.89% 87.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1685836 1.12% 88.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2306234 1.53% 90.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2113026 1.40% 91.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1118544 0.74% 92.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2593877 1.72% 93.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 765442 0.51% 94.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8337364 5.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151283915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031186 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.194967 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32009474 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96255861 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18724959 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1031397 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3262224 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2019817 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174593 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 109260478 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 576218 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3262224 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33806773 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36827261 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 53335707 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17902220 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6149730 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 104066052 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21507 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1015259 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4119258 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 31916 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 107817309 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 475022232 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 474932056 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90176 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78731209 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 29086099 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 892462 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 797997 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12333143 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20063520 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13521808 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1973034 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2429271 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 96511584 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2058662 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 123961862 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 189585 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 20013916 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 50091772 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 514148 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151283915 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.819399 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.531663 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 150571175 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030751 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.192875 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31657449 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96342520 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18430846 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1034189 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3106171 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1969595 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172369 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107934392 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 571655 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3106171 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33426960 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36897380 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 53334301 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17638840 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6167523 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102924268 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21343 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1016075 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4132060 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 29183 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106686272 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 469883831 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 469792749 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 91082 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78730768 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27955503 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 879837 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 786100 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12323975 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19838005 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13393703 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1972033 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2410684 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95618817 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2046180 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 123387582 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 174864 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19151232 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 48036492 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501695 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 150571175 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.819463 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.532492 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 106904579 70.66% 70.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13863783 9.16% 79.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7099546 4.69% 84.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5863279 3.88% 88.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12474907 8.25% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2771705 1.83% 98.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1719952 1.14% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 458027 0.30% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128137 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 106455995 70.70% 70.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13758975 9.14% 79.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7009673 4.66% 84.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5842702 3.88% 88.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12442883 8.26% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2768710 1.84% 98.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1710517 1.14% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 450789 0.30% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 130931 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151283915 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 150571175 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 57031 0.64% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 3 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8373952 94.62% 95.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 418898 4.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 59954 0.68% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8366032 94.65% 95.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 413370 4.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58283800 47.02% 47.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95201 0.08% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52766411 42.57% 89.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12450621 10.04% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57926411 46.95% 47.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93267 0.08% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 17 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 17 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52616961 42.64% 89.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12385106 10.04% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 123961862 # Type of FU issued -system.cpu.iq.rate 0.262844 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8849884 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071392 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 408318037 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 118600535 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86285351 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23227 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12408 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10278 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132435732 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12348 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 629942 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 123387582 # Type of FU issued +system.cpu.iq.rate 0.261997 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8839360 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071639 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 406427994 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116832614 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85860436 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23103 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12565 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10308 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131851026 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12250 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624646 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4347483 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7997 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29897 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1723272 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4122070 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6381 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30063 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1595239 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34108218 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 695964 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107814 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 695818 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3262224 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27920683 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 435052 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 98794824 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 232558 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20063520 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13521808 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1467094 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 114012 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3652 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29897 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 410015 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 293518 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 703533 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121755337 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52081116 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2206525 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3106171 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27981842 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 438339 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97885744 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 205866 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19838005 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13393703 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1459318 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 116468 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3836 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30063 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 352690 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 272400 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 625090 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121269392 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51965419 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2118190 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 224578 # number of nop insts executed -system.cpu.iew.exec_refs 64400589 # number of memory reference insts executed -system.cpu.iew.exec_branches 11599904 # Number of branches executed -system.cpu.iew.exec_stores 12319473 # Number of stores executed -system.cpu.iew.exec_rate 0.258166 # Inst execution rate -system.cpu.iew.wb_sent 120729614 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86295629 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47354389 # num instructions producing a value -system.cpu.iew.wb_consumers 88420573 # num instructions consuming a value +system.cpu.iew.exec_nop 220747 # number of nop insts executed +system.cpu.iew.exec_refs 64230871 # number of memory reference insts executed +system.cpu.iew.exec_branches 11527542 # Number of branches executed +system.cpu.iew.exec_stores 12265452 # Number of stores executed +system.cpu.iew.exec_rate 0.257499 # Inst execution rate +system.cpu.iew.wb_sent 120289637 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85870744 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47162688 # num instructions producing a value +system.cpu.iew.wb_consumers 88075667 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182978 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535558 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182335 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535479 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 19868776 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1544514 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 612308 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 148104118 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.527303 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.512767 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18952599 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1544485 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 541833 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147547429 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.529290 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.517447 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120332893 81.25% 81.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13565443 9.16% 90.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3964002 2.68% 93.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2135941 1.44% 94.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1954116 1.32% 95.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 973664 0.66% 96.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1592335 1.08% 97.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 730104 0.49% 98.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2855620 1.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 119858518 81.23% 81.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13515143 9.16% 90.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3916529 2.65% 93.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2132463 1.45% 94.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1950760 1.32% 95.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 976387 0.66% 96.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1592516 1.08% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 731256 0.50% 98.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2873857 1.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 148104118 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60747617 # Number of instructions committed -system.cpu.commit.committedOps 78095752 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 147547429 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60747230 # Number of instructions committed +system.cpu.commit.committedOps 78095309 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27514573 # Number of memory references committed -system.cpu.commit.loads 15716037 # Number of loads committed -system.cpu.commit.membars 413105 # Number of memory barriers committed -system.cpu.commit.branches 10023091 # Number of branches committed +system.cpu.commit.refs 27514399 # Number of memory references committed +system.cpu.commit.loads 15715935 # Number of loads committed +system.cpu.commit.membars 413101 # Number of memory barriers committed +system.cpu.commit.branches 10023041 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69134185 # Number of committed integer instructions. -system.cpu.commit.function_calls 995980 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2855620 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69133795 # Number of committed integer instructions. +system.cpu.commit.function_calls 995976 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2873857 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 241297904 # The number of ROB reads -system.cpu.rob.rob_writes 199283253 # The number of ROB writes -system.cpu.timesIdled 1774711 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320333327 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575553300 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60597236 # Number of Instructions Simulated -system.cpu.committedOps 77945371 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60597236 # Number of Instructions Simulated -system.cpu.cpi 7.782818 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.782818 # CPI: Total CPI of All Threads -system.cpu.ipc 0.128488 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.128488 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 551506175 # number of integer regfile reads -system.cpu.int_regfile_writes 88407137 # number of integer regfile writes -system.cpu.fp_regfile_reads 8339 # number of floating regfile reads -system.cpu.fp_regfile_writes 2916 # number of floating regfile writes -system.cpu.misc_regfile_reads 124072221 # number of misc regfile reads -system.cpu.misc_regfile_writes 912903 # number of misc regfile writes -system.cpu.icache.replacements 990875 # number of replacements -system.cpu.icache.tagsinuse 510.405236 # Cycle average of tags in use -system.cpu.icache.total_refs 10787830 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 991387 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 10.881553 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6691567000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.405236 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996885 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996885 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10787830 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10787830 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10787830 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10787830 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10787830 # number of overall hits -system.cpu.icache.overall_hits::total 10787830 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1074333 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1074333 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1074333 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1074333 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1074333 # number of overall misses -system.cpu.icache.overall_misses::total 1074333 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14125562486 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14125562486 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14125562486 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14125562486 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14125562486 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14125562486 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11862163 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11862163 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11862163 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11862163 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11862163 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11862163 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.090568 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.090568 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.090568 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.090568 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.090568 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.090568 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13148.216136 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13148.216136 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13148.216136 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13148.216136 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13148.216136 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13148.216136 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4400 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 296 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 14.864865 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.rob.rob_reads 239806361 # The number of ROB reads +system.cpu.rob.rob_writes 197293644 # The number of ROB writes +system.cpu.timesIdled 1776983 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320379854 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575961583 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60596849 # Number of Instructions Simulated +system.cpu.committedOps 77944928 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60596849 # Number of Instructions Simulated +system.cpu.cpi 7.771873 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.771873 # CPI: Total CPI of All Threads +system.cpu.ipc 0.128669 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.128669 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 549353817 # number of integer regfile reads +system.cpu.int_regfile_writes 87979071 # number of integer regfile writes +system.cpu.fp_regfile_reads 8318 # number of floating regfile reads +system.cpu.fp_regfile_writes 2932 # number of floating regfile writes +system.cpu.misc_regfile_reads 122823412 # number of misc regfile reads +system.cpu.misc_regfile_writes 912865 # number of misc regfile writes +system.cpu.icache.replacements 980837 # number of replacements +system.cpu.icache.tagsinuse 511.007226 # Cycle average of tags in use +system.cpu.icache.total_refs 10539450 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 981349 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 10.739757 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6666804000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.007226 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.998061 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.998061 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 10539450 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10539450 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10539450 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10539450 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10539450 # number of overall hits +system.cpu.icache.overall_hits::total 10539450 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1060605 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1060605 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1060605 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1060605 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1060605 # number of overall misses +system.cpu.icache.overall_misses::total 1060605 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13961403491 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13961403491 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13961403491 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13961403491 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13961403491 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13961403491 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11600055 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11600055 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11600055 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11600055 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11600055 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11600055 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091431 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.091431 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.091431 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.091431 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.091431 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.091431 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13163.622169 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13163.622169 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13163.622169 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13163.622169 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13163.622169 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13163.622169 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5262 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 8 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 297 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 17.717172 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 8 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 82890 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 82890 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 82890 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 82890 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 82890 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 82890 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11354795991 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11354795991 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11354795991 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6803000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6803000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6803000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 6803000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.084602 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.084602 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.084602 # 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average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 645101 # number of replacements -system.cpu.dcache.tagsinuse 511.994184 # Cycle average of tags in use -system.cpu.dcache.total_refs 21772820 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 645613 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.724259 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 35202000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.994184 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999989 # 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number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 730115 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 730115 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2961662 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2961662 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13591 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13591 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 19 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 19 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3691777 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3691777 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3691777 # number of overall misses -system.cpu.dcache.overall_misses::total 3691777 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9540231500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9540231500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 104360444235 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 104360444235 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180814000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 180814000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 283000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 283000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 113900675735 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 113900675735 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 113900675735 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 113900675735 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14639834 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14639834 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10250683 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10250683 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 298787 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 298787 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285758 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285758 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24890517 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24890517 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24890517 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24890517 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049872 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.049872 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288923 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.288923 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045487 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045487 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000066 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000066 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.148321 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.148321 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.148321 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.148321 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13066.751813 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13066.751813 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35237.121669 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35237.121669 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13303.951144 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13303.951144 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 14894.736842 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 14894.736842 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30852.534087 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30852.534087 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30852.534087 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30852.534087 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29089 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 14501 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2531 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 252 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.493086 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 57.543651 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 609133 # number of writebacks -system.cpu.dcache.writebacks::total 609133 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 342878 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 342878 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2712526 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2712526 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1365 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1365 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3055404 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3055404 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3055404 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3055404 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387237 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 387237 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249136 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249136 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12226 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12226 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 19 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 19 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 636373 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 636373 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 636373 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 636373 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4781839500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4781839500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8147970920 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8147970920 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141479000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141479000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 245000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 245000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12929810420 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12929810420 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12929810420 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12929810420 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182356641500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182356641500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 28006523855 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 28006523855 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210363165355 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 210363165355 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026451 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026451 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024304 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024304 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.040919 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.040919 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000066 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000066 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025567 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025567 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025567 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025567 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12348.612090 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12348.612090 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32704.911855 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32704.911855 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11571.977752 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11571.977752 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12894.736842 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12894.736842 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20317.974553 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20317.974553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20317.974553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20317.974553 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 64428 # number of replacements -system.cpu.l2cache.tagsinuse 51367.264734 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1930539 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129823 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 14.870547 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2488482557500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 36879.772922 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 44.022997 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000230 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 8192.461940 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6251.006645 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.562741 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000672 # Average percentage of cache occupancy +system.cpu.l2cache.replacements 64388 # number of replacements +system.cpu.l2cache.tagsinuse 51373.602635 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1911501 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 129780 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 14.728779 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2488431429000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 36915.014302 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 29.696477 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000348 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 8183.272105 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6245.619403 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.563278 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000453 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.125007 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.095383 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.783802 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 83028 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12007 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 977743 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 388649 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1461427 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 609133 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 609133 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 53 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 53 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 16 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 113031 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 113031 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 83028 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 12007 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 977743 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 501680 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1574458 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 83028 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 12007 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 977743 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 501680 # number of overall hits -system.cpu.l2cache.overall_hits::total 1574458 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 55 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12377 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10733 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 23166 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2933 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2933 # number of UpgradeReq misses +system.cpu.l2cache.occ_percent::cpu.inst 0.124867 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.095301 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.783899 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 79304 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10595 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 967765 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 387173 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1444837 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 607749 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 607749 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 43 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 43 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 9 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 112887 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 112887 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 79304 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 10595 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 967765 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 500060 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1557724 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 79304 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 10595 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 967765 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 500060 # number of overall hits +system.cpu.l2cache.overall_hits::total 1557724 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 43 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12372 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 10735 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 23152 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2918 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2918 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133200 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133200 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 55 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12377 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143933 # 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number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 478000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6695831998 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6695831998 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3825000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 49000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 666073500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7284872996 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7954820496 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3825000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 49000 # 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miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046329 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000042 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000042 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.148951 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.148951 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.148951 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.148951 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13079.075268 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13079.075268 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35640.300937 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35640.300937 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13304.748275 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13304.748275 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31170.534336 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31170.534336 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31170.534336 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 30622 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 13737 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2589 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 255 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.827733 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 53.870588 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 607749 # number of writebacks +system.cpu.dcache.writebacks::total 607749 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345667 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 345667 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2711644 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2711644 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1415 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1415 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3057311 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3057311 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3057311 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3057311 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385788 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385788 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248933 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248933 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12211 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12211 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634721 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634721 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634721 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634721 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4768255000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4768255000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8227495919 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8227495919 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141520500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141520500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 168000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 168000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12995750919 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12995750919 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12995750919 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12995750919 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182357111500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182357111500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 27981839814 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 27981839814 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210338951314 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 210338951314 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026540 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026540 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024285 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024285 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041517 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041517 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000042 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000042 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025607 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025607 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025607 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12359.780501 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12359.780501 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33051.045538 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33051.045538 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11589.591352 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11589.591352 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20474.745469 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20474.745469 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1072,16 +1072,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1068163777856 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1068163777856 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1068163777856 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1068163777856 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1068305538529 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1068305538529 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1068305538529 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1068305538529 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88030 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88025 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |