diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm')
8 files changed, 11491 insertions, 9703 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index ad6f569ba..59143a518 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,174 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.145505 # Number of seconds simulated -sim_ticks 1145504982000 # Number of ticks simulated -final_tick 1145504982000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.658500 # Number of seconds simulated +sim_ticks 2658500429500 # Number of ticks simulated +final_tick 2658500429500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 113120 # Simulator instruction rate (inst/s) -host_op_rate 136231 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2095202848 # Simulator tick rate (ticks/s) -host_mem_usage 413760 # Number of bytes of host memory used -host_seconds 546.73 # Real time elapsed on the host -sim_insts 61845931 # Number of instructions simulated -sim_ops 74481224 # Number of ops (including micro ops) simulated +host_inst_rate 100914 # Simulator instruction rate (inst/s) +host_op_rate 121517 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4256503307 # Simulator tick rate (ticks/s) +host_mem_usage 437672 # Number of bytes of host memory used +host_seconds 624.57 # Real time elapsed on the host +sim_insts 63028509 # Number of instructions simulated +sim_ops 75896503 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu0.inst 256 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 704 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 256 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 4 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 223 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 391 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 615 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 223 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 391 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 615 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 223 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 391 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 615 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.clcd 50331648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 7004988 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3603320 # Number of bytes read from this memory -system.physmem.bytes_read::total 60941044 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 751104 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 270784 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1021888 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4281152 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 670652 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 5012160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 503736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 5163008 # Number of bytes read from this memory +system.physmem.bytes_read::total 134034100 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 219584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 61824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 281408 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4338816 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.inst 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.inst 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7308496 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 6291456 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 6 # Number of read requests responded to by this memory +system.physmem.bytes_written::cpu1.inst 3012136 # Number of bytes written to this memory +system.physmem.bytes_written::total 7367952 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 109512 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 9 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 56320 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6457305 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66893 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10538 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 78315 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 7889 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 80672 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15512856 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 67794 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.inst 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.inst 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823729 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43938393 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 112 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 6115196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 3145617 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53200156 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 655697 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 236388 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 892085 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3737349 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.inst 14841 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.inst 2627962 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6380152 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3737349 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43938393 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 112 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 6130037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 5773579 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 59580308 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6457305 # Number of read requests accepted -system.physmem.writeReqs 823729 # Number of write requests accepted -system.physmem.readBursts 6457305 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 823729 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 413239936 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 27584 # Total number of bytes read from write queue -system.physmem.bytesWritten 7320448 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 60941044 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7308496 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 431 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 709326 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 12284 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 403300 # Per bank write bursts -system.physmem.perBankRdBursts::1 403658 # Per bank write bursts -system.physmem.perBankRdBursts::2 403038 # Per bank write bursts -system.physmem.perBankRdBursts::3 403410 # Per bank write bursts -system.physmem.perBankRdBursts::4 406147 # Per bank write bursts -system.physmem.perBankRdBursts::5 403703 # Per bank write bursts -system.physmem.perBankRdBursts::6 403511 # Per bank write bursts -system.physmem.perBankRdBursts::7 403334 # Per bank write bursts -system.physmem.perBankRdBursts::8 403656 # Per bank write bursts -system.physmem.perBankRdBursts::9 404136 # Per bank write bursts -system.physmem.perBankRdBursts::10 403079 # Per bank write bursts -system.physmem.perBankRdBursts::11 402530 # Per bank write bursts -system.physmem.perBankRdBursts::12 403635 # Per bank write bursts -system.physmem.perBankRdBursts::13 403544 # Per bank write bursts -system.physmem.perBankRdBursts::14 403293 # Per bank write bursts -system.physmem.perBankRdBursts::15 402900 # Per bank write bursts -system.physmem.perBankWrBursts::0 6991 # Per bank write bursts -system.physmem.perBankWrBursts::1 7395 # Per bank write bursts -system.physmem.perBankWrBursts::2 6850 # Per bank write bursts -system.physmem.perBankWrBursts::3 7056 # Per bank write bursts -system.physmem.perBankWrBursts::4 7584 # Per bank write bursts -system.physmem.perBankWrBursts::5 7290 # Per bank write bursts -system.physmem.perBankWrBursts::6 7311 # Per bank write bursts -system.physmem.perBankWrBursts::7 7141 # Per bank write bursts -system.physmem.perBankWrBursts::8 7309 # Per bank write bursts -system.physmem.perBankWrBursts::9 7743 # Per bank write bursts -system.physmem.perBankWrBursts::10 6877 # Per bank write bursts -system.physmem.perBankWrBursts::11 6465 # Per bank write bursts -system.physmem.perBankWrBursts::12 7382 # Per bank write bursts -system.physmem.perBankWrBursts::13 7153 # Per bank write bursts -system.physmem.perBankWrBursts::14 7067 # Per bank write bursts -system.physmem.perBankWrBursts::15 6768 # Per bank write bursts +system.physmem.num_writes::cpu1.inst 753034 # Number of write requests responded to by this memory +system.physmem.num_writes::total 825078 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46147592 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 120 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 48 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 252267 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 1885334 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 241 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 24 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 189481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 1942075 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50417182 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 82597 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 23255 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 105852 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1632054 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.inst 6395 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.inst 1133021 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2771469 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1632054 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46147592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 120 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 48 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 258662 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 1885334 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 241 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 24 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 1322502 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 1942075 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53188651 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15512856 # Number of read requests accepted +system.physmem.writeReqs 825078 # Number of write requests accepted +system.physmem.readBursts 15512856 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 825078 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 992706816 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 115968 # Total number of bytes read from write queue +system.physmem.bytesWritten 7383872 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 134034100 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7367952 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1812 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 709689 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 15707 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 969471 # Per bank write bursts +system.physmem.perBankRdBursts::1 969246 # Per bank write bursts +system.physmem.perBankRdBursts::2 969043 # Per bank write bursts +system.physmem.perBankRdBursts::3 969564 # Per bank write bursts +system.physmem.perBankRdBursts::4 971813 # Per bank write bursts +system.physmem.perBankRdBursts::5 969510 # Per bank write bursts +system.physmem.perBankRdBursts::6 969103 # Per bank write bursts +system.physmem.perBankRdBursts::7 968972 # Per bank write bursts +system.physmem.perBankRdBursts::8 969597 # Per bank write bursts +system.physmem.perBankRdBursts::9 969588 # Per bank write bursts +system.physmem.perBankRdBursts::10 969467 # Per bank write bursts +system.physmem.perBankRdBursts::11 968939 # Per bank write bursts +system.physmem.perBankRdBursts::12 969138 # Per bank write bursts +system.physmem.perBankRdBursts::13 969444 # Per bank write bursts +system.physmem.perBankRdBursts::14 969295 # Per bank write bursts +system.physmem.perBankRdBursts::15 968854 # Per bank write bursts +system.physmem.perBankWrBursts::0 7363 # Per bank write bursts +system.physmem.perBankWrBursts::1 7345 # Per bank write bursts +system.physmem.perBankWrBursts::2 6989 # Per bank write bursts +system.physmem.perBankWrBursts::3 7254 # Per bank write bursts +system.physmem.perBankWrBursts::4 7419 # Per bank write bursts +system.physmem.perBankWrBursts::5 7425 # Per bank write bursts +system.physmem.perBankWrBursts::6 7374 # Per bank write bursts +system.physmem.perBankWrBursts::7 7152 # Per bank write bursts +system.physmem.perBankWrBursts::8 7408 # Per bank write bursts +system.physmem.perBankWrBursts::9 7360 # Per bank write bursts +system.physmem.perBankWrBursts::10 7357 # Per bank write bursts +system.physmem.perBankWrBursts::11 7062 # Per bank write bursts +system.physmem.perBankWrBursts::12 6947 # Per bank write bursts +system.physmem.perBankWrBursts::13 7077 # Per bank write bursts +system.physmem.perBankWrBursts::14 7057 # Per bank write bursts +system.physmem.perBankWrBursts::15 6784 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1145502120500 # Total gap between requests +system.physmem.totGap 2658500409000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 59 # Read request sizes (log2) -system.physmem.readPktSize::3 6291481 # Read request sizes (log2) +system.physmem.readPktSize::3 15335449 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 165765 # Read request sizes (log2) +system.physmem.readPktSize::6 177348 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 756836 # Write request sizes (log2) +system.physmem.writePktSize::2 757284 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66893 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 558286 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 398741 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 399967 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 444496 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 405001 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 431562 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1118263 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1083915 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1408608 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 55788 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 45494 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 41962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 40334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8421 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 7962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 7851 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 67794 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1046196 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1019688 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 986842 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1094338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 993106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1055542 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2738032 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2641383 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3439999 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 128528 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 110050 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 101603 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 98027 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19641 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18942 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18731 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 149 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 85 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 21 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see @@ -186,31 +180,31 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6584 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6660 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4092 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5835 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see @@ -235,456 +229,585 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 460787 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 912.700193 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 781.910252 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 290.668132 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24338 5.28% 5.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 21658 4.70% 9.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5935 1.29% 11.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2553 0.55% 11.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2424 0.53% 12.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1615 0.35% 12.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4021 0.87% 13.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 977 0.21% 13.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 397266 86.21% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 460787 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6652 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 970.665664 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 26177.869763 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-65535 6645 99.89% 99.89% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-262143 3 0.05% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.50733e+06-1.57286e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6652 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6652 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.195129 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.166489 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.984981 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2678 40.26% 40.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 22 0.33% 40.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3930 59.08% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 20 0.30% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6652 # Writes before turning the bus around for reads -system.physmem.totQLat 165525335000 # Total ticks spent queuing -system.physmem.totMemAccLat 286591722500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 32284370000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25635.52 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1037696 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 963.760762 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 885.523874 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 219.463963 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 32040 3.09% 3.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 21332 2.06% 5.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9404 0.91% 6.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2470 0.24% 6.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3075 0.30% 6.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2164 0.21% 6.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8825 0.85% 7.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1075 0.10% 7.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 957311 92.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1037696 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6640 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2336.000602 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 97357.467769 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-262143 6632 99.88% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::262144-524287 2 0.03% 99.91% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::524288-786431 3 0.05% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::7.60218e+06-7.86432e+06 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6640 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6640 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.375452 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.330517 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.281391 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2518 37.92% 37.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 36 0.54% 38.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3683 55.47% 93.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 190 2.86% 96.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 92 1.39% 98.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 40 0.60% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 30 0.45% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 20 0.30% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 15 0.23% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 13 0.20% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6640 # Writes before turning the bus around for reads +system.physmem.totQLat 403478953250 # Total ticks spent queuing +system.physmem.totMemAccLat 694311028250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77555220000 # Total ticks spent in databus transfers +system.physmem.avgQLat 26012.37 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44385.52 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 360.75 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 6.39 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 53.20 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 6.38 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44762.37 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 373.41 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.78 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.42 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.77 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.87 # Data bus utilization in percentage -system.physmem.busUtilRead 2.82 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 3.81 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.84 # Average write queue length when enqueuing -system.physmem.readRowHits 6016106 # Number of row buffer hits during reads -system.physmem.writeRowHits 94363 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.17 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 82.48 # Row buffer hit rate for writes -system.physmem.avgGap 157326.85 # Average gap between requests -system.physmem.pageHitRate 92.99 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 907058635500 # Time in different power states -system.physmem.memoryStateTime::REF 38250680000 # Time in different power states +system.physmem.busUtil 2.94 # Data bus utilization in percentage +system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 6.07 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.23 # Average write queue length when enqueuing +system.physmem.readRowHits 14503444 # Number of row buffer hits during reads +system.physmem.writeRowHits 85277 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.50 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.90 # Row buffer hit rate for writes +system.physmem.avgGap 162719.50 # Average gap between requests +system.physmem.pageHitRate 93.36 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2316371594000 # Time in different power states +system.physmem.memoryStateTime::REF 88773100000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 200188472000 # Time in different power states +system.physmem.memoryStateTime::ACT 253353834750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 61688542 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7506218 # Transaction distribution -system.membus.trans_dist::ReadResp 7506218 # Transaction distribution -system.membus.trans_dist::WriteReq 767823 # Transaction distribution -system.membus.trans_dist::WriteResp 767823 # Transaction distribution -system.membus.trans_dist::Writeback 66893 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33061 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 17229 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12284 # Transaction distribution -system.membus.trans_dist::ReadExReq 137868 # Transaction distribution -system.membus.trans_dist::ReadExResp 137512 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382652 # Packet count per connected master and slave (bytes) +system.realview.nvmem.bytes_read::cpu0.inst 256 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 704 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 256 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 4 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 96 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 169 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 265 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 96 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 169 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 265 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 96 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 169 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 265 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 16692425 # Transaction distribution +system.membus.trans_dist::ReadResp 16692425 # Transaction distribution +system.membus.trans_dist::WriteReq 768873 # Transaction distribution +system.membus.trans_dist::WriteResp 768873 # Transaction distribution +system.membus.trans_dist::Writeback 67794 # Transaction distribution +system.membus.trans_dist::UpgradeReq 55379 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 22285 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15707 # Transaction distribution +system.membus.trans_dist::ReadExReq 15268 # Transaction distribution +system.membus.trans_dist::ReadExResp 8420 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384472 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11272 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 12568 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 874 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1975193 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4370017 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12582912 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 12582912 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 16952929 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389988 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 22544 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1748 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17917892 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 20332884 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 50331648 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 50331648 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 70664532 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 70664532 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1775897999 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.reqLayer1.occupancy 16500 # Layer occupancy (ticks) +system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2090 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2037445 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4436601 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 35107449 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2392888 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 25136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4180 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18718660 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 21141576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 143824968 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 68805 # Total snoops (count) +system.membus.snoop_fanout::samples 327203 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 327203 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 327203 # Request fanout histogram +system.membus.reqLayer0.occupancy 1769123496 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 10198500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 10983499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 781000 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1597500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 8866177000 # Layer occupancy (ticks) -system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4931588399 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 15569082998 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17876588998 # Layer occupancy (ticks) +system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 5004631688 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer2.occupancy 37937018429 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 73238 # number of replacements -system.l2c.tags.tagsinuse 53823.910561 # Cycle average of tags in use -system.l2c.tags.total_refs 2398257 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 138408 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 17.327445 # Average number of references to valid blocks. +system.l2c.tags.replacements 92212 # number of replacements +system.l2c.tags.tagsinuse 55213.567741 # Cycle average of tags in use +system.l2c.tags.total_refs 396364 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 156868 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.526736 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 38958.946929 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.880846 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001294 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 8788.881914 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.740937 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 6066.458640 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.594466 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000029 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.134108 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000118 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.092567 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.821288 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65164 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2438 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8664 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53947 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994324 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 23040420 # Number of tag accesses -system.l2c.tags.data_accesses 23040420 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 22272 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 6564 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 949144 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 22723 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5189 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 959680 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1965572 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 575172 # number of Writeback hits -system.l2c.Writeback_hits::total 575172 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.inst 954 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.inst 1026 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1980 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.inst 203 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.inst 94 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 297 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.inst 58656 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.inst 50708 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109364 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 22272 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 6564 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 1007800 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 22723 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5189 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 1010388 # number of demand (read+write) hits -system.l2c.demand_hits::total 2074936 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 22272 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 6564 # number of overall hits -system.l2c.overall_hits::cpu0.inst 1007800 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 22723 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5189 # number of overall hits -system.l2c.overall_hits::cpu1.inst 1010388 # number of overall hits -system.l2c.overall_hits::total 2074936 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 6 # number of ReadReq misses +system.l2c.tags.occ_blocks::writebacks 8088.192516 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.706191 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 1.029154 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2502.443827 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 29448.913538 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.609197 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.004438 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2039.532288 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13124.136592 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.123416 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000057 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.038184 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.449355 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000086 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.031121 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.200258 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.842492 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 53217 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 11430 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 151 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4758 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 48307 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 265 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 1757 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 9394 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.812027 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000137 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.174408 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5122526 # Number of tag accesses +system.l2c.tags.data_accesses 5122526 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 183 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 37 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 15214 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 88074 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 233 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 50 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 19471 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 76181 # number of ReadReq hits +system.l2c.ReadReq_hits::total 199443 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 215065 # number of Writeback hits +system.l2c.Writeback_hits::total 215065 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.inst 3153 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.inst 2020 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 5173 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.inst 94 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.inst 213 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 307 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.inst 2198 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.inst 2398 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 4596 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 183 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 37 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 17412 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 88074 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 233 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 50 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 21869 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 76181 # number of demand (read+write) hits +system.l2c.demand_hits::total 204039 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 183 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 37 # number of overall hits +system.l2c.overall_hits::cpu0.inst 17412 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 88074 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 233 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 50 # number of overall hits +system.l2c.overall_hits::cpu1.inst 21869 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 76181 # number of overall hits +system.l2c.overall_hits::total 204039 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 5 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 16107 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 9 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 9802 # number of ReadReq misses -system.l2c.ReadReq_misses::total 25926 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.inst 4879 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.inst 4062 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8941 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.inst 695 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.inst 300 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 995 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.inst 92450 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.inst 47410 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 139860 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 6 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu0.inst 4198 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 78315 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 10 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 3275 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 80672 # number of ReadReq misses +system.l2c.ReadReq_misses::total 166478 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.inst 7866 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.inst 5570 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 13436 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.inst 1047 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.inst 1097 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2144 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.inst 3980 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.inst 4567 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 8547 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 5 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 108557 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 9 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 57212 # number of demand (read+write) misses -system.l2c.demand_misses::total 165786 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 6 # number of overall misses +system.l2c.demand_misses::cpu0.inst 8178 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 78315 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 10 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 7842 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 80672 # number of demand (read+write) misses +system.l2c.demand_misses::total 175025 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 5 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 108557 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 9 # number of overall misses -system.l2c.overall_misses::cpu1.inst 57212 # number of overall misses -system.l2c.overall_misses::total 165786 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 592000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 1134045250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 716250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 732959500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1868462500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.inst 8149146 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.inst 13619415 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 21768561 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 695470 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 2181906 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 2877376 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.inst 6400503611 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.inst 3385304039 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9785807650 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 592000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 149500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 7534548861 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 716250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 4118263539 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 11654270150 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 592000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 149500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 7534548861 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 716250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 4118263539 # number of overall miss cycles -system.l2c.overall_miss_latency::total 11654270150 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 22278 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 6566 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 965251 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 22732 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 5189 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 969482 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1991498 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 575172 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 575172 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.inst 5833 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.inst 5088 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 10921 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.inst 898 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.inst 394 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1292 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.inst 151106 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.inst 98118 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 249224 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 22278 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 6566 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 1116357 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 22732 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 5189 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 1067600 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2240722 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 22278 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 6566 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 1116357 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 22732 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 5189 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 1067600 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2240722 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000269 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000305 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.016687 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000396 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010111 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.013018 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.836448 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.798349 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.818698 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.773942 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.761421 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.770124 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.inst 0.611822 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.inst 0.483194 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.561182 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000269 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000305 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.097242 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000396 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.053589 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.073988 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000269 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000305 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.097242 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000396 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.053589 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.073988 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 98666.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70406.981437 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79583.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74776.525199 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 72069.061946 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 1670.249231 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 3352.884047 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2434.689744 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 1000.676259 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 7273.020000 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 2891.835176 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 69232.056366 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 71404.852120 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 69968.594666 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 98666.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 69406.384305 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79583.333333 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 71982.513092 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 70297.070621 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 98666.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 69406.384305 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79583.333333 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 71982.513092 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 70297.070621 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.overall_misses::cpu0.inst 8178 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 78315 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 10 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu1.inst 7842 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 80672 # number of overall misses +system.l2c.overall_misses::total 175025 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 332000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 150000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 326103000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 7093548438 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 790750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 142500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 265072000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 8784856390 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 16470995078 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.inst 13809412 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.inst 6376729 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 20186141 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 656474 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 4281316 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 4937790 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.inst 283206167 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.inst 338006954 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 621213121 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 332000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 150000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 609309167 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 7093548438 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 790750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 142500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 603078954 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 8784856390 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 17092208199 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 332000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 150000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 609309167 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 7093548438 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 790750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 142500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 603078954 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 8784856390 # number of overall miss cycles +system.l2c.overall_miss_latency::total 17092208199 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 188 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 39 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 19412 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 166389 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 243 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 51 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 22746 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 156853 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 365921 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 215065 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 215065 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.inst 11019 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.inst 7590 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18609 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.inst 1141 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.inst 1310 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2451 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.inst 6178 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.inst 6965 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 13143 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 188 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 39 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 25590 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 166389 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 243 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 51 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 29711 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 156853 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 379064 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 188 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 39 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 25590 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 166389 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 243 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 51 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 29711 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 156853 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 379064 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.026596 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.051282 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.216258 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.470674 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.041152 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.019608 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.143981 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.514316 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.454956 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.713858 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.733860 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.722016 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.917616 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.837405 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.874745 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.inst 0.644221 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.inst 0.655707 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.650308 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.026596 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.051282 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.319578 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.470674 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.041152 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.019608 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.263943 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.514316 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.461729 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.026596 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.051282 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.319578 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.470674 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.041152 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.019608 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.263943 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.514316 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.461729 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 66400 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 77680.562172 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 90577.136411 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79075 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 142500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 80938.015267 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 108895.978654 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 98937.968248 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 1755.582507 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 1144.834650 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1502.392155 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 627.004776 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 3902.749316 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 2303.073694 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 71157.328392 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 74010.719072 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 72682.007839 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 66400 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 74505.889826 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 90577.136411 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79075 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 142500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 76903.717674 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 108895.978654 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 97655.810307 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 66400 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 74505.889826 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 90577.136411 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79075 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 142500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 76903.717674 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 108895.978654 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 97655.810307 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 174 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 5 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 34.800000 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 66893 # number of writebacks -system.l2c.writebacks::total 66893 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 49 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 22 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 49 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 22 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 49 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 22 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 71 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 6 # number of ReadReq MSHR misses +system.l2c.writebacks::writebacks 67795 # number of writebacks +system.l2c.writebacks::total 67795 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 5 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 16058 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 9 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 9780 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 25855 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.inst 4879 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.inst 4062 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 8941 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 695 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 300 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 995 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.inst 92450 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.inst 47410 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 139860 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 6 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 4198 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 78315 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 10 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 3274 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 80672 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 166477 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.inst 7866 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.inst 5570 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 13436 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 1047 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 1097 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 2144 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.inst 3980 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.inst 4567 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 8547 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 5 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 108508 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 9 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 57190 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 165715 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 6 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 8178 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 78315 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 10 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 7841 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 80672 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 175024 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 5 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 108508 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 9 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 57190 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 165715 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 518500 # number of ReadReq MSHR miss cycles +system.l2c.overall_mshr_misses::cpu0.inst 8178 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 78315 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 10 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 7841 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 80672 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 175024 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 270000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 929504000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 603750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 609332000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1540083250 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 48881350 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 40684546 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 89565896 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 6993689 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 3002299 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 9995988 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 5227989883 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 2775821957 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8003811840 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 518500 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 273844500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 6123836438 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 666250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 130500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 224380000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 7789791392 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 14413044080 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 79216804 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 56126525 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 135343329 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 10623534 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 10994091 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 21617625 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 233127823 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 280625546 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 513753369 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 270000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 6157493883 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 603750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 3385153957 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 9543895090 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 518500 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 506972323 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 6123836438 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 666250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 130500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 505005546 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 7789791392 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 14926797449 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 270000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 6157493883 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 603750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 3385153957 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 9543895090 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 156449029487 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10979297747 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167428327234 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 1364347483 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 15414886347 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 16779233830 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 157813376970 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 26394184094 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 184207561064 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000269 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000305 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016636 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000396 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010088 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.012983 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.836448 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.798349 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.818698 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.773942 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.761421 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.770124 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.611822 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.483194 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.561182 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000269 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000305 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.097198 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000396 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.053569 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.073956 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000269 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000305 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.097198 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000396 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.053569 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.073956 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 86416.666667 # average ReadReq mshr miss latency +system.l2c.overall_mshr_miss_latency::cpu0.inst 506972323 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 6123836438 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 666250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 130500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 505005546 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 7789791392 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 14926797449 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 12572348996 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 155062093246 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167634442242 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 1125655500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 15721437217 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 16847092717 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 13698004496 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 170783530463 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 184481534959 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.026596 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.051282 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.216258 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470674 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.041152 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.143937 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.514316 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.454953 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.713858 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.733860 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.722016 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.917616 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.837405 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.874745 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.644221 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.655707 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.650308 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.026596 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.051282 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.319578 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470674 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.041152 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.263909 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.514316 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.461727 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.026596 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.051282 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.319578 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470674 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.041152 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.263909 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.514316 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.461727 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 54000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57884.169884 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62303.885481 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 59566.167086 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10018.723099 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10015.890202 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10017.436081 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10062.861871 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10007.663333 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10046.219095 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 56549.376777 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 58549.292491 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 57227.311883 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 86416.666667 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 65232.134350 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78194.936321 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66625 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 130500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 68533.903482 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96561.277668 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 86576.788866 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10070.786168 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10076.575404 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10073.186142 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10146.641834 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10021.960802 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10082.847481 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 58574.829899 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61446.364353 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 60109.204282 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 54000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56746.911592 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59191.361374 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 57592.222128 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 86416.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61992.213622 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78194.936321 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66625 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64405.757684 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96561.277668 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 85284.289292 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 54000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56746.911592 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59191.361374 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 57592.222128 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61992.213622 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78194.936321 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66625 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64405.757684 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96561.277668 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 85284.289292 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -701,67 +824,53 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 163445997 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 3265310 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 3265309 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 767823 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 767823 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 575172 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 32693 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 17526 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 50219 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 260531 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 260531 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1555911 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3285118 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 16087 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52607 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1583939 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2567940 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 13476 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 53641 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 9128719 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 49766528 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 43750900 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26264 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 89112 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 50661248 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 38001760 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 20756 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 90928 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 182407496 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 182407496 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4820708 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5144551012 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3505001405 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2792622052 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 9525491 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30330496 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 3566573438 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 1934335367 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer8.occupancy 8290992 # Layer occupancy (ticks) -system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer9.occupancy 30912744 # Layer occupancy (ticks) -system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 46024799 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7474816 # Transaction distribution -system.iobus.trans_dist::ReadResp 7474816 # Transaction distribution -system.iobus.trans_dist::WriteReq 7966 # Transaction distribution -system.iobus.trans_dist::WriteResp 7966 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30566 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8038 # Packet count per connected master and slave (bytes) +system.toL2Bus.trans_dist::ReadReq 1655769 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1655769 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 768873 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 768873 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 215065 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 60425 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 22592 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 83017 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 22828 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 22828 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 802487 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4302639 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5105126 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 20032432 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 23601176 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 43633608 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 171019 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 786212 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 786212 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 786212 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2618569936 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 1234710374 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 2607103376 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 16519576 # Transaction distribution +system.iobus.trans_dist::ReadResp 16519576 # Transaction distribution +system.iobus.trans_dist::WriteReq 8084 # Transaction distribution +system.iobus.trans_dist::WriteResp 8084 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8928 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 732 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 498 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 738 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -778,54 +887,53 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382652 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12582912 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 12582912 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 14965564 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40335 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16076 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1464 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 273 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2389988 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 50331648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 50331648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 52721636 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 52721636 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21429000 # Layer occupancy (ticks) +system.iobus.pkt_count_system.bridge.master::total 2384472 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 33055320 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40715 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17856 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 393 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 2392888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 125076280 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 21715000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4025000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4470000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 372000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 299000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 441000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) @@ -856,21 +964,21 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6291456000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374686000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 15862213002 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) -system.cpu0.branchPred.lookups 6670288 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4756995 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 639495 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4605007 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3289427 # Number of BTB hits +system.iobus.reqLayer26.occupancy 15335424000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2376388000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) +system.iobus.respLayer1.occupancy 38667942571 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) +system.cpu0.branchPred.lookups 7247667 # Number of BP lookups +system.cpu0.branchPred.condPredicted 5145194 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 425040 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4677323 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 3357189 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 71.431531 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 870926 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 69312 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 71.775864 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 942424 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 64273 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -894,25 +1002,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7193152 # DTB read hits -system.cpu0.dtb.read_misses 17493 # DTB read misses -system.cpu0.dtb.write_hits 6058571 # DTB write hits -system.cpu0.dtb.write_misses 1416 # DTB write misses +system.cpu0.dtb.read_hits 6449421 # DTB read hits +system.cpu0.dtb.read_misses 22629 # DTB read misses +system.cpu0.dtb.write_hits 5803237 # DTB write hits +system.cpu0.dtb.write_misses 1880 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1942 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1486 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 207 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1731 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1649 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 155 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 320 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7210645 # DTB read accesses -system.cpu0.dtb.write_accesses 6059987 # DTB write accesses +system.cpu0.dtb.perms_faults 268 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 6472050 # DTB read accesses +system.cpu0.dtb.write_accesses 5805117 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 13251723 # DTB hits -system.cpu0.dtb.misses 18909 # DTB misses -system.cpu0.dtb.accesses 13270632 # DTB accesses +system.cpu0.dtb.hits 12252658 # DTB hits +system.cpu0.dtb.misses 24509 # DTB misses +system.cpu0.dtb.accesses 12277167 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -934,8 +1042,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 12268451 # ITB inst hits -system.cpu0.itb.inst_misses 4809 # ITB inst misses +system.cpu0.itb.inst_hits 13306402 # ITB inst hits +system.cpu0.itb.inst_misses 3981 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -944,82 +1052,83 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1294 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1196 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 2809 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 3606 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 12273260 # ITB inst accesses -system.cpu0.itb.hits 12268451 # DTB hits -system.cpu0.itb.misses 4809 # DTB misses -system.cpu0.itb.accesses 12273260 # DTB accesses -system.cpu0.numCycles 431172708 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 13310383 # ITB inst accesses +system.cpu0.itb.hits 13306402 # DTB hits +system.cpu0.itb.misses 3981 # DTB misses +system.cpu0.itb.accesses 13310383 # DTB accesses +system.cpu0.numCycles 86779776 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29878954 # Number of instructions committed -system.cpu0.committedOps 36403873 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 1704985 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 39450 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 1859905219 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 14.430649 # CPI: cycles per instruction -system.cpu0.ipc 0.069297 # IPC: instructions per cycle +system.cpu0.committedInsts 29469177 # Number of instructions committed +system.cpu0.committedOps 35692469 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 1968048 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 41085 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5234632408 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.944764 # CPI: cycles per instruction +system.cpu0.ipc 0.339586 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 50317 # number of quiesce instructions executed -system.cpu0.tickCycles 351703818 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 79468890 # Total number of cycles that the object has spent stopped -system.cpu0.icache.tags.replacements 775463 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.771777 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 11489502 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 775975 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 14.806536 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10202297000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 510.771777 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.997601 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997601 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 47499 # number of quiesce instructions executed +system.cpu0.tickCycles 68210329 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 18569447 # Total number of cycles that the object has spent stopped +system.cpu0.icache.tags.replacements 669895 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.780265 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 12632215 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 670407 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 18.842606 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6077782000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.780265 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999571 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999571 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 507 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 216 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 124 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 13041458 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 13041458 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 11489502 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 11489502 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 11489502 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 11489502 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 11489502 # number of overall hits -system.cpu0.icache.overall_hits::total 11489502 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 775978 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 775978 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 775978 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 775978 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 775978 # number of overall misses -system.cpu0.icache.overall_misses::total 775978 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10689826155 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10689826155 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10689826155 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10689826155 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10689826155 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10689826155 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 12265480 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 12265480 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 12265480 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 12265480 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 12265480 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 12265480 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.063265 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.063265 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.063265 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.063265 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.063265 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.063265 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13775.939724 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13775.939724 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13775.939724 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13775.939724 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13775.939724 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13775.939724 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 27275662 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 27275662 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 12632215 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 12632215 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 12632215 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 12632215 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 12632215 # number of overall hits +system.cpu0.icache.overall_hits::total 12632215 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 670411 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 670411 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 670411 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 670411 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 670411 # number of overall misses +system.cpu0.icache.overall_misses::total 670411 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5588337897 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5588337897 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5588337897 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5588337897 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5588337897 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5588337897 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 13302626 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 13302626 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 13302626 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 13302626 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 13302626 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 13302626 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050397 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.050397 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050397 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.050397 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050397 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.050397 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8335.689446 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8335.689446 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8335.689446 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8335.689446 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8335.689446 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8335.689446 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1028,125 +1137,465 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 775978 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 775978 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 775978 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 775978 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 775978 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 775978 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9133730845 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9133730845 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9133730845 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9133730845 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9133730845 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9133730845 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 171407250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 171407250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 171407250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 171407250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.063265 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.063265 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.063265 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.063265 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.063265 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.063265 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11770.605410 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11770.605410 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11770.605410 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11770.605410 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11770.605410 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11770.605410 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 670411 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 670411 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 670411 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 670411 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 670411 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 670411 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4581839103 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4581839103 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4581839103 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4581839103 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4581839103 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4581839103 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 215199250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 215199250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 215199250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 215199250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050397 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050397 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050397 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.050397 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050397 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.050397 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6834.373396 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6834.373396 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6834.373396 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 6834.373396 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6834.373396 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 6834.373396 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 331184 # number of replacements -system.cpu0.dcache.tags.tagsinuse 495.308279 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11419092 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 331547 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 34.441850 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 235572250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.inst 495.308279 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.967399 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.967399 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 363 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 363 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.708984 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 48281639 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 48281639 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.inst 5587990 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5587990 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.inst 5501455 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5501455 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 152609 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 152609 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 153662 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 153662 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.inst 11089445 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11089445 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.inst 11089445 # number of overall hits -system.cpu0.dcache.overall_hits::total 11089445 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.inst 255115 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 255115 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.inst 311930 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 311930 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 8548 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8548 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 7439 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7439 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.inst 567045 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 567045 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.inst 567045 # number of overall misses -system.cpu0.dcache.overall_misses::total 567045 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 3832963977 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 3832963977 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 15354005377 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 15354005377 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 89150250 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 89150250 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 47371188 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 47371188 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.inst 19186969354 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 19186969354 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.inst 19186969354 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 19186969354 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.inst 5843105 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 5843105 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.inst 5813385 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5813385 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 161157 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 161157 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 161101 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 161101 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.inst 11656490 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11656490 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.inst 11656490 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11656490 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.043661 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.043661 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.053657 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.053657 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.053041 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053041 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.046176 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.046176 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.048646 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.048646 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.048646 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.048646 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 15024.455547 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15024.455547 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 49222.599227 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 49222.599227 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 10429.369443 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10429.369443 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 6367.951069 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6367.951069 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 33836.766666 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33836.766666 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 33836.766666 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33836.766666 # average overall miss latency +system.cpu0.toL2Bus.trans_dist::ReadReq 1297449 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1098949 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 10915 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 10915 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 277394 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 309853 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 48681 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 23393 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 54656 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 145161 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 136933 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1345495 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 1384854 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13521 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 67392 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 2811262 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 43053120 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 45712112 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 22348 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 121316 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 88908896 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 663093 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 2014813 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.294791 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.455949 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 1420865 70.52% 70.52% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 593948 29.48% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 2014813 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 1042501632 # Layer occupancy (ticks) +system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.snoopLayer0.occupancy 66915000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer0.occupancy 1010138647 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer1.occupancy 706064108 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer2.occupancy 7935497 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer3.occupancy 37067990 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 6505286 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 197873 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6075585 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 2087 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2097 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 227641 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 451994 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.l2cache.tags.replacements 185568 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16045.943959 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1211197 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 201780 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.002562 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 5120960000 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 4785.288649 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 15.661304 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.175022 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2150.935803 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9093.883182 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.292071 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000956 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000011 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.131283 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.555047 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.979367 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8308 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 18 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7886 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 36 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 61 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 933 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5734 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1544 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1527 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5465 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 648 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.507080 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.001099 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.481323 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 22965812 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 22965812 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 29822 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5414 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 885726 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 920962 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 277394 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 277394 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 1852 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 1852 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 771 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 771 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 107990 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 107990 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 29822 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 5414 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 993716 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1028952 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 29822 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 5414 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 993716 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1028952 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 507 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 173 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 49350 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 50030 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 18889 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 18889 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 10120 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 10120 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 23685 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 23685 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 507 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 173 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 73035 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 73715 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 507 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 173 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 73035 # number of overall misses +system.cpu0.l2cache.overall_misses::total 73715 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 10873500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3613500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 1326942681 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 1341429681 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 312233020 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 312233020 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 200699599 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 200699599 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 1269500 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1269500 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 847496588 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 847496588 # number of ReadExReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 10873500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3613500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2174439269 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 2188926269 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 10873500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3613500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2174439269 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 2188926269 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 30329 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5587 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 935076 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 970992 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 277394 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 277394 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 20741 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 20741 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 10891 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 10891 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 131675 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 131675 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 30329 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5587 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1066751 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1102667 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 30329 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5587 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1066751 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 1102667 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.016717 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.030965 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.052776 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.051525 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.910708 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.910708 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.929208 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.929208 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.179875 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.179875 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.016717 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.030965 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.068465 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.066852 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.016717 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.030965 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.068465 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.066852 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 21446.745562 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 20887.283237 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 26888.402857 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26812.506116 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 16529.886177 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 16529.886177 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19831.976186 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19831.976186 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst inf # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 35781.996538 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 35781.996538 # average ReadExReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 21446.745562 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 20887.283237 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 29772.564784 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 29694.448470 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 21446.745562 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 20887.283237 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 29772.564784 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 29694.448470 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 1346 # number of cycles access was blocked +system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 34 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 39.588235 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.l2cache.fast_writes 0 # number of fast writes performed +system.cpu0.l2cache.cache_copies 0 # number of cache copies performed +system.cpu0.l2cache.writebacks::writebacks 114944 # number of writebacks +system.cpu0.l2cache.writebacks::total 114944 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 2945 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 2945 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 748 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 748 # number of ReadExReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 3693 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 3693 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 3693 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 3693 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 507 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 173 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 46405 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 47085 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 227640 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 227640 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 18889 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 18889 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 10120 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 10120 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 22937 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 22937 # number of ReadExReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 507 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 173 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 69342 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 70022 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 507 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 173 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 69342 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 227640 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 297662 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 7324500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2402500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 949940475 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 959667475 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 8587835748 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 8587835748 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 341053600 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 341053600 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 145849953 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 145849953 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 1059500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1059500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 592786901 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 592786901 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 7324500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2402500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 1542727376 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 1552454376 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 7324500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2402500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 1542727376 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 8587835748 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 10140290124 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 14160332496 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 14160332496 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 1312896000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 1312896000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 15473228496 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15473228496 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.016717 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.030965 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.049627 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.048492 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.910708 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.910708 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.929208 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.929208 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.174194 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.174194 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.016717 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.030965 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.065003 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.063502 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.016717 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.030965 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.065003 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.269947 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14446.745562 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 13887.283237 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 20470.649176 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20381.596581 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 37725.512862 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 37725.512862 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 18055.672614 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18055.672614 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 14412.050692 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14412.050692 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst inf # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 25844.133976 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 25844.133976 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14446.745562 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 13887.283237 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22248.094604 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 22170.951644 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14446.745562 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 13887.283237 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22248.094604 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 37725.512862 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34066.458345 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.tags.replacements 363620 # number of replacements +system.cpu0.dcache.tags.tagsinuse 473.092728 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11412864 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 364132 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 31.342656 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 243086500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.inst 473.092728 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.924009 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.924009 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 24359055 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 24359055 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.inst 5804369 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5804369 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.inst 5275244 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5275244 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 147463 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 147463 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 146615 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 146615 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.inst 11079613 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11079613 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.inst 11079613 # number of overall hits +system.cpu0.dcache.overall_hits::total 11079613 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.inst 309599 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 309599 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.inst 276951 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 276951 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 10168 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 10168 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 10891 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 10891 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.inst 586550 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 586550 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.inst 586550 # number of overall misses +system.cpu0.dcache.overall_misses::total 586550 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 3701357617 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3701357617 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 4193199790 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 4193199790 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 166675501 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 166675501 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 254636964 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 254636964 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 1359500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1359500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.inst 7894557407 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 7894557407 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.inst 7894557407 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 7894557407 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.inst 6113968 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6113968 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.inst 5552195 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5552195 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 157631 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 157631 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 157506 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 157506 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.inst 11666163 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11666163 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.inst 11666163 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11666163 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.050638 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.050638 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.049881 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.049881 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.064505 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064505 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.069147 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.069147 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.050278 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.050278 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.050278 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.050278 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 11955.328076 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 11955.328076 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15140.583677 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15140.583677 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16392.161782 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16392.161782 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 23380.494353 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23380.494353 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13459.308511 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 13459.308511 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13459.308511 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13459.308511 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1155,72 +1604,76 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 307170 # number of writebacks -system.cpu0.dcache.writebacks::total 307170 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 50178 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 50178 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 144238 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 144238 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 22 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.inst 194416 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 194416 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.inst 194416 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 194416 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 204937 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 204937 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 167692 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 167692 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 8526 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8526 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 7439 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7439 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.inst 372629 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 372629 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.inst 372629 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 372629 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 2523643558 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2523643558 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 7293302576 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7293302576 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 71695750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 71695750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 32490812 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32490812 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9816946134 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9816946134 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9816946134 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 9816946134 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 170796523752 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 170796523752 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 1513122000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1513122000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 172309645752 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 172309645752 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.035073 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035073 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.028846 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.028846 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.052905 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.052905 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.046176 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.046176 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.031968 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.031968 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.031968 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031968 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12314.240757 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12314.240757 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 43492.251127 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43492.251127 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 8409.072250 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8409.072250 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 4367.631671 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4367.631671 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 26345.094273 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26345.094273 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 26345.094273 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26345.094273 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 277395 # number of writebacks +system.cpu0.dcache.writebacks::total 277395 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 54934 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 54934 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 124546 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 124546 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 74 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 74 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.inst 179480 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 179480 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.inst 179480 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 179480 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 254665 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 254665 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 152405 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 152405 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 10094 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 10094 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 10891 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 10891 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.inst 407070 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 407070 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.inst 407070 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 407070 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 2527058296 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2527058296 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 2131958823 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2131958823 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 145779499 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145779499 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 231881036 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 231881036 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 1299500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1299500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 4659017119 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 4659017119 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 4659017119 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 4659017119 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 14650509239 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 14650509239 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 1394876998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1394876998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 16045386237 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 16045386237 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.041653 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041653 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.027450 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027450 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.064036 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064036 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.069147 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.069147 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.034893 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.034893 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.034893 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.034893 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9923.068722 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 9923.068722 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 13988.772173 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13988.772173 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14442.193283 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14442.193283 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 21291.069323 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21291.069323 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11445.248038 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11445.248038 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11445.248038 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11445.248038 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency @@ -1228,15 +1681,15 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 6159330 # Number of BP lookups -system.cpu1.branchPred.condPredicted 4534606 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 426160 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 3924244 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3043762 # Number of BTB hits +system.cpu1.branchPred.lookups 7015971 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5101339 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 682515 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 5021553 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3808301 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 77.563016 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 713205 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 64399 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 75.839108 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 855690 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 72942 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1260,25 +1713,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 6763605 # DTB read hits -system.cpu1.dtb.read_misses 17087 # DTB read misses -system.cpu1.dtb.write_hits 5563764 # DTB write hits -system.cpu1.dtb.write_misses 2456 # DTB write misses +system.cpu1.dtb.read_hits 7897430 # DTB read hits +system.cpu1.dtb.read_misses 21135 # DTB read misses +system.cpu1.dtb.write_hits 6047519 # DTB write hits +system.cpu1.dtb.write_misses 2176 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1713 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1918 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 230 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1928 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 3376 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 148 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 260 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 6780692 # DTB read accesses -system.cpu1.dtb.write_accesses 5566220 # DTB write accesses +system.cpu1.dtb.perms_faults 328 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 7918565 # DTB read accesses +system.cpu1.dtb.write_accesses 6049695 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 12327369 # DTB hits -system.cpu1.dtb.misses 19543 # DTB misses -system.cpu1.dtb.accesses 12346912 # DTB accesses +system.cpu1.dtb.hits 13944949 # DTB hits +system.cpu1.dtb.misses 23311 # DTB misses +system.cpu1.dtb.accesses 13968260 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1300,8 +1753,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 11206823 # ITB inst hits -system.cpu1.itb.inst_misses 4156 # ITB inst misses +system.cpu1.itb.inst_hits 14225149 # ITB inst hits +system.cpu1.itb.inst_misses 5020 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1310,84 +1763,81 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1190 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1294 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 2956 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 3363 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 11210979 # ITB inst accesses -system.cpu1.itb.hits 11206823 # DTB hits -system.cpu1.itb.misses 4156 # DTB misses -system.cpu1.itb.accesses 11210979 # DTB accesses -system.cpu1.numCycles 147611080 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 14230169 # ITB inst accesses +system.cpu1.itb.hits 14225149 # DTB hits +system.cpu1.itb.misses 5020 # DTB misses +system.cpu1.itb.accesses 14230169 # DTB accesses +system.cpu1.numCycles 502333604 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 31966977 # Number of instructions committed -system.cpu1.committedOps 38077351 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 1608279 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 39953 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 2144312243 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 4.617611 # CPI: cycles per instruction -system.cpu1.ipc 0.216562 # IPC: instructions per cycle +system.cpu1.committedInsts 33559332 # Number of instructions committed +system.cpu1.committedOps 40204034 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 2027525 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 40422 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 4816582490 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 14.968522 # CPI: cycles per instruction +system.cpu1.ipc 0.066807 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 40481 # number of quiesce instructions executed -system.cpu1.tickCycles 117794272 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 29816808 # Total number of cycles that the object has spent stopped -system.cpu1.icache.tags.replacements 791766 # number of replacements -system.cpu1.icache.tags.tagsinuse 480.612166 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 10411414 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 792278 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 13.141112 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 82581306250 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.612166 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938696 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.938696 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 45430 # number of quiesce instructions executed +system.cpu1.tickCycles 438569606 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 63763998 # Total number of cycles that the object has spent stopped +system.cpu1.icache.tags.replacements 776883 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.132911 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 13444222 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 777395 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 17.293939 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 68940011500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.132911 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974869 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.974869 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 186 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 11995971 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 11995971 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 10411414 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 10411414 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 10411414 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 10411414 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 10411414 # number of overall hits -system.cpu1.icache.overall_hits::total 10411414 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 792279 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 792279 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 792279 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 792279 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 792279 # number of overall misses -system.cpu1.icache.overall_misses::total 792279 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10606605688 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 10606605688 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 10606605688 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 10606605688 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 10606605688 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 10606605688 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 11203693 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 11203693 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 11203693 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 11203693 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 11203693 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 11203693 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.070716 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.070716 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.070716 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.070716 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.070716 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.070716 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13387.462861 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13387.462861 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13387.462861 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13387.462861 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13387.462861 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13387.462861 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 29220629 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 29220629 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 13444222 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 13444222 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 13444222 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 13444222 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 13444222 # number of overall hits +system.cpu1.icache.overall_hits::total 13444222 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 777395 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 777395 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 777395 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 777395 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 777395 # number of overall misses +system.cpu1.icache.overall_misses::total 777395 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6473834509 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6473834509 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6473834509 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6473834509 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6473834509 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6473834509 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 14221617 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 14221617 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 14221617 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 14221617 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 14221617 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 14221617 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.054663 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.054663 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.054663 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.054663 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.054663 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.054663 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8327.599880 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8327.599880 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8327.599880 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8327.599880 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8327.599880 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8327.599880 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1396,128 +1846,468 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 792279 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 792279 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 792279 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 792279 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 792279 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 792279 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 9020137312 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 9020137312 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 9020137312 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 9020137312 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 9020137312 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 9020137312 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5771250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5771250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5771250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 5771250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.070716 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.070716 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.070716 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.070716 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.070716 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.070716 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11385.051619 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11385.051619 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11385.051619 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11385.051619 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11385.051619 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11385.051619 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 777395 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 777395 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 777395 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 777395 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 777395 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 777395 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5306001991 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5306001991 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5306001991 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5306001991 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5306001991 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5306001991 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7443500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7443500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7443500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 7443500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.054663 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.054663 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.054663 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.054663 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.054663 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.054663 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6825.361613 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6825.361613 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6825.361613 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 6825.361613 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6825.361613 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 6825.361613 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 300206 # number of replacements -system.cpu1.dcache.tags.tagsinuse 447.094079 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 10899911 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 300718 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 36.246287 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 76416861250 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.inst 447.094079 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.873231 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.873231 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 350 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 45736548 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 45736548 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.inst 6288103 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 6288103 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.inst 4421998 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4421998 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 78443 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 78443 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 79055 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 79055 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.inst 10710101 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 10710101 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.inst 10710101 # number of overall hits -system.cpu1.dcache.overall_hits::total 10710101 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.inst 241320 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 241320 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.inst 223635 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 223635 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 10750 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 10750 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 10087 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10087 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.inst 464955 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 464955 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.inst 464955 # number of overall misses -system.cpu1.dcache.overall_misses::total 464955 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 3586794993 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3586794993 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 8773828993 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 8773828993 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 90116500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 90116500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 50277799 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 50277799 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.inst 12360623986 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 12360623986 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.inst 12360623986 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 12360623986 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.inst 6529423 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 6529423 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.inst 4645633 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4645633 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 89193 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 89193 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 89142 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 89142 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.inst 11175056 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 11175056 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.inst 11175056 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 11175056 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.036959 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.036959 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.048139 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.048139 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.120525 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120525 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.113157 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113157 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.041607 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.041607 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.041607 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.041607 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14863.231365 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14863.231365 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 39232.807892 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 39232.807892 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 8382.930233 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8382.930233 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 4984.415485 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 4984.415485 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 26584.559766 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 26584.559766 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 26584.559766 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 26584.559766 # average overall miss latency +system.cpu1.toL2Bus.trans_dist::ReadReq 2372884 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 2161619 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 757958 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 757958 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 242023 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 269237 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 52848 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 23732 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 50462 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 31 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 145739 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 137938 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1554692 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 4766762 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17488 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 67601 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 6406543 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 49741696 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 44501144 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30140 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 121260 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 94394240 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 607829 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 2003123 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.277710 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.447870 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 1446836 72.23% 72.23% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 556287 27.77% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 2003123 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 2275243689 # Layer occupancy (ticks) +system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu1.toL2Bus.snoopLayer0.occupancy 46353997 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer0.occupancy 1167104009 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer1.occupancy 2025335762 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer2.occupancy 9955994 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer3.occupancy 37292239 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 6843055 # number of hwpf identified +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 163843 # number of hwpf that were already in mshr +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6478033 # number of hwpf that were already in the cache +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 2741 # number of hwpf that were already in the prefetch queue +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2015 # number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 196423 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 563857 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.l2cache.tags.replacements 179577 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15624.309787 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1195829 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 195022 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 6.131765 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 2581358397500 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 4477.438103 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 22.594175 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.081575 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2724.649779 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8398.546154 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.273281 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001379 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000066 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.166299 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.512607 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.953632 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9457 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5975 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2071 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1611 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 5775 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2329 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 929 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2717 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.577209 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.364685 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 23391503 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 23391503 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 29831 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7391 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 925413 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 962635 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 242023 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 242023 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1810 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 1810 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 1118 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 1118 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 112181 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 112181 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 29831 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7391 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 1037594 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 1074816 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 29831 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7391 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 1037594 # number of overall hits +system.cpu1.l2cache.overall_hits::total 1074816 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 484 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 144 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 61489 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 62117 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 18553 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 18553 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 12524 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 12524 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.inst 1 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 24216 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 24216 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 484 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 144 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 85705 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 86333 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 484 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 144 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 85705 # number of overall misses +system.cpu1.l2cache.overall_misses::total 86333 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10993750 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 3129500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 1532483424 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 1546606674 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 310148223 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 310148223 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 250854673 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 250854673 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 743500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 743500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 1014040211 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1014040211 # number of ReadExReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10993750 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 3129500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 2546523635 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 2560646885 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10993750 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 3129500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 2546523635 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 2560646885 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 30315 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7535 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 986902 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 1024752 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 242023 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 242023 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 20363 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 20363 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 13642 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 13642 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.inst 1 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 136397 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 136397 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 30315 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7535 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 1123299 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 1161149 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 30315 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7535 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 1123299 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 1161149 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.015966 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.019111 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.062305 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.060617 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.911113 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.911113 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.918047 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.918047 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.inst 1 # miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.177541 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.177541 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.015966 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.019111 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.076298 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.074351 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.015966 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.019111 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.076298 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.074351 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22714.359504 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 21732.638889 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 24922.887411 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24898.283465 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 16716.877217 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 16716.877217 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 20029.916401 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20029.916401 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst 743500 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 743500 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 41874.802238 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 41874.802238 # average ReadExReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22714.359504 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 21732.638889 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29712.661280 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 29660.117047 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22714.359504 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 21732.638889 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29712.661280 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 29660.117047 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 2162 # number of cycles access was blocked +system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 53 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 40.792453 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.l2cache.fast_writes 0 # number of fast writes performed +system.cpu1.l2cache.cache_copies 0 # number of cache copies performed +system.cpu1.l2cache.writebacks::writebacks 100121 # number of writebacks +system.cpu1.l2cache.writebacks::total 100121 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 3717 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 3717 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 1346 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 1346 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 5063 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 5063 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 5063 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 5063 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 484 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 144 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 57772 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 58400 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 196422 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 196422 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 18553 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 18553 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 12524 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 12524 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.inst 1 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 22870 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 22870 # number of ReadExReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 484 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 144 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 80642 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 81270 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 484 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 144 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 80642 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 196422 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 277692 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 7604250 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 2121500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 1060116241 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1069841991 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 10135528743 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 10135528743 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 305752523 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 305752523 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 178428901 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 178428901 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 582500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 582500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 637234022 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 637234022 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 7604250 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 2121500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1697350263 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 1707076013 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7604250 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 2121500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1697350263 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 10135528743 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 11842604756 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 174928342748 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 174928342748 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 28797063287 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 28797063287 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 203725406035 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 203725406035 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.015966 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.019111 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.058539 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.056989 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.911113 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.911113 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.918047 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.918047 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.inst 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.167672 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.167672 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.015966 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.019111 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.071790 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.069991 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.015966 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.019111 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.071790 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.239153 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15711.260331 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14732.638889 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18350.000710 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18319.212175 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 51600.781700 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 51600.781700 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 16479.950574 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16479.950574 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 14246.957921 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14246.957921 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst 582500 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 582500 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 27863.315348 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27863.315348 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15711.260331 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14732.638889 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21047.968342 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 21004.995853 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15711.260331 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14732.638889 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21047.968342 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 51600.781700 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42646.546375 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.tags.replacements 322636 # number of replacements +system.cpu1.dcache.tags.tagsinuse 491.144142 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 11399665 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 322979 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 35.295375 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 72461169500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.inst 491.144142 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.959266 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.959266 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 343 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.669922 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 24160845 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 24160845 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.inst 6375348 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 6375348 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.inst 4820943 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4820943 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 83445 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 83445 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 81578 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 81578 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.inst 11196291 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 11196291 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.inst 11196291 # number of overall hits +system.cpu1.dcache.overall_hits::total 11196291 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.inst 234523 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 234523 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.inst 286003 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 286003 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 11843 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11843 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 13643 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 13643 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.inst 520526 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 520526 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.inst 520526 # number of overall misses +system.cpu1.dcache.overall_misses::total 520526 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 3079569141 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3079569141 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 4582527620 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 4582527620 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 211610249 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 211610249 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 314496917 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 314496917 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 813000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 813000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.inst 7662096761 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 7662096761 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.inst 7662096761 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 7662096761 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.inst 6609871 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 6609871 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.inst 5106946 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5106946 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 95288 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 95288 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 95221 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 95221 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.inst 11716817 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 11716817 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.inst 11716817 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 11716817 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.035481 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035481 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.056003 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.056003 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.124286 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124286 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.143277 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.143277 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.044426 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.044426 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.044426 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044426 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 13131.203085 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13131.203085 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 16022.655776 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 16022.655776 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 17867.959892 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17867.959892 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23051.888661 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23051.888661 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 14719.911707 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14719.911707 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 14719.911707 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14719.911707 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1526,72 +2316,76 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 268002 # number of writebacks -system.cpu1.dcache.writebacks::total 268002 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 36395 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 36395 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 98109 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 98109 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst 34 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 34 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.inst 134504 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 134504 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.inst 134504 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 134504 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 204925 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 204925 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 125526 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 125526 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 10716 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 10716 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 10087 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10087 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.inst 330451 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 330451 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.inst 330451 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 330451 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2412502275 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2412502275 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 4153602004 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4153602004 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 68123500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 68123500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 30103201 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30103201 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 6566104279 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 6566104279 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 6566104279 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6566104279 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 11993503000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 11993503000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 24672579152 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 24672579152 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 36666082152 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 36666082152 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.031385 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.031385 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.027020 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027020 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.120144 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120144 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.113157 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.113157 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.029570 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.029570 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.029570 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.029570 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11772.610833 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11772.610833 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 33089.575100 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33089.575100 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 6357.176185 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6357.176185 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 2984.356201 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 2984.356201 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 19870.129850 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19870.129850 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 19870.129850 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19870.129850 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 242023 # number of writebacks +system.cpu1.dcache.writebacks::total 242023 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 36547 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 36547 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 129246 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 129246 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst 45 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 45 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.inst 165793 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 165793 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.inst 165793 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 165793 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 197976 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 197976 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 156757 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 156757 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 11798 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11798 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 13643 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 13643 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.inst 354733 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 354733 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.inst 354733 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 354733 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2204262298 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2204262298 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 2289972148 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2289972148 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 187457749 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 187457749 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 286173083 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 286173083 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 767000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 767000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4494234446 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4494234446 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4494234446 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4494234446 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 183748244745 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 183748244745 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 34481816713 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 34481816713 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 218230061458 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 218230061458 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.029952 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029952 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.030695 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030695 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.123814 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.123814 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.143277 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.143277 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.030276 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.030276 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.030276 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.030276 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11133.987443 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11133.987443 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 14608.420345 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14608.420345 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 15888.942956 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15888.942956 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 20975.817855 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20975.817855 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 12669.344115 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12669.344115 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 12669.344115 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12669.344115 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency @@ -1615,10 +2409,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 722335941002 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 722335941002 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 722335941002 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 722335941002 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1759208062571 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1759208062571 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1759208062571 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1759208062571 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 8849a7b1f..c758d0203 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.566439 # Number of seconds simulated -sim_ticks 2566439177500 # Number of ticks simulated -final_tick 2566439177500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.566404 # Number of seconds simulated +sim_ticks 2566404096500 # Number of ticks simulated +final_tick 2566404096500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109798 # Simulator instruction rate (inst/s) -host_op_rate 132178 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4650508258 # Simulator tick rate (ticks/s) -host_mem_usage 408644 # Number of bytes of host memory used -host_seconds 551.86 # Real time elapsed on the host -sim_insts 60593470 # Number of instructions simulated -sim_ops 72944147 # Number of ops (including micro ops) simulated +host_inst_rate 108919 # Simulator instruction rate (inst/s) +host_op_rate 131120 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4613194748 # Simulator tick rate (ticks/s) +host_mem_usage 411228 # Number of bytes of host memory used +host_seconds 556.32 # Real time elapsed on the host +sim_insts 60593541 # Number of instructions simulated +sim_ops 72944224 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.realview.nvmem.bytes_read::cpu.inst 256 # Number of bytes read from this memory @@ -26,119 +26,119 @@ system.realview.nvmem.bw_inst_read::total 100 # I system.realview.nvmem.bw_total::cpu.inst 100 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 100 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 1664 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10079960 # Number of bytes read from this memory -system.physmem.bytes_read::total 131191960 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1001344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1001344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3811328 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 10080024 # Number of bytes read from this memory +system.physmem.bytes_read::total 131192344 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1001408 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1001408 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3810496 # Number of bytes written to this memory system.physmem.bytes_written::cpu.inst 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6827400 # Number of bytes written to this memory +system.physmem.bytes_written::total 6826568 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 26 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 157525 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15296364 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59552 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 157526 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15296370 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59539 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.inst 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813570 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47190103 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 524 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813557 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47190748 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 648 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 3927605 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51118281 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 390169 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 390169 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1485065 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.inst 1175197 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2660262 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1485065 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47190103 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 524 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3927684 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51119130 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 390199 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 390199 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1484761 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.inst 1175213 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2659974 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1484761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47190748 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 648 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5102802 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53778543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15296364 # Number of read requests accepted -system.physmem.writeReqs 813570 # Number of write requests accepted -system.physmem.readBursts 15296364 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813570 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 978868736 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 98560 # Total number of bytes read from write queue -system.physmem.bytesWritten 6836224 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131191960 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6827400 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1540 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706728 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4670 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 955903 # Per bank write bursts -system.physmem.perBankRdBursts::1 955584 # Per bank write bursts +system.physmem.bw_total::cpu.inst 5102897 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53779104 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15296370 # Number of read requests accepted +system.physmem.writeReqs 813557 # Number of write requests accepted +system.physmem.readBursts 15296370 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813557 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 978862336 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 105344 # Total number of bytes read from write queue +system.physmem.bytesWritten 6837568 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131192344 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6826568 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1646 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706692 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4678 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 955907 # Per bank write bursts +system.physmem.perBankRdBursts::1 955585 # Per bank write bursts system.physmem.perBankRdBursts::2 955711 # Per bank write bursts -system.physmem.perBankRdBursts::3 955912 # Per bank write bursts -system.physmem.perBankRdBursts::4 957606 # Per bank write bursts -system.physmem.perBankRdBursts::5 955733 # Per bank write bursts -system.physmem.perBankRdBursts::6 955604 # Per bank write bursts -system.physmem.perBankRdBursts::7 955438 # Per bank write bursts -system.physmem.perBankRdBursts::8 956293 # Per bank write bursts -system.physmem.perBankRdBursts::9 955954 # Per bank write bursts -system.physmem.perBankRdBursts::10 955536 # Per bank write bursts -system.physmem.perBankRdBursts::11 955097 # Per bank write bursts -system.physmem.perBankRdBursts::12 956286 # Per bank write bursts -system.physmem.perBankRdBursts::13 955995 # Per bank write bursts -system.physmem.perBankRdBursts::14 956150 # Per bank write bursts -system.physmem.perBankRdBursts::15 956022 # Per bank write bursts -system.physmem.perBankWrBursts::0 6610 # Per bank write bursts -system.physmem.perBankWrBursts::1 6419 # Per bank write bursts -system.physmem.perBankWrBursts::2 6537 # Per bank write bursts -system.physmem.perBankWrBursts::3 6577 # Per bank write bursts -system.physmem.perBankWrBursts::4 6482 # Per bank write bursts -system.physmem.perBankWrBursts::5 6744 # Per bank write bursts -system.physmem.perBankWrBursts::6 6779 # Per bank write bursts -system.physmem.perBankWrBursts::7 6682 # Per bank write bursts -system.physmem.perBankWrBursts::8 7031 # Per bank write bursts -system.physmem.perBankWrBursts::9 6794 # Per bank write bursts -system.physmem.perBankWrBursts::10 6476 # Per bank write bursts -system.physmem.perBankWrBursts::11 6093 # Per bank write bursts -system.physmem.perBankWrBursts::12 7096 # Per bank write bursts -system.physmem.perBankWrBursts::13 6664 # Per bank write bursts -system.physmem.perBankWrBursts::14 6987 # Per bank write bursts -system.physmem.perBankWrBursts::15 6845 # Per bank write bursts +system.physmem.perBankRdBursts::3 955918 # Per bank write bursts +system.physmem.perBankRdBursts::4 957666 # Per bank write bursts +system.physmem.perBankRdBursts::5 955713 # Per bank write bursts +system.physmem.perBankRdBursts::6 955586 # Per bank write bursts +system.physmem.perBankRdBursts::7 955417 # Per bank write bursts +system.physmem.perBankRdBursts::8 956298 # Per bank write bursts +system.physmem.perBankRdBursts::9 955963 # Per bank write bursts +system.physmem.perBankRdBursts::10 955537 # Per bank write bursts +system.physmem.perBankRdBursts::11 955091 # Per bank write bursts +system.physmem.perBankRdBursts::12 956282 # Per bank write bursts +system.physmem.perBankRdBursts::13 955994 # Per bank write bursts +system.physmem.perBankRdBursts::14 956147 # Per bank write bursts +system.physmem.perBankRdBursts::15 955909 # Per bank write bursts +system.physmem.perBankWrBursts::0 6629 # Per bank write bursts +system.physmem.perBankWrBursts::1 6411 # Per bank write bursts +system.physmem.perBankWrBursts::2 6529 # Per bank write bursts +system.physmem.perBankWrBursts::3 6576 # Per bank write bursts +system.physmem.perBankWrBursts::4 6489 # Per bank write bursts +system.physmem.perBankWrBursts::5 6741 # Per bank write bursts +system.physmem.perBankWrBursts::6 6778 # Per bank write bursts +system.physmem.perBankWrBursts::7 6680 # Per bank write bursts +system.physmem.perBankWrBursts::8 7055 # Per bank write bursts +system.physmem.perBankWrBursts::9 6798 # Per bank write bursts +system.physmem.perBankWrBursts::10 6471 # Per bank write bursts +system.physmem.perBankWrBursts::11 6090 # Per bank write bursts +system.physmem.perBankWrBursts::12 7091 # Per bank write bursts +system.physmem.perBankWrBursts::13 6663 # Per bank write bursts +system.physmem.perBankWrBursts::14 6989 # Per bank write bursts +system.physmem.perBankWrBursts::15 6847 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2566437420000 # Total gap between requests +system.physmem.totGap 2566402308000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 18 # Read request sizes (log2) system.physmem.readPktSize::3 15138826 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 157520 # Read request sizes (log2) +system.physmem.readPktSize::6 157526 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59552 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1111382 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 958419 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 963594 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1074014 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 973771 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1037292 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2691805 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2600171 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3390697 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 128159 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 109522 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 101552 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 98177 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19262 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18514 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 197 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59539 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1111407 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 958360 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 963566 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1076065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 974438 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1039000 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2689873 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2594671 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3384839 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 130586 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 112191 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 103349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 100054 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19345 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18516 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18281 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 177 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -167,25 +167,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6205 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 6203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -216,44 +216,47 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1014534 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 971.583959 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 905.812030 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 204.103928 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21965 2.17% 2.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22634 2.23% 4.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8771 0.86% 5.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2477 0.24% 5.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2600 0.26% 5.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1707 0.17% 5.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8766 0.86% 6.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1031 0.10% 6.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 944583 93.11% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1014534 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6199 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2467.302629 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 115861.516346 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 6194 99.92% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 2 0.03% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6199 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6199 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.231166 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.203067 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.975146 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2381 38.41% 38.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 18 0.29% 38.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3787 61.09% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 12 0.19% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6199 # Writes before turning the bus around for reads -system.physmem.totQLat 394563558000 # Total ticks spent queuing -system.physmem.totMemAccLat 681341508000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76474120000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25797.20 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1014578 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 971.536840 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 905.616961 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 204.240777 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22129 2.18% 2.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22531 2.22% 4.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8793 0.87% 5.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2465 0.24% 5.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2547 0.25% 5.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1763 0.17% 5.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8722 0.86% 6.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 969 0.10% 6.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 944659 93.11% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1014578 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6201 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2466.490405 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 89690.748368 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-262143 6195 99.90% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::786432-1.04858e+06 2 0.03% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.31072e+06-1.57286e+06 1 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2.62144e+06-2.88358e+06 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6.02931e+06-6.29146e+06 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6201 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6201 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.228995 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.200624 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.980358 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2397 38.66% 38.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 13 0.21% 38.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3771 60.81% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 16 0.26% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 3 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6201 # Writes before turning the bus around for reads +system.physmem.totQLat 395011426750 # Total ticks spent queuing +system.physmem.totMemAccLat 681787501750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76473620000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25826.65 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44547.20 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 44576.65 # Average memory access latency per DRAM burst system.physmem.avgRdBW 381.41 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.66 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.12 # Average system read bandwidth in MiByte/s @@ -262,62 +265,71 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 3.00 # Data bus utilization in percentage system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.61 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.40 # Average write queue length when enqueuing -system.physmem.readRowHits 14297661 # Number of row buffer hits during reads -system.physmem.writeRowHits 89445 # Number of row buffer hits during writes +system.physmem.avgRdQLen 6.27 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.27 # Average write queue length when enqueuing +system.physmem.readRowHits 14297539 # Number of row buffer hits during reads +system.physmem.writeRowHits 89444 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.72 # Row buffer hit rate for writes -system.physmem.avgGap 159307.76 # Average gap between requests +system.physmem.writeRowHitRate 83.70 # Row buffer hit rate for writes +system.physmem.avgGap 159305.64 # Average gap between requests system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2209628504250 # Time in different power states -system.physmem.memoryStateTime::REF 85698860000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2209544766500 # Time in different power states +system.physmem.memoryStateTime::REF 85697820000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 271106544500 # Time in different power states +system.physmem.memoryStateTime::ACT 271160177250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 54713053 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16348871 # Transaction distribution -system.membus.trans_dist::ReadResp 16348871 # Transaction distribution +system.membus.trans_dist::ReadReq 16348869 # Transaction distribution +system.membus.trans_dist::ReadResp 16348869 # Transaction distribution system.membus.trans_dist::WriteReq 763365 # Transaction distribution system.membus.trans_dist::WriteResp 763365 # Transaction distribution -system.membus.trans_dist::Writeback 59552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4670 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4670 # Transaction distribution -system.membus.trans_dist::ReadExReq 131585 # Transaction distribution -system.membus.trans_dist::ReadExResp 131585 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383068 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::Writeback 59539 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4678 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4678 # Transaction distribution +system.membus.trans_dist::ReadExReq 131592 # Transaction distribution +system.membus.trans_dist::ReadExResp 131592 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383066 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 8 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3800 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1892024 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4278902 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1892039 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4278915 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34556534 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390502 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7600 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16908832 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19307194 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140417722 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140417722 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1781248000 # Layer occupancy (ticks) +system.membus.pkt_count::total 34556547 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390498 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16908384 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19306742 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 140417270 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 219423 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 219423 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 219423 # Request fanout histogram +system.membus.reqLayer0.occupancy 1783264500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 6000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3519500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3414000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17618629000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17618330500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4827707725 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4827152764 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37448813750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37437958000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -325,13 +337,12 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48121550 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16322172 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322172 # Transaction distribution +system.iobus.trans_dist::ReadReq 16322171 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322171 # Transaction distribution system.iobus.trans_dist::WriteReq 8178 # Transaction distribution system.iobus.trans_dist::WriteResp 8178 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7942 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 524 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -353,41 +364,40 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2383068 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2383066 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32660700 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1048 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390502 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123501030 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123501030 # Total data (bytes) +system.iobus.pkt_count::total 32660698 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1048 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 2390498 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 123501026 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3977000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3976000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 524000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -431,22 +441,22 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374890000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2374888000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38181688250 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38185527000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 12541574 # Number of BP lookups -system.cpu.branchPred.condPredicted 9090690 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1061681 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8536244 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6183587 # Number of BTB hits +system.cpu.branchPred.lookups 12550628 # Number of BP lookups +system.cpu.branchPred.condPredicted 9093116 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1061685 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8575859 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6183324 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.439202 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1558068 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 139509 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.101512 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1560078 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 139853 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -470,25 +480,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 13629654 # DTB read hits -system.cpu.dtb.read_misses 33608 # DTB read misses -system.cpu.dtb.write_hits 11376786 # DTB write hits -system.cpu.dtb.write_misses 3775 # DTB write misses +system.cpu.dtb.read_hits 13629467 # DTB read hits +system.cpu.dtb.read_misses 33605 # DTB read misses +system.cpu.dtb.write_hits 11376627 # DTB write hits +system.cpu.dtb.write_misses 3703 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3449 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1586 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 251 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3447 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1539 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 252 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 593 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 13663262 # DTB read accesses -system.cpu.dtb.write_accesses 11380561 # DTB write accesses +system.cpu.dtb.read_accesses 13663072 # DTB read accesses +system.cpu.dtb.write_accesses 11380330 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 25006440 # DTB hits -system.cpu.dtb.misses 37383 # DTB misses -system.cpu.dtb.accesses 25043823 # DTB accesses +system.cpu.dtb.hits 25006094 # DTB hits +system.cpu.dtb.misses 37308 # DTB misses +system.cpu.dtb.accesses 25043402 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -510,8 +520,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 22903214 # ITB inst hits -system.cpu.itb.inst_misses 9061 # ITB inst misses +system.cpu.itb.inst_hits 22908933 # ITB inst hits +system.cpu.itb.inst_misses 9079 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -520,84 +530,84 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2388 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2384 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 5760 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 5702 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 22912275 # ITB inst accesses -system.cpu.itb.hits 22903214 # DTB hits -system.cpu.itb.misses 9061 # DTB misses -system.cpu.itb.accesses 22912275 # DTB accesses -system.cpu.numCycles 572663270 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 22918012 # ITB inst accesses +system.cpu.itb.hits 22908933 # DTB hits +system.cpu.itb.misses 9079 # DTB misses +system.cpu.itb.accesses 22918012 # DTB accesses +system.cpu.numCycles 572551547 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60593470 # Number of instructions committed -system.cpu.committedOps 72944147 # Number of ops (including micro ops) committed -system.cpu.discardedOps 3225433 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 60593541 # Number of instructions committed +system.cpu.committedOps 72944224 # Number of ops (including micro ops) committed +system.cpu.discardedOps 3228444 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 77492 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 4562060973 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 9.450907 # CPI: cycles per instruction -system.cpu.ipc 0.105810 # IPC: instructions per cycle +system.cpu.quiesceCycles 4562038068 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 9.449052 # CPI: cycles per instruction +system.cpu.ipc 0.105831 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 82978 # number of quiesce instructions executed -system.cpu.tickCycles 466702382 # Number of cycles that the object actually ticked -system.cpu.idleCycles 105960888 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 1529303 # number of replacements -system.cpu.icache.tags.tagsinuse 511.463660 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 21367406 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1529815 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 13.967314 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 9992606000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.463660 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998952 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998952 # Average percentage of cache occupancy +system.cpu.tickCycles 466653116 # Number of cycles that the object actually ticked +system.cpu.idleCycles 105898431 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 1529478 # number of replacements +system.cpu.icache.tags.tagsinuse 511.463685 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 21373010 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1529990 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 13.969379 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 9990881000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.463685 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998953 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998953 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 190 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 24427037 # Number of tag accesses -system.cpu.icache.tags.data_accesses 24427037 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 21367406 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 21367406 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 21367406 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 21367406 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 21367406 # number of overall hits -system.cpu.icache.overall_hits::total 21367406 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1529816 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1529816 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1529816 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1529816 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1529816 # number of overall misses -system.cpu.icache.overall_misses::total 1529816 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20677210137 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20677210137 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20677210137 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20677210137 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20677210137 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20677210137 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22897222 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22897222 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22897222 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22897222 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22897222 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22897222 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.066812 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.066812 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.066812 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.066812 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.066812 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.066812 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13516.141900 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13516.141900 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13516.141900 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13516.141900 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13516.141900 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13516.141900 # average overall miss latency +system.cpu.icache.tags.tag_accesses 24432991 # Number of tag accesses +system.cpu.icache.tags.data_accesses 24432991 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 21373010 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 21373010 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 21373010 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 21373010 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 21373010 # number of overall hits +system.cpu.icache.overall_hits::total 21373010 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1529991 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1529991 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1529991 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1529991 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1529991 # number of overall misses +system.cpu.icache.overall_misses::total 1529991 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20681368889 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20681368889 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20681368889 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20681368889 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20681368889 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20681368889 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22903001 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22903001 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22903001 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22903001 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22903001 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22903001 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.066803 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.066803 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.066803 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.066803 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.066803 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.066803 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13517.314082 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13517.314082 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13517.314082 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13517.314082 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13517.314082 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13517.314082 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -606,198 +616,211 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1529816 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1529816 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1529816 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1529816 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1529816 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1529816 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17611902863 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17611902863 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17611902863 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17611902863 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17611902863 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17611902863 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1529991 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1529991 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1529991 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1529991 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1529991 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1529991 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17615727111 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17615727111 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17615727111 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17615727111 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17615727111 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17615727111 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 172140750 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 172140750 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 172140750 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 172140750 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.066812 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.066812 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.066812 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.066812 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.066812 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.066812 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11512.432125 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11512.432125 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11512.432125 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11512.432125 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11512.432125 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11512.432125 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.066803 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.066803 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.066803 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.066803 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.066803 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.066803 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11513.614859 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11513.614859 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11513.614859 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11513.614859 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11513.614859 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11513.614859 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 71285625 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 3182019 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3182018 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 3182062 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3182061 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763365 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763365 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 600964 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2972 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2972 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 247467 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 247467 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3062398 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5774016 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 28971 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 100817 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8966202 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 97936512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84584698 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 43908 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 166616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 182731734 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 182731734 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 218488 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3381194945 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 600919 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2980 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2980 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 247461 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 247461 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3062730 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5773755 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 28972 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 100548 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8966005 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 97946560 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84574454 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 43804 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 165736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 182730554 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 26649 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2846983 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 2846983 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2846983 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3381152937 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2301585887 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2301840639 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2547997212 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2547807667 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 18000487 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 18027487 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 59164999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 59116998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 65085 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51558.734735 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2407104 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 130473 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 18.449058 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2524856942500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36497.819876 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 14.059887 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 65091 # number of replacements +system.cpu.l2cache.tags.tagsinuse 51567.943403 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2406935 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 130479 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 18.446915 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2524835361000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 36492.360835 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 17.402377 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000576 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 15046.854396 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.556913 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000215 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 15058.179616 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.556829 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000266 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.229597 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.786724 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65374 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.229770 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.786864 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 15 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65373 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2560 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6585 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56117 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000214 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997528 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 22967155 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 22967155 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 41633 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10975 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1892880 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1945488 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 600964 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 600964 # number of Writeback hits +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2561 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6578 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56121 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000229 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997513 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 22965227 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 22965227 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 41408 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10949 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 1892934 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1945291 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 600919 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 600919 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.inst 25 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 25 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 114159 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 114159 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 41633 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 10975 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 2007039 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2059647 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 41633 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 10975 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 2007039 # number of overall hits -system.cpu.l2cache.overall_hits::total 2059647 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 21 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_hits::cpu.inst 114146 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 114146 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 41408 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 10949 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 2007080 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2059437 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 41408 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 10949 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 2007080 # number of overall hits +system.cpu.l2cache.overall_hits::total 2059437 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 26 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 23661 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 23684 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.inst 2947 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2947 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 133308 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133308 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 21 # number of demand (read+write) misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 23655 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 23683 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.inst 2955 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2955 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 133315 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133315 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 26 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 156969 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 156992 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 21 # number of overall misses +system.cpu.l2cache.demand_misses::cpu.inst 156970 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 156998 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 26 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 156969 # number of overall misses -system.cpu.l2cache.overall_misses::total 156992 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1631500 # number of ReadReq miss cycles +system.cpu.l2cache.overall_misses::cpu.inst 156970 # number of overall misses +system.cpu.l2cache.overall_misses::total 156998 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2068000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 149500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1700660750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1702441750 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 347985 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 347985 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9353977027 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9353977027 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1631500 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1704040750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1706258250 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 348485 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 348485 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9355155027 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9355155027 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2068000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 149500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11054637777 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 11056418777 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1631500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11059195777 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11061413277 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2068000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 149500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11054637777 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 11056418777 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 41654 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10977 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1916541 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1969172 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 600964 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 600964 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 2972 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2972 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 247467 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 247467 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 41654 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 10977 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 2164008 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2216639 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 41654 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 10977 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 2164008 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2216639 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000504 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000182 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012346 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.012027 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.991588 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991588 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.538690 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.538690 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000504 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000182 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.072536 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.070824 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000504 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000182 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.072536 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.070824 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 77690.476190 # average ReadReq miss latency +system.cpu.l2cache.overall_miss_latency::cpu.inst 11059195777 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11061413277 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 41434 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10951 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1916589 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1968974 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 600919 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 600919 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 2980 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2980 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 247461 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 247461 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 41434 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 10951 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 2164050 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2216435 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 41434 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 10951 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 2164050 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2216435 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000628 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000183 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012342 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.012028 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.991611 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991611 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.538731 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.538731 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000628 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000183 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.072535 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.070834 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000628 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000183 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.072535 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.070834 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 79538.461538 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 74750 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71876.114704 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71881.512836 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 118.081099 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 118.081099 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 70168.159653 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70168.159653 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 77690.476190 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72037.233143 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72045.697336 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 117.930626 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 117.930626 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 70173.311533 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70173.311533 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 79538.461538 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70425.611280 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70426.638154 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 77690.476190 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70454.200019 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70455.759163 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 79538.461538 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70425.611280 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70426.638154 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70454.200019 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70455.759163 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -806,84 +829,84 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59552 # number of writebacks -system.cpu.l2cache.writebacks::total 59552 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 59539 # number of writebacks +system.cpu.l2cache.writebacks::total 59539 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 69 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 21 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 26 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 23592 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 23615 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 2947 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2947 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 133308 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133308 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 21 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 23586 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 23614 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 2955 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2955 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 133315 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133315 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 26 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 156900 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 156923 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 21 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 156901 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 156929 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 26 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 156900 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 156923 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1370000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.inst 156901 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 156929 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1746000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1400834750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1402329750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 29473947 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29473947 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7655220473 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7655220473 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1370000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1404219250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1406090250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 29553955 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29553955 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7656846473 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7656846473 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1746000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9056055223 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9057550223 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1370000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9061065723 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9062936723 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1746000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9056055223 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9057550223 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 167362107250 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167362107250 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 16707879855 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16707879855 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 184069987105 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184069987105 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000504 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000182 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012310 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.011992 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.991588 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991588 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.538690 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.538690 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000504 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000182 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.072504 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.070793 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000504 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000182 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.072504 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.070793 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65238.095238 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9061065723 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9062936723 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 167363942750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167363942750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 16707802808 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16707802808 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 184071745558 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184071745558 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000628 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000183 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012306 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.011993 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.991611 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991611 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.538731 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.538731 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000628 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000183 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.072503 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.070802 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000628 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000183 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.072503 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.070802 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67153.846154 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59377.532638 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59383.008681 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10001.339328 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.339328 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57425.064310 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57425.064310 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65238.095238 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59536.133723 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59544.772169 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10001.338409 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.338409 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57434.245756 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57434.245756 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67153.846154 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57718.643869 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57719.711088 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65238.095238 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57750.210152 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57751.828680 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67153.846154 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57718.643869 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57719.711088 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57750.210152 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57751.828680 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency @@ -891,86 +914,86 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 635561 # number of replacements +system.cpu.dcache.tags.replacements 635446 # number of replacements system.cpu.dcache.tags.tagsinuse 511.959259 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21828853 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 636073 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 34.318157 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 21828831 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 635958 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.324328 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 227074250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.inst 511.959259 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.999920 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999920 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 343 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 91724261 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 91724261 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 11595405 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11595405 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 9746069 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9746069 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 236744 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236744 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 91723842 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 91723842 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 11595412 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11595412 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 9746012 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9746012 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 236764 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236764 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.inst 247613 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247613 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 21341474 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21341474 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 21341474 # number of overall hits -system.cpu.dcache.overall_hits::total 21341474 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 458732 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 458732 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 476614 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 476614 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.inst 10870 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 10870 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.inst 935346 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 935346 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 935346 # number of overall misses -system.cpu.dcache.overall_misses::total 935346 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6943170934 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6943170934 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 22231593506 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22231593506 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 151835000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 151835000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 29174764440 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29174764440 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 29174764440 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29174764440 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 12054137 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12054137 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 10222683 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222683 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.inst 21341424 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21341424 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 21341424 # number of overall hits +system.cpu.dcache.overall_hits::total 21341424 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 458657 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 458657 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 476663 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 476663 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.inst 10850 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 10850 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.inst 935320 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 935320 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 935320 # number of overall misses +system.cpu.dcache.overall_misses::total 935320 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6947637684 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6947637684 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 22233411759 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22233411759 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 151795500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 151795500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 29181049443 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29181049443 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 29181049443 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29181049443 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 12054069 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12054069 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 10222675 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222675 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 247614 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 247614 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.inst 247613 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247613 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 22276820 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 22276820 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 22276820 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 22276820 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.038056 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.038056 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.046623 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.046623 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.043899 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.043899 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.041987 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.041987 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.041987 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.041987 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 15135.571388 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15135.571388 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 46644.860424 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 46644.860424 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13968.261270 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13968.261270 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 31191.414129 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31191.414129 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 31191.414129 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31191.414129 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.inst 22276744 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 22276744 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 22276744 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 22276744 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.038050 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.038050 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.046628 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.046628 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.043818 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.043818 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.041986 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.041986 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.041986 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.041986 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 15147.785129 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15147.785129 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 46643.879972 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 46643.879972 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13990.368664 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13990.368664 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 31199.000816 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31199.000816 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 31199.000816 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31199.000816 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -979,64 +1002,64 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 600964 # number of writebacks -system.cpu.dcache.writebacks::total 600964 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 80923 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 80923 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 226176 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 226176 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 72 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 72 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 307099 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 307099 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 307099 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 307099 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 377809 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 377809 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 250438 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250438 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 10798 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 10798 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 628247 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 628247 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 628247 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 628247 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4823958811 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4823958811 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10813361832 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10813361832 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 129211000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 129211000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 15637320643 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15637320643 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 15637320643 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15637320643 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 182632094750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182632094750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 26058171145 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26058171145 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 208690265895 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 208690265895 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.031343 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031343 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 600919 # number of writebacks +system.cpu.dcache.writebacks::total 600919 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 80937 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 80937 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 226224 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 226224 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 71 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 71 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 307161 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 307161 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 307161 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 307161 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 377720 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 377720 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 250439 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250439 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 10779 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 10779 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 628159 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 628159 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 628159 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 628159 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4824316311 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4824316311 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10814527330 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10814527330 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 129220000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 129220000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 15638843641 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15638843641 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 15638843641 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15638843641 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 182633838500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182633838500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 26058035692 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26058035692 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 208691874192 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 208691874192 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.031335 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031335 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.024498 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024498 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.043608 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.043608 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.028202 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028202 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.028202 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028202 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12768.247477 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12768.247477 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 43177.799823 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43177.799823 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11966.197444 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11966.197444 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 24890.402410 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24890.402410 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 24890.402410 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24890.402410 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.043531 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.043531 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.028198 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028198 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.028198 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028198 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12772.202454 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12772.202454 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 43182.281234 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43182.281234 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11988.125058 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11988.125058 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 24896.313897 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24896.313897 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 24896.313897 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24896.313897 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency @@ -1060,10 +1083,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736623648250 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1736623648250 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736623648250 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1736623648250 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1737063641000 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1737063641000 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1737063641000 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1737063641000 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 05396d247..ffb671fcc 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.542203 # Number of seconds simulated -sim_ticks 2542202956000 # Number of ticks simulated -final_tick 2542202956000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.542157 # Number of seconds simulated +sim_ticks 2542156879500 # Number of ticks simulated +final_tick 2542156879500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 40853 # Simulator instruction rate (inst/s) -host_op_rate 49218 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1721973071 # Simulator tick rate (ticks/s) -host_mem_usage 411692 # Number of bytes of host memory used -host_seconds 1476.33 # Real time elapsed on the host -sim_insts 60311945 # Number of instructions simulated -sim_ops 72661478 # Number of ops (including micro ops) simulated +host_inst_rate 45011 # Simulator instruction rate (inst/s) +host_op_rate 54228 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1897222602 # Simulator tick rate (ticks/s) +host_mem_usage 464684 # Number of bytes of host memory used +host_seconds 1339.94 # Real time elapsed on the host +sim_insts 60311972 # Number of instructions simulated +sim_ops 72661518 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.realview.nvmem.bytes_read::cpu.inst 48 # Number of bytes read from this memory @@ -28,95 +28,95 @@ system.realview.nvmem.bw_total::total 19 # To system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 640 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 798576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9072728 # Number of bytes read from this memory -system.physmem.bytes_read::total 130982664 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 798576 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 798576 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 798448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9072920 # Number of bytes read from this memory +system.physmem.bytes_read::total 130982728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 798448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798448 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 3743232 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory system.physmem.bytes_written::total 6759304 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 10 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 14991 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141787 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15295607 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 14989 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141790 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15295608 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 58488 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory system.physmem.num_writes::total 812506 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47639992 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.clcd 47640855 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 252 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314128 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3568845 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51523292 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314128 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314128 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1472436 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1186401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2658837 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1472436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47639992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314083 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3568985 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51524251 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314083 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314083 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1472463 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1186422 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2658885 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1472463 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47640855 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 252 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314128 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4755246 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54182129 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15295607 # Number of read requests accepted +system.physmem.bw_total::cpu.inst 314083 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4755408 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54183136 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15295608 # Number of read requests accepted system.physmem.writeReqs 812506 # Number of write requests accepted -system.physmem.readBursts 15295607 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 15295608 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 812506 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 976934144 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1984704 # Total number of bytes read from write queue -system.physmem.bytesWritten 6778304 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 130982664 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 977064192 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1854720 # Total number of bytes read from write queue +system.physmem.bytesWritten 6781120 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 130982728 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 6759304 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 31011 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706576 # Number of DRAM write bursts merged with an existing one +system.physmem.servicedByWrQ 28980 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706520 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 4612 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 955786 # Per bank write bursts +system.physmem.perBankRdBursts::0 955787 # Per bank write bursts system.physmem.perBankRdBursts::1 955478 # Per bank write bursts -system.physmem.perBankRdBursts::2 953003 # Per bank write bursts -system.physmem.perBankRdBursts::3 951059 # Per bank write bursts -system.physmem.perBankRdBursts::4 958601 # Per bank write bursts -system.physmem.perBankRdBursts::5 955602 # Per bank write bursts -system.physmem.perBankRdBursts::6 952653 # Per bank write bursts -system.physmem.perBankRdBursts::7 950407 # Per bank write bursts -system.physmem.perBankRdBursts::8 956154 # Per bank write bursts +system.physmem.perBankRdBursts::2 953511 # Per bank write bursts +system.physmem.perBankRdBursts::3 951566 # Per bank write bursts +system.physmem.perBankRdBursts::4 958612 # Per bank write bursts +system.physmem.perBankRdBursts::5 955530 # Per bank write bursts +system.physmem.perBankRdBursts::6 953056 # Per bank write bursts +system.physmem.perBankRdBursts::7 951020 # Per bank write bursts +system.physmem.perBankRdBursts::8 956158 # Per bank write bursts system.physmem.perBankRdBursts::9 955874 # Per bank write bursts -system.physmem.perBankRdBursts::10 952889 # Per bank write bursts -system.physmem.perBankRdBursts::11 950148 # Per bank write bursts +system.physmem.perBankRdBursts::10 952686 # Per bank write bursts +system.physmem.perBankRdBursts::11 950200 # Per bank write bursts system.physmem.perBankRdBursts::12 956166 # Per bank write bursts system.physmem.perBankRdBursts::13 955918 # Per bank write bursts -system.physmem.perBankRdBursts::14 953918 # Per bank write bursts -system.physmem.perBankRdBursts::15 950940 # Per bank write bursts -system.physmem.perBankWrBursts::0 6546 # Per bank write bursts -system.physmem.perBankWrBursts::1 6352 # Per bank write bursts -system.physmem.perBankWrBursts::2 6488 # Per bank write bursts -system.physmem.perBankWrBursts::3 6518 # Per bank write bursts -system.physmem.perBankWrBursts::4 6421 # Per bank write bursts -system.physmem.perBankWrBursts::5 6701 # Per bank write bursts -system.physmem.perBankWrBursts::6 6665 # Per bank write bursts -system.physmem.perBankWrBursts::7 6611 # Per bank write bursts -system.physmem.perBankWrBursts::8 6966 # Per bank write bursts -system.physmem.perBankWrBursts::9 6759 # Per bank write bursts -system.physmem.perBankWrBursts::10 6421 # Per bank write bursts -system.physmem.perBankWrBursts::11 6055 # Per bank write bursts -system.physmem.perBankWrBursts::12 7037 # Per bank write bursts -system.physmem.perBankWrBursts::13 6645 # Per bank write bursts -system.physmem.perBankWrBursts::14 6920 # Per bank write bursts -system.physmem.perBankWrBursts::15 6806 # Per bank write bursts +system.physmem.perBankRdBursts::14 953812 # Per bank write bursts +system.physmem.perBankRdBursts::15 951254 # Per bank write bursts +system.physmem.perBankWrBursts::0 6556 # Per bank write bursts +system.physmem.perBankWrBursts::1 6344 # Per bank write bursts +system.physmem.perBankWrBursts::2 6481 # Per bank write bursts +system.physmem.perBankWrBursts::3 6512 # Per bank write bursts +system.physmem.perBankWrBursts::4 6422 # Per bank write bursts +system.physmem.perBankWrBursts::5 6709 # Per bank write bursts +system.physmem.perBankWrBursts::6 6691 # Per bank write bursts +system.physmem.perBankWrBursts::7 6631 # Per bank write bursts +system.physmem.perBankWrBursts::8 6968 # Per bank write bursts +system.physmem.perBankWrBursts::9 6764 # Per bank write bursts +system.physmem.perBankWrBursts::10 6424 # Per bank write bursts +system.physmem.perBankWrBursts::11 6068 # Per bank write bursts +system.physmem.perBankWrBursts::12 7033 # Per bank write bursts +system.physmem.perBankWrBursts::13 6638 # Per bank write bursts +system.physmem.perBankWrBursts::14 6915 # Per bank write bursts +system.physmem.perBankWrBursts::15 6799 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2542201638000 # Total gap between requests +system.physmem.totGap 2542155562500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 18 # Read request sizes (log2) system.physmem.readPktSize::3 15138826 # Read request sizes (log2) system.physmem.readPktSize::4 3351 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 153412 # Read request sizes (log2) +system.physmem.readPktSize::6 153413 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) @@ -124,26 +124,26 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 58488 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1110293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 964892 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 965548 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1076032 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 973735 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1036027 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2680967 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2587988 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3368391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 128855 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 111642 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 103064 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 98734 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20085 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 19255 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18985 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 85 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1110331 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 964948 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 965784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1077100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 974799 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1038209 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2680927 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2586042 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3366057 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 129275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 112161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 103418 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 99187 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20031 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 19249 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 19008 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 90 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -171,28 +171,28 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2611 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2919 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -220,50 +220,53 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1010606 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 973.388688 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 909.020446 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 200.819397 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22711 2.25% 2.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19828 1.96% 4.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8563 0.85% 5.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2249 0.22% 5.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2594 0.26% 5.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1688 0.17% 5.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8931 0.88% 6.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 959 0.09% 6.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 943083 93.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1010606 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6196 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2463.620239 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 113702.310017 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 6191 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1010646 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 973.481627 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 909.246732 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 200.676766 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22575 2.23% 2.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19975 1.98% 4.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8601 0.85% 5.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2200 0.22% 5.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2445 0.24% 5.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1700 0.17% 5.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8928 0.88% 6.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 928 0.09% 6.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 943294 93.34% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1010646 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6195 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2464.343987 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 113708.986245 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 6190 99.92% 99.92% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 2 0.03% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6196 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6196 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.093447 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.042337 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.354685 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3441 55.54% 55.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 45 0.73% 56.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1714 27.66% 83.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 868 14.01% 97.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 47 0.76% 98.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 22 0.36% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 27 0.44% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 21 0.34% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 10 0.16% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6196 # Writes before turning the bus around for reads -system.physmem.totQLat 395449280750 # Total ticks spent queuing -system.physmem.totMemAccLat 681660455750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76322980000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25906.31 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6195 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6195 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.103309 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.049475 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.400786 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3455 55.77% 55.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 44 0.71% 56.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1683 27.17% 83.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 856 13.82% 97.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 62 1.00% 98.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 32 0.52% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 30 0.48% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 14 0.23% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 13 0.21% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 3 0.05% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6195 # Writes before turning the bus around for reads +system.physmem.totQLat 395458190750 # Total ticks spent queuing +system.physmem.totMemAccLat 681707465750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76333140000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25903.44 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44656.31 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 384.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44653.44 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 384.34 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.67 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.52 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.66 # Average system write bandwidth in MiByte/s @@ -271,62 +274,71 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 3.02 # Data bus utilization in percentage system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.20 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.61 # Average write queue length when enqueuing -system.physmem.readRowHits 14269193 # Number of row buffer hits during reads -system.physmem.writeRowHits 90708 # Number of row buffer hits during writes +system.physmem.avgRdQLen 7.09 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.73 # Average write queue length when enqueuing +system.physmem.readRowHits 14271218 # Number of row buffer hits during reads +system.physmem.writeRowHits 90719 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.63 # Row buffer hit rate for writes -system.physmem.avgGap 157821.19 # Average gap between requests -system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2194513894000 # Time in different power states -system.physmem.memoryStateTime::REF 84889480000 # Time in different power states +system.physmem.writeRowHitRate 85.60 # Row buffer hit rate for writes +system.physmem.avgGap 157818.32 # Average gap between requests +system.physmem.pageHitRate 93.43 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2194559119750 # Time in different power states +system.physmem.memoryStateTime::REF 84888180000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 262799464750 # Time in different power states +system.physmem.memoryStateTime::ACT 262709081500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 55125441 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16348039 # Transaction distribution -system.membus.trans_dist::ReadResp 16348039 # Transaction distribution +system.membus.trans_dist::ReadReq 16348037 # Transaction distribution +system.membus.trans_dist::ReadResp 16348037 # Transaction distribution system.membus.trans_dist::WriteReq 763357 # Transaction distribution system.membus.trans_dist::WriteResp 763357 # Transaction distribution system.membus.trans_dist::Writeback 58488 # Transaction distribution system.membus.trans_dist::UpgradeReq 4612 # Transaction distribution system.membus.trans_dist::UpgradeResp 4612 # Transaction distribution -system.membus.trans_dist::ReadExReq 131651 # Transaction distribution -system.membus.trans_dist::ReadExResp 131651 # Transaction distribution +system.membus.trans_dist::ReadExReq 131654 # Transaction distribution +system.membus.trans_dist::ReadExResp 131654 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383056 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 6 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3780 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1889330 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4276174 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1889332 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4276176 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34553806 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390478 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 48 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16631440 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19029530 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140140058 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140140058 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1558440500 # Layer occupancy (ticks) +system.membus.pkt_count::total 34553808 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390478 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 48 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16631504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19029594 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 140140122 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 216513 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 216513 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 216513 # Request fanout histogram +system.membus.reqLayer0.occupancy 1556318500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 3500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3512000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3760500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17513415500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17512345000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4726913870 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4726136292 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37423565460 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37419189712 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -334,7 +346,6 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48580309 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16322168 # Transaction distribution system.iobus.trans_dist::ReadResp 16322168 # Transaction distribution system.iobus.trans_dist::WriteReq 8176 # Transaction distribution @@ -366,34 +377,33 @@ system.iobus.pkt_count_system.bridge.master::total 2383056 system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 32660688 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390478 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123501006 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123501006 # Total data (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 2390478 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 123501006 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks) @@ -440,22 +450,22 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374880000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38173420540 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38173439288 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 13201290 # Number of BP lookups -system.cpu.branchPred.condPredicted 9675974 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 704139 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8377301 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6024680 # Number of BTB hits +system.cpu.branchPred.lookups 13200672 # Number of BP lookups +system.cpu.branchPred.condPredicted 9675464 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 704019 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8378152 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6024616 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.916719 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1435837 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 30801 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 71.908650 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1435808 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 30777 # Number of incorrect RAS predictions. system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -479,25 +489,25 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 13156743 # DTB read hits -system.cpu.checker.dtb.read_misses 7321 # DTB read misses -system.cpu.checker.dtb.write_hits 11227340 # DTB write hits +system.cpu.checker.dtb.read_hits 13156766 # DTB read hits +system.cpu.checker.dtb.read_misses 7319 # DTB read misses +system.cpu.checker.dtb.write_hits 11227349 # DTB write hits system.cpu.checker.dtb.write_misses 2193 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 3404 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_entries 3403 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.checker.dtb.prefetch_faults 180 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 13164064 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11229533 # DTB write accesses +system.cpu.checker.dtb.read_accesses 13164085 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11229542 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 24384083 # DTB hits -system.cpu.checker.dtb.misses 9514 # DTB misses -system.cpu.checker.dtb.accesses 24393597 # DTB accesses +system.cpu.checker.dtb.hits 24384115 # DTB hits +system.cpu.checker.dtb.misses 9512 # DTB misses +system.cpu.checker.dtb.accesses 24393627 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -519,7 +529,7 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.inst_hits 61486079 # ITB inst hits +system.cpu.checker.itb.inst_hits 61486106 # ITB inst hits system.cpu.checker.itb.inst_misses 4473 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -536,11 +546,11 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61490552 # ITB inst accesses -system.cpu.checker.itb.hits 61486079 # DTB hits +system.cpu.checker.itb.inst_accesses 61490579 # ITB inst accesses +system.cpu.checker.itb.hits 61486106 # DTB hits system.cpu.checker.itb.misses 4473 # DTB misses -system.cpu.checker.itb.accesses 61490552 # DTB accesses -system.cpu.checker.numCycles 72947431 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61490579 # DTB accesses +system.cpu.checker.numCycles 72947471 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -566,25 +576,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 31642294 # DTB read hits -system.cpu.dtb.read_misses 39524 # DTB read misses -system.cpu.dtb.write_hits 11381361 # DTB write hits -system.cpu.dtb.write_misses 10135 # DTB write misses +system.cpu.dtb.read_hits 31644036 # DTB read hits +system.cpu.dtb.read_misses 39518 # DTB read misses +system.cpu.dtb.write_hits 11381434 # DTB write hits +system.cpu.dtb.write_misses 10146 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3437 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 348 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.flush_entries 3436 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 314 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 314 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 1342 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 31681818 # DTB read accesses -system.cpu.dtb.write_accesses 11391496 # DTB write accesses +system.cpu.dtb.read_accesses 31683554 # DTB read accesses +system.cpu.dtb.write_accesses 11391580 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 43023655 # DTB hits -system.cpu.dtb.misses 49659 # DTB misses -system.cpu.dtb.accesses 43073314 # DTB accesses +system.cpu.dtb.hits 43025470 # DTB hits +system.cpu.dtb.misses 49664 # DTB misses +system.cpu.dtb.accesses 43075134 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -606,8 +616,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 24159481 # ITB inst hits -system.cpu.itb.inst_misses 10516 # ITB inst misses +system.cpu.itb.inst_hits 24158829 # ITB inst hits +system.cpu.itb.inst_misses 10513 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -616,98 +626,98 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2464 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2463 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 4176 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 4177 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 24169997 # ITB inst accesses -system.cpu.itb.hits 24159481 # DTB hits -system.cpu.itb.misses 10516 # DTB misses -system.cpu.itb.accesses 24169997 # DTB accesses -system.cpu.numCycles 499350041 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 24169342 # ITB inst accesses +system.cpu.itb.hits 24158829 # DTB hits +system.cpu.itb.misses 10513 # DTB misses +system.cpu.itb.accesses 24169342 # DTB accesses +system.cpu.numCycles 499362415 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 43030629 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 74131140 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13201290 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 7460517 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 448266810 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1858598 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 133224 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 12550 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 145871 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 3032125 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 24158180 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 404816 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4527 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 495550550 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.179793 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 0.652924 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 43030394 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 74128653 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13200672 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 7460424 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 448275105 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1858360 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 133126 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 12568 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 145919 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 3031035 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 24157528 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 404783 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4525 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 495557370 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.179785 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 0.652906 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 454644690 91.75% 91.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13614673 2.75% 94.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6391682 1.29% 95.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 20899505 4.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 454652495 91.75% 91.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13614115 2.75% 94.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6392828 1.29% 95.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 20897932 4.22% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 495550550 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.026437 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.148455 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35577628 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 424964763 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 30286365 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4037656 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 684138 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1691487 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 250438 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 80256354 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2078563 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 684138 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 38799814 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 217885603 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 28702319 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 30653900 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 178824776 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 78213523 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 597412 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 61147213 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 42400387 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 160465829 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 14695892 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 82092463 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 364185184 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 97017359 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 495557370 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.026435 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.148447 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35569711 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 424983346 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 30281377 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4038894 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 684042 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1691471 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 250415 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 80255110 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2078434 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 684042 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 38792488 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 217877928 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 28703436 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 30648610 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 178850866 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 78212678 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 597297 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 61152111 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 42400388 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 160465834 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 14716938 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 82091302 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 364181024 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 97016550 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 9816 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 75931181 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6161276 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1134052 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 964724 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8995770 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 14558741 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 12101093 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 791110 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1256144 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 75819284 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1655722 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 93902738 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 178739 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4397586 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8688962 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 172255 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 495550550 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 75931219 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 6160077 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1133996 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 964709 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 9001428 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 14558433 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 12101238 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 791096 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1255692 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 75818942 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1655707 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 93904368 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 178701 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4397117 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 8687724 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 172240 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 495557370 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.189492 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.548412 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.548385 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 430558497 86.88% 86.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 42998311 8.68% 95.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 15714626 3.17% 98.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5641325 1.14% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 637755 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 430560734 86.88% 86.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 43002673 8.68% 95.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 15716973 3.17% 98.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5640247 1.14% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 636707 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 36 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -715,44 +725,44 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 495550550 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 495557370 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4849757 15.79% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 148 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 20356138 66.26% 82.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5517293 17.96% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4845097 15.77% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 148 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 20357888 66.27% 82.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5517607 17.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 28518 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49538159 52.75% 52.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91859 0.10% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49538039 52.75% 52.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91860 0.10% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.88% # Type of FU issued @@ -776,101 +786,101 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.88% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 32267131 34.36% 87.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 11974960 12.75% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 32268758 34.36% 87.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 11975082 12.75% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 93902738 # Type of FU issued -system.cpu.iq.rate 0.188050 # Inst issue rate -system.cpu.iq.fu_busy_cnt 30723336 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.327183 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 714225557 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 81867089 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 74968821 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 93904368 # Type of FU issued +system.cpu.iq.rate 0.188049 # Inst issue rate +system.cpu.iq.fu_busy_cnt 30720740 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.327149 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 714233003 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 81866264 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 74968812 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 32544 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 12124 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10212 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124576093 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 124575127 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 21463 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 210027 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 210020 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1045815 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 542 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6661 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 369450 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1045495 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 540 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6662 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 369586 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17074256 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1003626 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17074158 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1006174 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 684138 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 94162664 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 98281305 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 77651016 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 684042 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 94158200 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 98278744 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 77650660 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 14558741 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 12101093 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1114432 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 20278 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 98196726 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6661 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 210280 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 275497 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 485777 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93247730 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 32000327 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 605564 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 14558433 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 12101238 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1114427 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 20284 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 98194153 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6662 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 210239 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 275440 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 485679 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93249449 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 32002025 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 605470 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 176010 # number of nop insts executed -system.cpu.iew.exec_refs 43889216 # number of memory reference insts executed -system.cpu.iew.exec_branches 10791342 # Number of branches executed -system.cpu.iew.exec_stores 11888889 # Number of stores executed -system.cpu.iew.exec_rate 0.186738 # Inst execution rate -system.cpu.iew.wb_sent 92183788 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 74979033 # cumulative count of insts written-back -system.cpu.iew.wb_producers 35465784 # num instructions producing a value -system.cpu.iew.wb_consumers 52709939 # num instructions consuming a value +system.cpu.iew.exec_nop 176011 # number of nop insts executed +system.cpu.iew.exec_refs 43890987 # number of memory reference insts executed +system.cpu.iew.exec_branches 10791373 # Number of branches executed +system.cpu.iew.exec_stores 11888962 # Number of stores executed +system.cpu.iew.exec_rate 0.186737 # Inst execution rate +system.cpu.iew.wb_sent 92183769 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 74979024 # cumulative count of insts written-back +system.cpu.iew.wb_producers 35461894 # num instructions producing a value +system.cpu.iew.wb_consumers 52697256 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.150153 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.672848 # average fanout of values written-back +system.cpu.iew.wb_rate 0.150150 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.672936 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 3942514 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 3942249 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1483467 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 458978 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 494644570 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.147200 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 0.699335 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 458881 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 494573774 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.147222 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 0.699394 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 457921524 92.58% 92.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 22157230 4.48% 97.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 6973464 1.41% 98.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2402706 0.49% 98.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1803578 0.36% 99.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1042786 0.21% 99.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 592301 0.12% 99.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 490313 0.10% 99.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1260668 0.25% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 457850390 92.57% 92.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 22155471 4.48% 97.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 6977487 1.41% 98.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2402189 0.49% 98.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1803487 0.36% 99.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1041949 0.21% 99.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 590384 0.12% 99.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 490446 0.10% 99.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1261971 0.26% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 494644570 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60462326 # Number of instructions committed -system.cpu.commit.committedOps 72811859 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 494573774 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60462353 # Number of instructions committed +system.cpu.commit.committedOps 72811899 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 25244569 # Number of memory references committed -system.cpu.commit.loads 13512926 # Number of loads committed +system.cpu.commit.refs 25244590 # Number of memory references committed +system.cpu.commit.loads 13512938 # Number of loads committed system.cpu.commit.membars 403660 # Number of memory barriers committed -system.cpu.commit.branches 10308073 # Number of branches committed +system.cpu.commit.branches 10308077 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 64250122 # Number of committed integer instructions. +system.cpu.commit.int_insts 64250158 # Number of committed integer instructions. system.cpu.commit.function_calls 991634 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 47477289 65.21% 65.21% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 87890 0.12% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 47477309 65.21% 65.21% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 87889 0.12% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.33% # Class of committed instruction @@ -898,72 +908,89 @@ system.cpu.commit.op_class_0::SimdFloatMisc 2111 0.00% 65.33% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 13512926 18.56% 83.89% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 11731643 16.11% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 13512938 18.56% 83.89% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 11731652 16.11% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 72811859 # Class of committed instruction -system.cpu.commit.bw_lim_events 1260668 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 72811899 # Class of committed instruction +system.cpu.commit.bw_lim_events 1261971 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 568287463 # The number of ROB reads -system.cpu.rob.rob_writes 154414560 # The number of ROB writes -system.cpu.timesIdled 544007 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3799491 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4584972685 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60311945 # Number of Instructions Simulated -system.cpu.committedOps 72661478 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.279455 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.279455 # CPI: Total CPI of All Threads -system.cpu.ipc 0.120781 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.120781 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 109116898 # number of integer regfile reads -system.cpu.int_regfile_writes 47012348 # number of integer regfile writes +system.cpu.rob.rob_reads 568215140 # The number of ROB reads +system.cpu.rob.rob_writes 154414029 # The number of ROB writes +system.cpu.timesIdled 543953 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3805045 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4584951345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60311972 # Number of Instructions Simulated +system.cpu.committedOps 72661518 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 8.279657 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.279657 # CPI: Total CPI of All Threads +system.cpu.ipc 0.120778 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.120778 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 109116744 # number of integer regfile reads +system.cpu.int_regfile_writes 47012213 # number of integer regfile writes system.cpu.fp_regfile_reads 8305 # number of floating regfile reads system.cpu.fp_regfile_writes 2780 # number of floating regfile writes -system.cpu.cc_regfile_reads 320404209 # number of cc regfile reads -system.cpu.cc_regfile_writes 30332896 # number of cc regfile writes -system.cpu.misc_regfile_reads 605539146 # number of misc regfile reads -system.cpu.misc_regfile_writes 1173999 # number of misc regfile writes -system.cpu.toL2Bus.throughput 57498963 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2604292 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2604292 # Transaction distribution +system.cpu.cc_regfile_reads 320409321 # number of cc regfile reads +system.cpu.cc_regfile_writes 30332935 # number of cc regfile writes +system.cpu.misc_regfile_reads 605119297 # number of misc regfile reads +system.cpu.misc_regfile_writes 1173998 # number of misc regfile writes +system.cpu.toL2Bus.trans_dist::ReadReq 2604204 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2604204 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763357 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763357 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 599976 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 599947 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2950 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2952 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246570 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246570 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1926546 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5768452 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 27160 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 85384 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7807542 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61456864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84377274 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 37916 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 135596 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 146007650 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 146007650 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 166384 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3090458553 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadExReq 246567 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246567 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1926460 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5768361 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 27152 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 85364 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7807337 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61454112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84373434 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 37904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 135564 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 146001014 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 26770 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2266210 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::9 2266210 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::10 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2266210 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3090363565 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1447056987 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1446991237 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2544187527 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2544137605 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 17686240 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 17681240 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 51535649 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 51517661 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 959881 # number of replacements -system.cpu.icache.tags.tagsinuse 511.383361 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 23149457 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 960393 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 24.104150 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 11344582250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.383361 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 959838 # number of replacements +system.cpu.icache.tags.tagsinuse 511.383389 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 23148830 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 960350 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 24.104576 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 11339333250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.383389 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998796 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998796 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -972,242 +999,242 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 171 system.cpu.icache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 25115239 # Number of tag accesses -system.cpu.icache.tags.data_accesses 25115239 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 23149457 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 23149457 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 23149457 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 23149457 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 23149457 # number of overall hits -system.cpu.icache.overall_hits::total 23149457 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1005369 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1005369 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1005369 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1005369 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1005369 # number of overall misses -system.cpu.icache.overall_misses::total 1005369 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13656038478 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13656038478 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13656038478 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13656038478 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13656038478 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13656038478 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24154826 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24154826 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24154826 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24154826 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24154826 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24154826 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 25114544 # Number of tag accesses +system.cpu.icache.tags.data_accesses 25114544 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 23148830 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 23148830 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 23148830 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 23148830 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 23148830 # number of overall hits +system.cpu.icache.overall_hits::total 23148830 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1005344 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1005344 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1005344 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1005344 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1005344 # number of overall misses +system.cpu.icache.overall_misses::total 1005344 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13667748229 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13667748229 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13667748229 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13667748229 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13667748229 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13667748229 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24154174 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24154174 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24154174 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24154174 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24154174 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24154174 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.041622 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.041622 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.041622 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.041622 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.041622 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.041622 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13583.110756 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13583.110756 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13583.110756 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13583.110756 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13583.110756 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13583.110756 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1617 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13595.096036 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13595.096036 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13595.096036 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13595.096036 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13595.096036 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13595.096036 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1628 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 119 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 118 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 13.588235 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 13.796610 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 44956 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 44956 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 44956 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 44956 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 44956 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 44956 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 960413 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 960413 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 960413 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 960413 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 960413 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 960413 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11283890760 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11283890760 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11283890760 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11283890760 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11283890760 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11283890760 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 223026500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 223026500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 223026500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 223026500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.039761 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.039761 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.039761 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.039761 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.039761 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.039761 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11748.998358 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11748.998358 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11748.998358 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11748.998358 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11748.998358 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11748.998358 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 44974 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 44974 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 44974 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 44974 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 44974 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 44974 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 960370 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 960370 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 960370 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 960370 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 960370 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 960370 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11288731510 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11288731510 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11288731510 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11288731510 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11288731510 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11288731510 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 223034500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 223034500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 223034500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 223034500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.039760 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.039760 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.039760 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.039760 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.039760 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.039760 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11754.564918 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11754.564918 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11754.564918 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11754.564918 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11754.564918 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11754.564918 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 63302 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51128.734687 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1829071 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 128690 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 14.213000 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2530789670500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37302.599889 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 6.814194 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 63303 # number of replacements +system.cpu.l2cache.tags.tagsinuse 51126.923594 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1828959 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 128691 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 14.212019 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2530750696500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 37301.769799 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 6.815946 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000703 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 7723.154288 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6096.165612 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.569193 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 7722.177507 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6096.159639 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.569180 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000104 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117846 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117831 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.093020 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.780163 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.780135 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 65381 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 268 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3024 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6221 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55835 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 269 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3025 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6220 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55834 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997635 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 18316308 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 18316308 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 33888 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 9476 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 947771 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 377103 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1368238 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 599976 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 599976 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 18315394 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 18315394 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 33880 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 9473 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 947730 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 377075 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1368158 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 599947 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 599947 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 41 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 41 # number of UpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 113216 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 113216 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 33888 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 9476 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 947771 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 490319 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1481454 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 33888 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 9476 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 947771 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 490319 # number of overall hits -system.cpu.l2cache.overall_hits::total 1481454 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 113210 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 113210 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 33880 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 9473 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 947730 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 490285 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1481368 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 33880 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 9473 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 947730 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 490285 # number of overall hits +system.cpu.l2cache.overall_hits::total 1481368 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 11 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 11654 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 11652 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 10148 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 21816 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 21814 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 2909 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 2909 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133354 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133354 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133357 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133357 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 11 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 11654 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143502 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 155170 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 11652 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143505 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 155171 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 11 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 11654 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143502 # number of overall misses -system.cpu.l2cache.overall_misses::total 155170 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 790250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 238750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 830265249 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 761175750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1592469999 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 348485 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 348485 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9338459797 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9338459797 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 790250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 238750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 830265249 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10099635547 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10930929796 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 790250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 238750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 830265249 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10099635547 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10930929796 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 33899 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 9479 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 959425 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 387251 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1390054 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 599976 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 599976 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.inst 11652 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143505 # number of overall misses +system.cpu.l2cache.overall_misses::total 155171 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 790750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 238250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 835556749 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 759914000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1596499749 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 349485 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 349485 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9345897297 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9345897297 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 790750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 238250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 835556749 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10105811297 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10942397046 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 790750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 238250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 835556749 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10105811297 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10942397046 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 33891 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 9476 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 959382 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 387223 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1389972 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 599947 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 599947 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2950 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2950 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246570 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246570 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 33899 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 9479 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 959425 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 633821 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1636624 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 33899 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 9479 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 959425 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 633821 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1636624 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000324 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000316 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012147 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026205 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246567 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246567 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 33891 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 9476 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 959382 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 633790 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1636539 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 33891 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 9476 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 959382 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 633790 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1636539 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000325 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000317 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012145 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026207 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.015694 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986102 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986102 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.540836 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.540836 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000324 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000316 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012147 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.226408 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.094811 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000324 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000316 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012147 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.226408 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.094811 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 71840.909091 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 79583.333333 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71242.942252 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75007.464525 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72995.507838 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 119.795462 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 119.795462 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70027.594200 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70027.594200 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 71840.909091 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 79583.333333 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71242.942252 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70379.754617 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70444.865605 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 71840.909091 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 79583.333333 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71242.942252 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70379.754617 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70444.865605 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.540855 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.540855 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000325 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000317 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012145 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.226424 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.094817 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000325 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000317 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012145 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.226424 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.094817 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 71886.363636 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 79416.666667 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71709.298747 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74883.129681 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73186.932658 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 120.139223 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 120.139223 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70081.790210 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70081.790210 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 71886.363636 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 79416.666667 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71709.298747 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70421.318400 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70518.312352 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 71886.363636 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 79416.666667 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71709.298747 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70421.318400 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70518.312352 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1232,88 +1259,88 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 40 system.cpu.l2cache.overall_mshr_hits::total 55 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 10 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 11640 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 11638 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10108 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 21761 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 21759 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2909 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 2909 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133354 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133354 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133357 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133357 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 10 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 11640 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143462 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 155115 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 11638 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143465 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 155116 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 10 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 11640 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143462 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 155115 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 11638 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143465 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 155116 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 596250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 201250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 683475499 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 632292750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1316565749 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29106909 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29106909 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7676486703 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7676486703 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 688774749 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 631278500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1320850749 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29121909 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29121909 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7684221703 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7684221703 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 596250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 201250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 683475499 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8308779453 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8993052452 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 688774749 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8315500203 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9005072452 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 596250 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 201250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 683475499 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8308779453 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8993052452 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 174348000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167014389750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167188737750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17147727018 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17147727018 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 174348000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184162116768 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184336464768 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 688774749 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8315500203 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9005072452 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 174356000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167012344750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167186700750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17146783596 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17146783596 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 174356000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184159128346 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184333484346 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000295 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000316 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012132 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026102 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015655 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000317 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012131 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026104 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015654 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986102 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986102 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540836 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540836 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540855 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540855 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000295 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000316 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012132 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.226345 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.094777 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000317 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012131 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.226360 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.094783 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000295 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000316 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012132 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.226345 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.094777 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000317 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012131 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.226360 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.094783 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58717.826375 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62553.695093 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60501.160287 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10005.812650 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10005.812650 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57564.727740 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57564.727740 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59183.257347 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62453.353779 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60703.651317 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10010.969062 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10010.969062 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57621.434968 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57621.434968 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58717.826375 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57916.238816 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57976.678284 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59183.257347 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57961.873649 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58053.794915 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58717.826375 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57916.238816 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57976.678284 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59183.257347 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57961.873649 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58053.794915 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1323,184 +1350,184 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 633309 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.949942 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 19068560 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 633821 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 30.085087 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 633278 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.949941 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 19068568 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 633790 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 30.086571 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 267154250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.949942 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.949941 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999902 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999902 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 91797001 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 91797001 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 11311240 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11311240 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7209458 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7209458 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 60823 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 60823 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236444 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236444 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 91796938 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 91796938 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 11311263 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11311263 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7209463 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7209463 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 60828 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 60828 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236419 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236419 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 247594 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247594 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 18520698 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18520698 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18581521 # number of overall hits -system.cpu.dcache.overall_hits::total 18581521 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 573261 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 573261 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3012484 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3012484 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 126501 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 126501 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 12988 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 12988 # number of LoadLockedReq misses +system.cpu.dcache.demand_hits::cpu.data 18520726 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18520726 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18581554 # number of overall hits +system.cpu.dcache.overall_hits::total 18581554 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 573243 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 573243 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3012489 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3012489 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 126499 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 126499 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 12987 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 12987 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3585745 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3585745 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3712246 # number of overall misses -system.cpu.dcache.overall_misses::total 3712246 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7216358166 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7216358166 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 126016512064 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 126016512064 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 178185500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 178185500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 3585732 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3585732 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3712231 # number of overall misses +system.cpu.dcache.overall_misses::total 3712231 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7223298916 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7223298916 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 126143348315 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 126143348315 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 177246500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 177246500 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 26000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 133232870230 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 133232870230 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 133232870230 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 133232870230 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 11884501 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 11884501 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10221942 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10221942 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 187324 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 187324 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 249432 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 249432 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 133366647231 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 133366647231 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 133366647231 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 133366647231 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 11884506 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 11884506 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10221952 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10221952 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 187327 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 187327 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 249406 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 249406 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247596 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247596 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 22106443 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 22106443 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 22293767 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 22293767 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.048236 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.048236 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 22106458 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 22106458 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 22293785 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 22293785 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.048234 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.048234 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.294708 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.294708 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.675306 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.675306 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052070 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052070 # miss rate for LoadLockedReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.675284 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.675284 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052072 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052072 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000008 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.162204 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.162204 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.166515 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.166515 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12588.259390 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12588.259390 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41831.429499 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41831.429499 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13719.240838 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13719.240838 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.162203 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.162203 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.166514 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.166514 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12600.762532 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12600.762532 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41873.463543 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41873.463543 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13647.994148 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13647.994148 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37156.259084 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37156.259084 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35890.097324 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35890.097324 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 18826 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1227 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.343113 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37193.701936 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37193.701936 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35926.279165 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35926.279165 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 17394 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 459 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1226 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.187602 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 459 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 599976 # number of writebacks -system.cpu.dcache.writebacks::total 599976 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 271755 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 271755 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2763119 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2763119 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 599947 # number of writebacks +system.cpu.dcache.writebacks::total 599947 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 271762 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 271762 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2763128 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2763128 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1233 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 1233 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3034874 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3034874 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3034874 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3034874 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 301506 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 301506 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249365 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249365 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 74145 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 74145 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11755 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11755 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 3034890 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3034890 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3034890 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3034890 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 301481 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 301481 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249361 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249361 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 74144 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 74144 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11754 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11754 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 550871 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 550871 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 625016 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 625016 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3569781578 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3569781578 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10783879319 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10783879319 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1231283000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1231283000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 140188500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 140188500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 550842 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 550842 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 624986 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 624986 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3569589078 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3569589078 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10791306319 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10791306319 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1230913250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1230913250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 139261250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 139261250 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14353660897 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14353660897 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15584943897 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15584943897 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182408022250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182408022250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26599942575 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26599942575 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209007964825 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209007964825 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025370 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025370 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14360895397 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14360895397 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15591808647 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15591808647 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182406065750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182406065750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26598901323 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26598901323 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209004967073 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209004967073 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025368 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025368 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024395 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024395 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.395812 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.395812 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047127 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047127 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.395800 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.395800 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047128 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047128 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000008 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024919 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.024919 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028035 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028035 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11839.835950 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11839.835950 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43245.360492 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43245.360492 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16606.419853 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16606.419853 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11925.861336 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11925.861336 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024918 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024918 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028034 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028034 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11840.179242 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11840.179242 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43275.838319 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43275.838319 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16601.656911 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16601.656911 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11847.987919 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11847.987919 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26056.301561 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26056.301561 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24935.271892 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24935.271892 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26070.806868 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26070.806868 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24947.452658 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24947.452658 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1524,16 +1551,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736929447540 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1736929447540 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736929447540 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1736929447540 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736978742288 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1736978742288 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736978742288 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1736978742288 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83187 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83186 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index b3c80425c..7c26dcd5b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,166 +1,192 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.621647 # Number of seconds simulated -sim_ticks 2621647051000 # Number of ticks simulated -final_tick 2621647051000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.607932 # Number of seconds simulated +sim_ticks 2607931908500 # Number of ticks simulated +final_tick 2607931908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56801 # Simulator instruction rate (inst/s) -host_op_rate 68443 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2377539464 # Simulator tick rate (ticks/s) -host_mem_usage 411700 # Number of bytes of host memory used -host_seconds 1102.67 # Real time elapsed on the host -sim_insts 62632896 # Number of instructions simulated -sim_ops 75470296 # Number of ops (including micro ops) simulated +host_inst_rate 43892 # Simulator instruction rate (inst/s) +host_op_rate 52863 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1823841209 # Simulator tick rate (ticks/s) +host_mem_usage 431084 # Number of bytes of host memory used +host_seconds 1429.91 # Real time elapsed on the host +sim_insts 62761278 # Number of instructions simulated +sim_ops 75589768 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.realview.nvmem.bytes_read::cpu0.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 128 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 176 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 128 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 176 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 3 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 8 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 18 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 49 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 67 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 18 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 49 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 67 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 18 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 49 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 67 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 516048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6568572 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 301968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2981560 # Number of bytes read from this memory -system.physmem.bytes_read::total 131479316 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 516048 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 301968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 818016 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4189696 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 3029096 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 7218832 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 122112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 457724 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 4608960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 71568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 618744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 5382208 # Number of bytes read from this memory +system.physmem.bytes_read::total 132372740 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 122112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 71568 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 193680 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4391552 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory +system.physmem.bytes_written::total 7420688 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10590 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 102693 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4761 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 46605 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15303475 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 65464 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 757274 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 822748 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46196351 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 171 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 196841 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2505513 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 115183 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1137285 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50151418 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 196841 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 115183 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 312024 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1598116 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 1155417 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 15 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2753548 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1598116 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46196351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 171 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 196841 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3660931 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 115183 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1137300 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 52904966 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15303475 # Number of read requests accepted -system.physmem.writeReqs 822748 # Number of write requests accepted -system.physmem.readBursts 15303475 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 822748 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 977402304 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 2020096 # Total number of bytes read from write queue -system.physmem.bytesWritten 7239040 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131479316 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7218832 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 31564 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 709609 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 12033 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 956536 # Per bank write bursts -system.physmem.perBankRdBursts::1 956505 # Per bank write bursts -system.physmem.perBankRdBursts::2 953083 # Per bank write bursts -system.physmem.perBankRdBursts::3 951219 # Per bank write bursts -system.physmem.perBankRdBursts::4 959451 # Per bank write bursts -system.physmem.perBankRdBursts::5 955886 # Per bank write bursts -system.physmem.perBankRdBursts::6 953593 # Per bank write bursts -system.physmem.perBankRdBursts::7 950807 # Per bank write bursts -system.physmem.perBankRdBursts::8 956024 # Per bank write bursts -system.physmem.perBankRdBursts::9 956507 # Per bank write bursts -system.physmem.perBankRdBursts::10 953309 # Per bank write bursts -system.physmem.perBankRdBursts::11 950948 # Per bank write bursts -system.physmem.perBankRdBursts::12 956403 # Per bank write bursts -system.physmem.perBankRdBursts::13 956390 # Per bank write bursts -system.physmem.perBankRdBursts::14 954120 # Per bank write bursts -system.physmem.perBankRdBursts::15 951130 # Per bank write bursts -system.physmem.perBankWrBursts::0 7301 # Per bank write bursts -system.physmem.perBankWrBursts::1 7301 # Per bank write bursts -system.physmem.perBankWrBursts::2 6635 # Per bank write bursts -system.physmem.perBankWrBursts::3 6826 # Per bank write bursts -system.physmem.perBankWrBursts::4 7245 # Per bank write bursts -system.physmem.perBankWrBursts::5 6961 # Per bank write bursts -system.physmem.perBankWrBursts::6 7187 # Per bank write bursts -system.physmem.perBankWrBursts::7 6869 # Per bank write bursts -system.physmem.perBankWrBursts::8 6823 # Per bank write bursts -system.physmem.perBankWrBursts::9 7301 # Per bank write bursts -system.physmem.perBankWrBursts::10 6956 # Per bank write bursts -system.physmem.perBankWrBursts::11 6738 # Per bank write bursts -system.physmem.perBankWrBursts::12 7232 # Per bank write bursts -system.physmem.perBankWrBursts::13 7102 # Per bank write bursts -system.physmem.perBankWrBursts::14 7378 # Per bank write bursts -system.physmem.perBankWrBursts::15 7255 # Per bank write bursts +system.physmem.num_reads::cpu0.dtb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 4443 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 7211 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 72015 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 8 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1161 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9686 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 84097 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15317443 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 68618 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory +system.physmem.num_writes::total 825902 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46439298 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 74 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 74 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 46823 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 175512 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 1767285 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 196 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 27442 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 237255 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 2063784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50757744 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 46823 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 27442 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 74266 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1683921 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6519 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1154990 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2845430 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1683921 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46439298 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 74 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 46823 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 182031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 1767285 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 196 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 27442 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1392245 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 2063784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53603174 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15317443 # Number of read requests accepted +system.physmem.writeReqs 825902 # Number of write requests accepted +system.physmem.readBursts 15317443 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 825902 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 976329024 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3987328 # Total number of bytes read from write queue +system.physmem.bytesWritten 7443968 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 132372740 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7420688 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 62302 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 709563 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 16003 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 957415 # Per bank write bursts +system.physmem.perBankRdBursts::1 954356 # Per bank write bursts +system.physmem.perBankRdBursts::2 951532 # Per bank write bursts +system.physmem.perBankRdBursts::3 951095 # Per bank write bursts +system.physmem.perBankRdBursts::4 960453 # Per bank write bursts +system.physmem.perBankRdBursts::5 954333 # Per bank write bursts +system.physmem.perBankRdBursts::6 950562 # Per bank write bursts +system.physmem.perBankRdBursts::7 950350 # Per bank write bursts +system.physmem.perBankRdBursts::8 957423 # Per bank write bursts +system.physmem.perBankRdBursts::9 955252 # Per bank write bursts +system.physmem.perBankRdBursts::10 950399 # Per bank write bursts +system.physmem.perBankRdBursts::11 949996 # Per bank write bursts +system.physmem.perBankRdBursts::12 957025 # Per bank write bursts +system.physmem.perBankRdBursts::13 954231 # Per bank write bursts +system.physmem.perBankRdBursts::14 950565 # Per bank write bursts +system.physmem.perBankRdBursts::15 950154 # Per bank write bursts +system.physmem.perBankWrBursts::0 7537 # Per bank write bursts +system.physmem.perBankWrBursts::1 7271 # Per bank write bursts +system.physmem.perBankWrBursts::2 7519 # Per bank write bursts +system.physmem.perBankWrBursts::3 7339 # Per bank write bursts +system.physmem.perBankWrBursts::4 7525 # Per bank write bursts +system.physmem.perBankWrBursts::5 7506 # Per bank write bursts +system.physmem.perBankWrBursts::6 7304 # Per bank write bursts +system.physmem.perBankWrBursts::7 7173 # Per bank write bursts +system.physmem.perBankWrBursts::8 7520 # Per bank write bursts +system.physmem.perBankWrBursts::9 7613 # Per bank write bursts +system.physmem.perBankWrBursts::10 6934 # Per bank write bursts +system.physmem.perBankWrBursts::11 6533 # Per bank write bursts +system.physmem.perBankWrBursts::12 7225 # Per bank write bursts +system.physmem.perBankWrBursts::13 7011 # Per bank write bursts +system.physmem.perBankWrBursts::14 7249 # Per bank write bursts +system.physmem.perBankWrBursts::15 7053 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2621645657000 # Total gap between requests +system.physmem.totGap 2607930021000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 59 # Read request sizes (log2) system.physmem.readPktSize::3 15138841 # Read request sizes (log2) -system.physmem.readPktSize::4 3426 # Read request sizes (log2) +system.physmem.readPktSize::4 3437 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 161149 # Read request sizes (log2) +system.physmem.readPktSize::6 175106 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 757284 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 65464 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1118217 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 965108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 965171 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1074431 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 973448 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1034951 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2682221 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2590422 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3372339 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 127125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 110466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 101918 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 97549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20170 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 19294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 19015 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 68618 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1022635 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1020084 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 981701 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1092290 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 979402 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1043990 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2669652 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2569034 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3344990 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 138441 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 119851 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 110072 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 105368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19798 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18864 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18580 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 86 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 1 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -176,46 +202,46 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6660 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6637 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4905 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6453 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7978 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see @@ -225,558 +251,604 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1014826 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 970.256324 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 901.955292 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 206.811149 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24748 2.44% 2.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 20792 2.05% 4.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9109 0.90% 5.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2441 0.24% 5.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2631 0.26% 5.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1759 0.17% 6.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9074 0.89% 6.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1088 0.11% 7.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 943184 92.94% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1014826 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6619 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2307.281009 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 96810.313262 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-262143 6612 99.89% 99.89% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::262144-524287 1 0.02% 99.91% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::524288-786431 1 0.02% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.02% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 2 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.31072e+06-1.57286e+06 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::7.34003e+06-7.60218e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6619 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6619 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.088684 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.037372 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.359683 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3686 55.69% 55.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 52 0.79% 56.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1827 27.60% 84.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 927 14.01% 98.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 37 0.56% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 27 0.41% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 28 0.42% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 21 0.32% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 11 0.17% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6619 # Writes before turning the bus around for reads -system.physmem.totQLat 395207982750 # Total ticks spent queuing -system.physmem.totMemAccLat 681556314000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76359555000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25878.10 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1020956 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 963.580205 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 884.289338 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 220.002398 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 33463 3.28% 3.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19295 1.89% 5.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8776 0.86% 6.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2662 0.26% 6.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3249 0.32% 6.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2138 0.21% 6.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8494 0.83% 7.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1074 0.11% 7.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 941805 92.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1020956 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6723 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2269.096237 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 97829.440322 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-262143 6717 99.91% 99.91% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::262144-524287 1 0.01% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::524288-786431 2 0.03% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2.3593e+06-2.62144e+06 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::7.34003e+06-7.60218e+06 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6723 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6723 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.300610 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.224413 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.695658 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3618 53.82% 53.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 52 0.77% 54.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1623 24.14% 78.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 981 14.59% 93.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 153 2.28% 95.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 115 1.71% 97.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 65 0.97% 98.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 63 0.94% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 23 0.34% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 16 0.24% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 7 0.10% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 4 0.06% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6723 # Writes before turning the bus around for reads +system.physmem.totQLat 400005056750 # Total ticks spent queuing +system.physmem.totMemAccLat 686038950500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76275705000 # Total ticks spent in databus transfers +system.physmem.avgQLat 26221.00 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44628.10 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 372.82 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.76 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 50.15 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.75 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44971.00 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 374.37 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.85 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.76 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.85 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.93 # Data bus utilization in percentage -system.physmem.busUtilRead 2.91 # Data bus utilization in percentage for reads +system.physmem.busUtil 2.95 # Data bus utilization in percentage +system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 5.85 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.60 # Average write queue length when enqueuing -system.physmem.readRowHits 14274861 # Number of row buffer hits during reads -system.physmem.writeRowHits 95334 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.47 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.26 # Row buffer hit rate for writes -system.physmem.avgGap 162570.35 # Average gap between requests -system.physmem.pageHitRate 93.40 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2271344460000 # Time in different power states -system.physmem.memoryStateTime::REF 87542520000 # Time in different power states +system.physmem.avgRdQLen 6.13 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.82 # Average write queue length when enqueuing +system.physmem.readRowHits 14262971 # Number of row buffer hits during reads +system.physmem.writeRowHits 87526 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.50 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.23 # Row buffer hit rate for writes +system.physmem.avgGap 161548.30 # Average gap between requests +system.physmem.pageHitRate 93.36 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2277790546750 # Time in different power states +system.physmem.memoryStateTime::REF 87084400000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 262759227500 # Time in different power states +system.physmem.memoryStateTime::ACT 243051888250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.bytes_read::cpu0.inst 48 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 192 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 48 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 192 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 3 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 12 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 18 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 55 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 73 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 18 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 55 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 73 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 18 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 55 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 73 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 53827614 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16353736 # Transaction distribution -system.membus.trans_dist::ReadResp 16353736 # Transaction distribution -system.membus.trans_dist::WriteReq 768463 # Transaction distribution -system.membus.trans_dist::WriteResp 768463 # Transaction distribution -system.membus.trans_dist::Writeback 65464 # Transaction distribution -system.membus.trans_dist::UpgradeReq 28363 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 16887 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12033 # Transaction distribution -system.membus.trans_dist::ReadExReq 137713 # Transaction distribution -system.membus.trans_dist::ReadExResp 137251 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384346 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 24 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10950 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 16496763 # Transaction distribution +system.membus.trans_dist::ReadResp 16496763 # Transaction distribution +system.membus.trans_dist::WriteReq 769202 # Transaction distribution +system.membus.trans_dist::WriteResp 769202 # Transaction distribution +system.membus.trans_dist::Writeback 68618 # Transaction distribution +system.membus.trans_dist::UpgradeReq 58416 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 23667 # Transaction distribution +system.membus.trans_dist::UpgradeResp 16003 # Transaction distribution +system.membus.trans_dist::ReadExReq 15703 # Transaction distribution +system.membus.trans_dist::ReadExResp 8933 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384368 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13898 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2058 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1967095 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4364477 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2050 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2045296 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4445638 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34642109 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392641 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 192 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 21900 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4116 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17587620 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 20006477 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 141117005 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 141117005 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1559281500 # Layer occupancy (ticks) +system.membus.pkt_count::total 34723270 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2392677 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 176 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27796 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4100 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18682900 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 21107657 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 142218185 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 72850 # Total snoops (count) +system.membus.snoop_fanout::samples 332577 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 332577 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 332577 # Request fanout histogram +system.membus.reqLayer0.occupancy 1569259492 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer1.occupancy 14500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 13500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 9763000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11956494 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1786500 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1552000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17605374000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17698783999 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4830238688 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5007965719 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37428300697 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37372928091 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 71035 # number of replacements -system.l2c.tags.tagsinuse 52844.560777 # Cycle average of tags in use -system.l2c.tags.total_refs 1830685 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 136207 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.440462 # Average number of references to valid blocks. +system.l2c.tags.replacements 91666 # number of replacements +system.l2c.tags.tagsinuse 54831.199714 # Cycle average of tags in use +system.l2c.tags.total_refs 387443 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 156491 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.475817 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37821.803984 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.739512 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000522 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5415.027395 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6377.582658 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.953654 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2390.174334 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 833.278718 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.577115 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000088 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.082627 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.097314 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.036471 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.012715 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.806344 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65168 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3098 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8323 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53527 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994385 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 18484845 # Number of tag accesses -system.l2c.tags.data_accesses 18484845 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 20873 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 5362 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 546777 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 243323 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 15709 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 4324 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 434561 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 119239 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1390168 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 583269 # number of Writeback hits -system.l2c.Writeback_hits::total 583269 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1334 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 378 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1712 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 271 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 117 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 388 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 65538 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 44550 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 110088 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 20873 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 5362 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 546777 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 308861 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 15709 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4324 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 434561 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 163789 # number of demand (read+write) hits -system.l2c.demand_hits::total 1500256 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 20873 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 5362 # number of overall hits -system.l2c.overall_hits::cpu0.inst 546777 # number of overall hits -system.l2c.overall_hits::cpu0.data 308861 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 15709 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4324 # number of overall hits -system.l2c.overall_hits::cpu1.inst 434561 # number of overall hits -system.l2c.overall_hits::cpu1.data 163789 # number of overall hits -system.l2c.overall_hits::total 1500256 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 8 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7230 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 9897 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 4714 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 2106 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23958 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 4509 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3863 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8372 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 516 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 628 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1144 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 94130 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 45638 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 139768 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7230 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 104027 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 4714 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 47744 # number of demand (read+write) misses -system.l2c.demand_misses::total 163726 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7230 # number of overall misses -system.l2c.overall_misses::cpu0.data 104027 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 4714 # number of overall misses -system.l2c.overall_misses::cpu1.data 47744 # number of overall misses -system.l2c.overall_misses::total 163726 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 551500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 150000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 522312750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 733828247 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 83500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 334292999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 165107999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1756326995 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 11295015 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 12799954 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 24094969 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1793923 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1118952 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 2912875 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 6378706625 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 3294603599 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9673310224 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 551500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 150000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 522312750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 7112534872 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 83500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 334292999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 3459711598 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 11429637219 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 551500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 150000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 522312750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 7112534872 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 83500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 334292999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 3459711598 # number of overall miss cycles -system.l2c.overall_miss_latency::total 11429637219 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 20881 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 5364 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 554007 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 253220 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 15710 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 4324 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 439275 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 121345 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1414126 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 583269 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 583269 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 5843 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 4241 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 10084 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 787 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 745 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1532 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 159668 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 90188 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 249856 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 20881 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 5364 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 554007 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 412888 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 15710 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 4324 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 439275 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 211533 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1663982 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 20881 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 5364 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 554007 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 412888 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 15710 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 4324 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 439275 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 211533 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1663982 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000383 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000373 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.013050 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.039085 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000064 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010731 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.017355 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016942 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.771693 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.910870 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.830226 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.655654 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.842953 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.746736 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.589536 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.506032 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.559394 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000383 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000373 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.013050 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.251950 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000064 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010731 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.225705 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.098394 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000383 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000373 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.013050 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.251950 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000064 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010731 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.225705 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.098394 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 68937.500000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72242.427386 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 74146.534000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 83500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70914.934026 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 78398.859924 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 73308.581476 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2504.993347 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3313.475019 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2878.042164 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3476.594961 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1781.770701 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 2546.219406 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 67764.863752 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72189.920658 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 69209.763494 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 68937.500000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 72242.427386 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 68372.007959 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 83500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 70914.934026 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 72463.798551 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 69809.542889 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 68937.500000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 72242.427386 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 68372.007959 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 83500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 70914.934026 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 72463.798551 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 69809.542889 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.tags.occ_blocks::writebacks 7736.589041 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.331203 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 1.025467 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 672.803532 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 1677.780077 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 24285.244228 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.407687 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 678.722766 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3493.963497 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 16278.332216 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.118051 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000020 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.010266 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.025601 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.370563 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000083 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.010356 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.053314 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.248388 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.836658 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 52524 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 12291 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 158 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 5897 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 46469 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 327 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2272 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 9679 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.801453 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000153 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.187546 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5049935 # Number of tag accesses +system.l2c.tags.data_accesses 5049935 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 116 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 44 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 4746 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 14884 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 72204 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 168 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 72 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 7407 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 16636 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 74707 # number of ReadReq hits +system.l2c.ReadReq_hits::total 190984 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 213987 # number of Writeback hits +system.l2c.Writeback_hits::total 213987 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 3107 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 2045 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 5152 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 90 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 245 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 335 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 1803 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 2746 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 4549 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 116 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 44 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 4746 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 16687 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 72204 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 168 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 72 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 7407 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 19382 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 74707 # number of demand (read+write) hits +system.l2c.demand_hits::total 195533 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 116 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 44 # number of overall hits +system.l2c.overall_hits::cpu0.inst 4746 # number of overall hits +system.l2c.overall_hits::cpu0.data 16687 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 72204 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 168 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 72 # number of overall hits +system.l2c.overall_hits::cpu1.inst 7407 # number of overall hits +system.l2c.overall_hits::cpu1.data 19382 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 74707 # number of overall hits +system.l2c.overall_hits::total 195533 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 3 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 1063 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 3259 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 72015 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 8 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1104 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4621 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 84097 # number of ReadReq misses +system.l2c.ReadReq_misses::total 166173 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 7830 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 5610 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 13440 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 1272 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1187 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2459 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 3945 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 5092 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 9037 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 3 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 1063 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 7204 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 72015 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 8 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1104 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 9713 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 84097 # number of demand (read+write) misses +system.l2c.demand_misses::total 175210 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 3 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses +system.l2c.overall_misses::cpu0.inst 1063 # number of overall misses +system.l2c.overall_misses::cpu0.data 7204 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 72015 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 8 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1104 # number of overall misses +system.l2c.overall_misses::cpu1.data 9713 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 84097 # number of overall misses +system.l2c.overall_misses::total 175210 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 195250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 182000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 88517249 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 251848999 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 6854006378 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 744500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 96486500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 359268498 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 9492494272 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 17143743646 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 12214974 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 6369731 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 18584705 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 508980 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 4358314 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 4867294 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 294129193 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 380271953 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 674401146 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 195250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 182000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 88517249 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 545978192 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 6854006378 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 744500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 96486500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 739540451 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 9492494272 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 17818144792 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 195250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 182000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 88517249 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 545978192 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 6854006378 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 744500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 96486500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 739540451 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 9492494272 # number of overall miss cycles +system.l2c.overall_miss_latency::total 17818144792 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 119 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 47 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 5809 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 18143 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 144219 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 176 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 72 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 8511 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 21257 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 158804 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 357157 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 213987 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 213987 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 10937 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 7655 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18592 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 1362 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1432 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2794 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 5748 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 7838 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 13586 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 119 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 47 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 5809 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 23891 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 144219 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 176 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 72 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 8511 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 29095 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 158804 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 370743 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 119 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 47 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 5809 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 23891 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 144219 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 176 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 72 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 8511 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 29095 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 158804 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 370743 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.025210 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.063830 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.182992 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.179629 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.499345 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.129714 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.217387 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.529565 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.465266 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.715918 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.732854 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.722892 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.933921 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.828911 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.880100 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.686326 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.649656 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.665170 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.025210 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.063830 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.182992 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.301536 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.499345 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.129714 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.333837 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.529565 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.472592 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.025210 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.063830 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.182992 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.301536 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.499345 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.129714 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.333837 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.529565 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.472592 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 65083.333333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 60666.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 83271.165569 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 77277.999079 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 95174.704964 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 93062.500000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 87397.192029 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 77746.915819 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 112875.539817 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 103168.045627 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1560.022222 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1135.424421 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1382.790551 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 400.141509 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 3671.705139 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1979.379423 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 74557.463371 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 74680.273566 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 74626.662167 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 65083.333333 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 60666.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 83271.165569 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 75788.199889 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 95174.704964 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 93062.500000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 87397.192029 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 76139.241326 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 112875.539817 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 101695.935118 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 65083.333333 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 60666.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 83271.165569 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 75788.199889 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 95174.704964 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 93062.500000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 87397.192029 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 76139.241326 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 112875.539817 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 101695.935118 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 369 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 10 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 36.900000 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 65464 # number of writebacks -system.l2c.writebacks::total 65464 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.inst 9 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 28 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 10 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 12 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 28 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 12 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 60 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 28 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 12 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 60 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 7 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 7221 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 9869 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 4704 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 2094 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 23898 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 4509 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 3863 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 8372 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 516 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 628 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1144 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 94130 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 45638 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 139768 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 7 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 7221 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 103999 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 4704 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 47732 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 163666 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 7 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 7221 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 103999 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 4704 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 47732 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 163666 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 395000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 431252250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 608078747 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 71000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 274798249 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 138281999 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1453002245 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 45149974 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 38756824 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 83906798 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5160516 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 6295125 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 11455641 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5201483861 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2728717885 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 7930201746 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 395000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 431252250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 5809562608 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 71000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 274798249 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 2866999884 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 9383203991 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 395000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 431252250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 5809562608 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 71000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 274798249 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 2866999884 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 9383203991 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 176335500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12626197496 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3342000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154644756250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167450631246 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 16805961075 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 475202500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 17281163575 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 176335500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 29432158571 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3342000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 155119958750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 184731794821 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000335 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000373 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013034 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.038974 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000064 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010709 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017257 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.016899 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.771693 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.910870 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.830226 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.655654 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.842953 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.746736 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.589536 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.506032 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.559394 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000335 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000373 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013034 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.251882 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000064 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010709 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.225648 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.098358 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000335 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000373 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013034 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.251882 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000064 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010709 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.225648 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.098358 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56428.571429 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59721.956793 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61615.031614 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 71000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58417.995111 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66037.248806 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 60800.160892 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10013.300954 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10032.830443 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10022.312231 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10024.084395 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10013.672203 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 55258.513343 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59790.479096 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56738.321690 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56428.571429 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59721.956793 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55861.716055 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 71000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58417.995111 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60064.524512 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 57331.418810 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56428.571429 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59721.956793 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55861.716055 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 71000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58417.995111 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60064.524512 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 57331.418810 # average overall mshr miss latency +system.l2c.writebacks::writebacks 68618 # number of writebacks +system.l2c.writebacks::total 68618 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 3 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 1063 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 3259 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 72015 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 8 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 1104 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 4621 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 84097 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 166173 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 7830 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 5610 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 13440 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1272 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1187 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 2459 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 3945 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 5092 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 9037 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 3 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 1063 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 7204 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 72015 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 8 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1104 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 9713 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 84097 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 175210 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 3 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 1063 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 7204 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 72015 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 8 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1104 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 9713 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 84097 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 175210 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 158750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 145000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 75361749 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 211101499 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 5961474378 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 645000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 82874000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 301675998 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 8458010282 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 15091446656 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 79003615 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 56662566 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 135666181 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 12832754 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 11966179 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 24798933 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 244772807 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 316260047 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 561032854 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 158750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 145000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 75361749 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 455874306 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 5961474378 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 645000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 82874000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 617936045 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 8458010282 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 15652479510 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 158750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 145000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 75361749 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 455874306 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 5961474378 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 645000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 82874000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 617936045 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 8458010282 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 15652479510 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 178129250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12343853503 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3278250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154953535743 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167478796746 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1076363997 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16025248776 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 17101612773 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 178129250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13420217500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3278250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 170978784519 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 184580409519 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.025210 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.063830 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.182992 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.179629 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.499345 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.045455 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.129714 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.217387 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.529565 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.465266 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.715918 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.732854 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.722892 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.933921 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.828911 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.880100 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.686326 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.649656 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.665170 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.025210 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.063830 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.182992 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.301536 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.499345 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.045455 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.129714 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.333837 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.529565 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.472592 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.025210 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.063830 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.182992 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.301536 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.499345 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.045455 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.129714 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.333837 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.529565 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.472592 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 52916.666667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48333.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 70895.342427 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 64774.930654 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82781.009206 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 80625 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 75067.028986 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65283.704393 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100574.459041 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 90817.681910 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10089.861430 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10100.279144 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10094.209896 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10088.643082 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10081.026959 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10084.966653 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 62046.338910 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62109.200118 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 62081.758770 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 52916.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48333.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70895.342427 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 63280.719878 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82781.009206 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80625 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75067.028986 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63619.483682 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100574.459041 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 89335.537412 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 52916.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48333.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70895.342427 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 63280.719878 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82781.009206 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80625 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75067.028986 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63619.483682 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100574.459041 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 89335.537412 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -797,69 +869,53 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 57560286 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2682607 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2682607 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 768463 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 768463 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 583269 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 27558 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 17275 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 44833 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 1 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 261997 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 261997 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1115277 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2956767 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 14518 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50368 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 879187 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2909426 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 12099 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 38611 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7976253 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 35510400 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 53724619 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21456 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83524 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 28114656 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 29015778 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 17296 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 62840 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 146550569 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 146550569 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4352184 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4888594820 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2503079453 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2482730980 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::ReadReq 1650974 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1650974 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 769202 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 769202 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 213987 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 63464 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 24002 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 87466 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 45 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 23286 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 23286 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 760669 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4337396 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5098065 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 18146443 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 24785598 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 42932041 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 177868 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 783993 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 783993 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 783993 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2614417508 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 1150691896 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 2659939258 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 9171959 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 29595779 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 1980581418 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 2244583247 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer8.occupancy 7797450 # Layer occupancy (ticks) -system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer9.occupancy 22968355 # Layer occupancy (ticks) -system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 47108999 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16322906 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322906 # Transaction distribution -system.iobus.trans_dist::WriteReq 8083 # Transaction distribution -system.iobus.trans_dist::WriteResp 8083 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30944 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8814 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 16322916 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322916 # Transaction distribution +system.iobus.trans_dist::WriteReq 8084 # Transaction distribution +system.iobus.trans_dist::WriteResp 8084 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8832 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1034 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 736 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 740 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -876,51 +932,50 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2384346 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2384368 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32661978 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40713 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 17628 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2068 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2392641 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123503169 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123503169 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21713000 # Layer occupancy (ticks) +system.iobus.pkt_count::total 32662000 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40715 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17664 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 394 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 2392677 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 123503205 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 21715000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4413000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4422000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 523000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 522000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 440000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 442000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) @@ -954,21 +1009,21 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2376263000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2376284000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38168032303 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38188943909 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 8682194 # Number of BP lookups -system.cpu0.branchPred.condPredicted 6490987 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 415813 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 5217710 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4131218 # Number of BTB hits +system.cpu0.branchPred.lookups 6445077 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4515785 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 302094 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3732049 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2838132 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 79.176842 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 908190 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 19748 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 76.047555 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 777958 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 15130 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -992,25 +1047,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 10917771 # DTB read hits -system.cpu0.dtb.read_misses 23643 # DTB read misses -system.cpu0.dtb.write_hits 7767808 # DTB write hits -system.cpu0.dtb.write_misses 8146 # DTB write misses +system.cpu0.dtb.read_hits 6738270 # DTB read hits +system.cpu0.dtb.read_misses 20792 # DTB read misses +system.cpu0.dtb.write_hits 5108254 # DTB write hits +system.cpu0.dtb.write_misses 4938 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1721 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 163 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 270 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1733 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 361 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 194 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 598 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 10941414 # DTB read accesses -system.cpu0.dtb.write_accesses 7775954 # DTB write accesses +system.cpu0.dtb.perms_faults 640 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 6759062 # DTB read accesses +system.cpu0.dtb.write_accesses 5113192 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 18685579 # DTB hits -system.cpu0.dtb.misses 31789 # DTB misses -system.cpu0.dtb.accesses 18717368 # DTB accesses +system.cpu0.dtb.hits 11846524 # DTB hits +system.cpu0.dtb.misses 25730 # DTB misses +system.cpu0.dtb.accesses 11872254 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1032,8 +1087,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 16449037 # ITB inst hits -system.cpu0.itb.inst_misses 5743 # ITB inst misses +system.cpu0.itb.inst_hits 11251934 # ITB inst hits +system.cpu0.itb.inst_misses 5844 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1042,593 +1097,996 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1206 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1215 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 2114 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 2392 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 16454780 # ITB inst accesses -system.cpu0.itb.hits 16449037 # DTB hits -system.cpu0.itb.misses 5743 # DTB misses -system.cpu0.itb.accesses 16454780 # DTB accesses -system.cpu0.numCycles 110984158 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 11257778 # ITB inst accesses +system.cpu0.itb.hits 11251934 # DTB hits +system.cpu0.itb.misses 5844 # DTB misses +system.cpu0.itb.accesses 11257778 # DTB accesses +system.cpu0.numCycles 70547986 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 29010417 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 51007104 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 8682194 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 5039408 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 76702951 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1090474 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 80643 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 23949 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 71996 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1961272 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 16450117 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 242573 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2510 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 108396478 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.561251 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.057421 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 4766943 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 34365037 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6445077 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3616090 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 61724532 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 827468 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 75473 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 31308 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 103372 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 2299403 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 9118 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 11252710 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 69213 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 1641 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 69423883 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.597378 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.081788 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 80471532 74.24% 74.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 9354408 8.63% 82.87% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 4228353 3.90% 86.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 14342185 13.23% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 50336190 72.51% 72.51% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 6591848 9.50% 82.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 2607109 3.76% 85.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 9888736 14.24% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 108396478 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.078229 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.459589 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 24273364 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 59696324 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 21865637 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 2148424 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 412729 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1100967 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 134603 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 56048449 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 1161275 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 412729 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 26181144 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 23163659 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 11818847 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 22001270 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 24818829 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 54863842 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 371818 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 4330145 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2622839 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 9842391 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 13156385 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 58083982 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 254404471 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 69151408 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 3820 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 54276662 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 3807314 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 540800 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 442723 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4591136 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9492850 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 8297955 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 506397 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 589876 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 53569882 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 859573 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 55433156 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 105167 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 2762956 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 5503873 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 84823 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 108396478 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.511393 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 0.864824 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 69423883 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.091357 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.487116 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 6423281 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 48508889 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 12244404 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1928072 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 319237 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 872011 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 96101 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 34918059 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 1200237 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 319237 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 8391286 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 22294228 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 11033133 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 12128468 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 15257531 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 33562016 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 347139 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 4725852 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2951017 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 10590659 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 2752771 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 34856617 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 154488080 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 39935090 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 3818 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30135138 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4721470 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 454498 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 374192 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4720858 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 6116778 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5560819 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 585791 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 708239 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 32317524 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 796272 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 32794597 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 169276 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 3620256 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 7615411 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 145849 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 69423883 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.472382 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 0.871380 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 74367725 68.61% 68.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 17769290 16.39% 85.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 11558620 10.66% 95.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 4256755 3.93% 99.59% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 444079 0.41% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 50273243 72.41% 72.41% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9200980 13.25% 85.67% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 6622047 9.54% 95.21% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2961360 4.27% 99.47% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 365822 0.53% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 431 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 108396478 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 69423883 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 3788078 33.87% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 172 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 3595287 32.14% 66.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 3801407 33.99% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 2899348 33.55% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 364 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 2954493 34.19% 67.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 2788370 32.26% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 14948 0.03% 0.03% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 35826739 64.63% 64.66% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 64782 0.12% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 722 0.00% 64.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 64.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 64.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 64.78% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 11302035 20.39% 85.16% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 8223930 14.84% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 14544 0.04% 0.04% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 20241553 61.72% 61.77% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 42703 0.13% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 684 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 7058068 21.52% 83.42% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5437045 16.58% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 55433156 # Type of FU issued -system.cpu0.iq.rate 0.499469 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 11184944 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.201774 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 230540772 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 57191232 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 52885161 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12129 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4604 # Number of floating instruction queue writes +system.cpu0.iq.FU_type_0::total 32794597 # Type of FU issued +system.cpu0.iq.rate 0.464855 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 8642575 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.263537 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 143812961 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 36735702 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 31078347 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 11966 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4590 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 3838 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 66595213 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 7939 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 146965 # Number of loads that had data forwarded from stores +system.cpu0.iq.int_alu_accesses 41415013 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 7615 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 165813 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 634189 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 503 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 3442 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 242149 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 774144 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 762 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 6359 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 332945 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 1082260 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 1003693 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 1087991 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 169554 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 412729 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 7302695 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 6441595 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 54523303 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 319237 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 7637691 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 6668537 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 33216242 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9492850 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 8297955 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 524870 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 12318 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 6420937 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 3442 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 134210 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 165432 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 299642 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 55026621 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 11133456 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 374843 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 6116778 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5560819 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 485296 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 10796 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 6648479 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 6359 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 101328 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 128415 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 229743 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 32427250 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 6903411 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 342013 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 93848 # number of nop insts executed -system.cpu0.iew.exec_refs 19301977 # number of memory reference insts executed -system.cpu0.iew.exec_branches 7332190 # Number of branches executed -system.cpu0.iew.exec_stores 8168521 # Number of stores executed -system.cpu0.iew.exec_rate 0.495806 # Inst execution rate -system.cpu0.iew.wb_sent 54039254 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 52888999 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 25110485 # num instructions producing a value -system.cpu0.iew.wb_consumers 37735585 # num instructions consuming a value +system.cpu0.iew.exec_nop 102446 # number of nop insts executed +system.cpu0.iew.exec_refs 12283212 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4700114 # Number of branches executed +system.cpu0.iew.exec_stores 5379801 # Number of stores executed +system.cpu0.iew.exec_rate 0.459648 # Inst execution rate +system.cpu0.iew.wb_sent 32232102 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 31082185 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 15739944 # num instructions producing a value +system.cpu0.iew.wb_consumers 27168343 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.476545 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.665433 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.440582 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.579349 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 2480238 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 774750 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 283305 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 107840192 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.477624 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.224539 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 3250105 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 650423 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 207597 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 68788504 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.427377 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.179796 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 82912194 76.88% 76.88% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 14339479 13.30% 90.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 5152045 4.78% 94.96% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1572745 1.46% 96.42% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1370622 1.27% 97.69% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 690625 0.64% 98.33% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 401555 0.37% 98.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 407085 0.38% 99.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 993842 0.92% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 54880088 79.78% 79.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7965099 11.58% 91.36% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2563469 3.73% 95.09% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1116854 1.62% 96.71% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 779155 1.13% 97.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 426783 0.62% 98.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 259327 0.38% 98.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 232321 0.34% 99.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 565408 0.82% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 107840192 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 43173906 # Number of instructions committed -system.cpu0.commit.committedOps 51507078 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 68788504 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 24068410 # Number of instructions committed +system.cpu0.commit.committedOps 29398607 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 16914467 # Number of memory references committed -system.cpu0.commit.loads 8858661 # Number of loads committed -system.cpu0.commit.membars 263890 # Number of memory barriers committed -system.cpu0.commit.branches 7043091 # Number of branches committed +system.cpu0.commit.refs 10570507 # Number of memory references committed +system.cpu0.commit.loads 5342633 # Number of loads committed +system.cpu0.commit.membars 231974 # Number of memory barriers committed +system.cpu0.commit.branches 4351471 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 45505753 # Number of committed integer instructions. -system.cpu0.commit.function_calls 666034 # Number of function calls committed. +system.cpu0.commit.int_insts 25743783 # Number of committed integer instructions. +system.cpu0.commit.function_calls 499778 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 34530023 67.04% 67.04% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 61866 0.12% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 722 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 8858661 17.20% 84.36% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 8055806 15.64% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 18787662 63.91% 63.91% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 39754 0.14% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 684 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 5342633 18.17% 82.22% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5227874 17.78% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 51507078 # Class of committed instruction -system.cpu0.commit.bw_lim_events 993842 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 29398607 # Class of committed instruction +system.cpu0.commit.bw_lim_events 565408 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 159811836 # The number of ROB reads -system.cpu0.rob.rob_writes 108530018 # The number of ROB writes -system.cpu0.timesIdled 338876 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 2587680 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5132257518 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 43093164 # Number of Instructions Simulated -system.cpu0.committedOps 51426336 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.575447 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.575447 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.388282 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.388282 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 67127966 # number of integer regfile reads -system.cpu0.int_regfile_writes 33211893 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3352 # number of floating regfile reads +system.cpu0.rob.rob_reads 99997744 # The number of ROB reads +system.cpu0.rob.rob_writes 65895627 # The number of ROB writes +system.cpu0.timesIdled 89184 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 1124103 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5145325170 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23987668 # Number of Instructions Simulated +system.cpu0.committedOps 29317865 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.941011 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.941011 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.340019 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.340019 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 37156240 # number of integer regfile reads +system.cpu0.int_regfile_writes 18851805 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3262 # number of floating regfile reads system.cpu0.fp_regfile_writes 840 # number of floating regfile writes -system.cpu0.cc_regfile_reads 191848471 # number of cc regfile reads -system.cpu0.cc_regfile_writes 22040987 # number of cc regfile writes -system.cpu0.misc_regfile_reads 169210728 # number of misc regfile reads -system.cpu0.misc_regfile_writes 593502 # number of misc regfile writes -system.cpu0.icache.tags.replacements 554010 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.387606 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 15866984 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 554522 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 28.613804 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 18806389250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.387606 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998804 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998804 # Average percentage of cache occupancy +system.cpu0.cc_regfile_reads 113767432 # number of cc regfile reads +system.cpu0.cc_regfile_writes 12814569 # number of cc regfile writes +system.cpu0.misc_regfile_reads 112163009 # number of misc regfile reads +system.cpu0.misc_regfile_writes 502202 # number of misc regfile writes +system.cpu0.toL2Bus.trans_dist::ReadReq 900797 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 693938 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 10818 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 10818 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 228050 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 268938 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 56335 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 24640 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 62766 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 29 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 45 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 133470 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 124418 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 651974 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 1223749 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 16358 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 46407 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 1938488 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20698608 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 38615195 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 26900 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 80012 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 59420715 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 640729 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 1524410 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.372076 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.483359 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 957213 62.79% 62.79% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 567197 37.21% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 1524410 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 761732905 # Layer occupancy (ticks) +system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.snoopLayer0.occupancy 71201999 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer0.occupancy 488672410 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer1.occupancy 613319434 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer2.occupancy 9639487 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer3.occupancy 26428702 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu0.icache.tags.replacements 322116 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.545879 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 10915164 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 322628 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 33.832042 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6524367000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.545879 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999113 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999113 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 152 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 231 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 17001271 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 17001271 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 15866984 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 15866984 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 15866984 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 15866984 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 15866984 # number of overall hits -system.cpu0.icache.overall_hits::total 15866984 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 579761 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 579761 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 579761 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 579761 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 579761 # number of overall misses -system.cpu0.icache.overall_misses::total 579761 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 8029558142 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 8029558142 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 8029558142 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 8029558142 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 8029558142 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 8029558142 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 16446745 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 16446745 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 16446745 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 16446745 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 16446745 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 16446745 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.035251 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.035251 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.035251 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.035251 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.035251 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.035251 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13849.772824 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13849.772824 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13849.772824 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13849.772824 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13849.772824 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13849.772824 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 739 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 55 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.436364 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.tags.tag_accesses 22821148 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 22821148 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 10915164 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 10915164 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 10915164 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 10915164 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 10915164 # number of overall hits +system.cpu0.icache.overall_hits::total 10915164 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 334091 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 334091 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 334091 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 334091 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 334091 # number of overall misses +system.cpu0.icache.overall_misses::total 334091 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 2863305358 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 2863305358 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 2863305358 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 2863305358 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 2863305358 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 2863305358 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 11249255 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 11249255 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 11249255 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 11249255 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 11249255 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 11249255 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029699 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.029699 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029699 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.029699 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029699 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.029699 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8570.435474 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8570.435474 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8570.435474 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8570.435474 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8570.435474 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8570.435474 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 177531 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 307 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 22346 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 5 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.944643 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 61.400000 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 25235 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 25235 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 25235 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 25235 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 25235 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 25235 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 554526 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 554526 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 554526 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 554526 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 554526 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 554526 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6629844046 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 6629844046 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6629844046 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6629844046 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6629844046 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6629844046 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 226658500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 226658500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 226658500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 226658500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033716 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033716 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033716 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.033716 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033716 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.033716 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11955.875912 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11955.875912 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11955.875912 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11955.875912 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11955.875912 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11955.875912 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 11453 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 11453 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 11453 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 11453 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 11453 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 11453 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 322638 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 322638 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 322638 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 322638 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 322638 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 322638 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 2310628588 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 2310628588 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 2310628588 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 2310628588 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 2310628588 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 2310628588 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 272886999 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 272886999 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 272886999 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 272886999 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028681 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028681 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028681 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.028681 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028681 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.028681 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7161.675277 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7161.675277 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7161.675277 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 7161.675277 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7161.675277 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 7161.675277 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 409126 # number of replacements -system.cpu0.dcache.tags.tagsinuse 483.194796 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 12942599 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 409638 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 31.595211 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 271704250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 483.194796 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.943740 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.943740 # Average percentage of cache occupancy +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 3529222 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 247992 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 2979692 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 86609 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 16144 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 198785 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 261906 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.l2cache.tags.replacements 165160 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15951.411231 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 747099 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 181321 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 4.120311 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 4999805500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 4772.372752 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 11.637155 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.084033 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 735.053900 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1518.442449 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8912.820942 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.291283 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000710 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000066 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.044864 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.092678 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.543995 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.973597 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 7338 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 12 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8811 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 34 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 105 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1027 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5229 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 943 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 485 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1656 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6017 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 598 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.447876 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000732 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.537781 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 15517001 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 15517001 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 19658 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 6554 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 314769 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 162769 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 503750 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 228045 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 228045 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 6593 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 6593 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 622 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 622 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 95529 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 95529 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 19658 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 6554 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 314769 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 258298 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 599279 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 19658 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 6554 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 314769 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 258298 # number of overall hits +system.cpu0.l2cache.overall_hits::total 599279 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 345 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 171 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 7801 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 50805 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 59122 # number of ReadReq misses +system.cpu0.l2cache.Writeback_misses::writebacks 5 # number of Writeback misses +system.cpu0.l2cache.Writeback_misses::total 5 # number of Writeback misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 19680 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 19680 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 10856 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 10856 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 23597 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 23597 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 345 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 171 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 7801 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 74402 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 82719 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 345 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 171 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 7801 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 74402 # number of overall misses +system.cpu0.l2cache.overall_misses::total 82719 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 7498249 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3753000 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 255179729 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 1303745054 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 1570176032 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 310997961 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 310997961 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 212766148 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 212766148 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 609000 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 609000 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 893661798 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 893661798 # number of ReadExReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 7498249 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3753000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 255179729 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 2197406852 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 2463837830 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 7498249 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3753000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 255179729 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 2197406852 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 2463837830 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 20003 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 6725 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 322570 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 213574 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 562872 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 228050 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 228050 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26273 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 26273 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 11478 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 11478 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 119126 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 119126 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 20003 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 6725 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 322570 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 332700 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 681998 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 20003 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 6725 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 322570 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 332700 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 681998 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.017247 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.025428 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.024184 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.237880 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.105036 # miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000022 # miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_miss_rate::total 0.000022 # miss rate for Writeback accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.749058 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.749058 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.945809 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.945809 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.198084 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.198084 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.017247 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.025428 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.024184 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.223631 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.121289 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.017247 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.025428 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.024184 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.223631 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.121289 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 21734.055072 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 21947.368421 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 32711.156134 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 25661.746954 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26558.236054 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 15802.741921 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 15802.741921 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19598.945099 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19598.945099 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 609000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 609000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 37871.839556 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 37871.839556 # average ReadExReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 21734.055072 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 21947.368421 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 32711.156134 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29534.244402 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 29785.633651 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 21734.055072 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 21947.368421 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 32711.156134 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29534.244402 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 29785.633651 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 4781 # number of cycles access was blocked +system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 266 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 17.973684 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.l2cache.fast_writes 0 # number of fast writes performed +system.cpu0.l2cache.cache_copies 0 # number of cache copies performed +system.cpu0.l2cache.writebacks::writebacks 105131 # number of writebacks +system.cpu0.l2cache.writebacks::total 105131 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 1845 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 997 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 2844 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 936 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 936 # number of ReadExReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 1845 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1933 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 3780 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 1845 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1933 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 3780 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 344 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 170 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 5956 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 49808 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 56278 # number of ReadReq MSHR misses +system.cpu0.l2cache.Writeback_mshr_misses::writebacks 5 # number of Writeback MSHR misses +system.cpu0.l2cache.Writeback_mshr_misses::total 5 # number of Writeback MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 198779 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 198779 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 19680 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 19680 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 10856 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 10856 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 22661 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 22661 # number of ReadExReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 344 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 170 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 5956 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 72469 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 78939 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 344 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 170 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 5956 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 72469 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 198779 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 277718 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 5004751 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2550500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 181100759 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 940424592 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1129080602 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 8151036272 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 8151036272 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 354005766 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 354005766 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 158485722 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 158485722 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 490000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 490000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 601346170 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 601346170 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 5004751 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2550500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 181100759 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 1541770762 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 1730426772 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 5004751 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2550500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 181100759 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 1541770762 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 8151036272 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 9881463044 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 244240750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 13865359008 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 14109599758 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 1262027985 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 1262027985 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 244240750 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 15127386993 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15371627743 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.017197 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.025279 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.018464 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.233212 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.099984 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000022 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000022 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.749058 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.749058 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.945809 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.945809 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.190227 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.190227 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.017197 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.025279 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.018464 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.217821 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.115747 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.017197 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.025279 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.018464 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.217821 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.407212 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14548.694767 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15002.941176 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 30406.440396 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 18880.994860 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20062.557340 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41005.520060 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41005.520060 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17988.097866 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17988.097866 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14598.905859 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14598.905859 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 490000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 490000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 26536.612241 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 26536.612241 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14548.694767 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15002.941176 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 30406.440396 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 21274.900468 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 21921.062745 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14548.694767 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15002.941176 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 30406.440396 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 21274.900468 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41005.520060 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35580.923973 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.tags.replacements 297335 # number of replacements +system.cpu0.dcache.tags.tagsinuse 469.059398 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 9029469 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 297847 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 30.315796 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 284699500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 469.059398 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.916132 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.916132 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 346 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63030887 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63030887 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 8037454 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 8037454 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4509267 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4509267 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 46089 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 46089 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156971 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 156971 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 159079 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 159079 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12546721 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12546721 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12592810 # number of overall hits -system.cpu0.dcache.overall_hits::total 12592810 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 406720 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 406720 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 2221250 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2221250 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 92142 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 92142 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10979 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 10979 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7659 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7659 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2627970 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2627970 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2720112 # number of overall misses -system.cpu0.dcache.overall_misses::total 2720112 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5668958645 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5668958645 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 107130503686 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 107130503686 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 114563996 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 114563996 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44413016 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 44413016 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 112799462331 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 112799462331 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 112799462331 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 112799462331 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8444174 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8444174 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 6730517 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6730517 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 138231 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 138231 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 167950 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 167950 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166738 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 166738 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 15174691 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15174691 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 15312922 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15312922 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.048166 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.048166 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.330027 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.330027 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.666580 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.666580 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065371 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065371 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.045934 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.045934 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.173181 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.173181 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.177635 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.177635 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13938.234277 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13938.234277 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 48229.827208 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 48229.827208 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10434.829766 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10434.829766 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5798.800888 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5798.800888 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 42922.659821 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 42922.659821 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41468.683029 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 41468.683029 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 14275 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 1041 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.712776 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 20887113 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 20887113 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 4736171 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 4736171 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3900194 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3900194 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 45240 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 45240 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 135351 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 135351 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 133505 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 133505 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8636365 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8636365 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8681605 # number of overall hits +system.cpu0.dcache.overall_hits::total 8681605 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 322447 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 322447 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 906986 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 906986 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 75027 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 75027 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10798 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 10798 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 11479 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 11479 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1229433 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1229433 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1304460 # number of overall misses +system.cpu0.dcache.overall_misses::total 1304460 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3662752641 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3662752641 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 13080008270 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 13080008270 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 182730500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 182730500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 273467244 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 273467244 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 660000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 660000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 16742760911 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 16742760911 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 16742760911 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 16742760911 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5058618 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 5058618 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4807180 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4807180 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 120267 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 120267 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 146149 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 146149 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144984 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144984 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 9865798 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 9865798 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 9986065 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 9986065 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063742 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063742 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.188673 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.188673 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.623837 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.623837 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.073884 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.073884 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.079174 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.079174 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.124616 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.124616 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.130628 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.130628 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 11359.239320 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 11359.239320 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14421.400408 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 14421.400408 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16922.624560 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16922.624560 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23823.263699 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23823.263699 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13618.278435 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 13618.278435 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12835.012887 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12835.012887 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1895359 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 9 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 100025 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 18.948853 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 375988 # number of writebacks -system.cpu0.dcache.writebacks::total 375988 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 193747 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 193747 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 2045363 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 2045363 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 1054 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1054 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2239110 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2239110 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2239110 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2239110 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 212973 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 212973 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175887 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 175887 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 54623 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 54623 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9925 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9925 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7659 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7659 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 388860 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 388860 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 443483 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 443483 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2487825853 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2487825853 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7369362883 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7369362883 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1035896777 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1035896777 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 82981003 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 82981003 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29093984 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29093984 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9857188736 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9857188736 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10893085513 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10893085513 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13737621002 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13737621002 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 26275689041 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26275689041 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 40013310043 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 40013310043 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025221 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.025221 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026133 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026133 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.395157 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.395157 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059095 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059095 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.045934 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.045934 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025626 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025626 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028961 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028961 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11681.414325 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11681.414325 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41898.280618 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41898.280618 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18964.479743 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18964.479743 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8360.806348 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8360.806348 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3798.666144 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3798.666144 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25348.939814 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25348.939814 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24562.577400 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24562.577400 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 228050 # number of writebacks +system.cpu0.dcache.writebacks::total 228050 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 162419 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 162419 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 762846 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 762846 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 1187 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1187 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 925265 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 925265 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 925265 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 925265 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 160028 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 160028 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 144140 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 144140 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 44124 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 44124 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9611 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9611 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 11479 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 11479 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 304168 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 304168 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 348292 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 348292 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1657269084 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1657269084 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 2153079279 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2153079279 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 708295495 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 708295495 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 147083500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 147083500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 249287756 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 249287756 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 626000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 626000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 3810348363 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 3810348363 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 4518643858 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 4518643858 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 14541407491 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 14541407491 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1345528496 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1345528496 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 15886935987 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 15886935987 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031635 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031635 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029984 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029984 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.366884 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.366884 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.065762 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.065762 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.079174 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.079174 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030831 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.030831 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.034878 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.034878 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10356.119454 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10356.119454 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14937.416949 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14937.416949 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16052.386343 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16052.386343 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15303.662470 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15303.662470 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21716.853036 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21716.853036 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12527.117787 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12527.117787 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12973.722790 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12973.722790 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1636,15 +2094,15 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 5001209 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3530067 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 291977 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 3184313 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 2141032 # Number of BTB hits +system.cpu1.branchPred.lookups 9149866 # Number of BP lookups +system.cpu1.branchPred.condPredicted 6786400 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 422129 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 5825788 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 4286605 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 67.236858 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 582225 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 13211 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 73.579832 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 927303 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 19424 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1668,25 +2126,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 21293354 # DTB read hits -system.cpu1.dtb.read_misses 17527 # DTB read misses -system.cpu1.dtb.write_hits 4063342 # DTB write hits -system.cpu1.dtb.write_misses 3266 # DTB write misses +system.cpu1.dtb.read_hits 25102636 # DTB read hits +system.cpu1.dtb.read_misses 30137 # DTB read misses +system.cpu1.dtb.write_hits 6841685 # DTB write hits +system.cpu1.dtb.write_misses 6769 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1908 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 789 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 274 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1912 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1186 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 224 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 694 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 21310881 # DTB read accesses -system.cpu1.dtb.write_accesses 4066608 # DTB write accesses +system.cpu1.dtb.perms_faults 731 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25132773 # DTB read accesses +system.cpu1.dtb.write_accesses 6848454 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 25356696 # DTB hits -system.cpu1.dtb.misses 20793 # DTB misses -system.cpu1.dtb.accesses 25377489 # DTB accesses +system.cpu1.dtb.hits 31944321 # DTB hits +system.cpu1.dtb.misses 36906 # DTB misses +system.cpu1.dtb.accesses 31981227 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1708,8 +2166,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 8626509 # ITB inst hits -system.cpu1.itb.inst_misses 4363 # ITB inst misses +system.cpu1.itb.inst_hits 16803682 # ITB inst hits +system.cpu1.itb.inst_misses 6173 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1718,595 +2176,986 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1319 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1327 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 2055 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 2309 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8630872 # ITB inst accesses -system.cpu1.itb.hits 8626509 # DTB hits -system.cpu1.itb.misses 4363 # DTB misses -system.cpu1.itb.accesses 8630872 # DTB accesses -system.cpu1.numCycles 396849081 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 16809855 # ITB inst accesses +system.cpu1.itb.hits 16803682 # DTB hits +system.cpu1.itb.misses 6173 # DTB misses +system.cpu1.itb.accesses 16809855 # DTB accesses +system.cpu1.numCycles 436917069 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 18444788 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 25760845 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 5001209 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 2723257 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 375027882 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 802688 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 60706 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 28139 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 75697 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1303305 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.CacheLines 8624270 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 181619 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 1774 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 395341861 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.079415 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 0.442124 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 7779761 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 51586006 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9149866 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 5213908 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 424935366 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 1119898 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 77514 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 41827 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 113975 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 2395843 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 15405 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 16801187 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 110293 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 1839 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 435919640 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.141195 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 0.582401 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 380851246 96.33% 96.33% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 4867429 1.23% 97.57% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 2340779 0.59% 98.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 7282407 1.84% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 407581344 93.50% 93.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 9416514 2.16% 95.66% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 4632400 1.06% 96.72% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 14289382 3.28% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 395341861 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.012602 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.064913 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 15111141 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 368322319 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9619404 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1988623 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 300374 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 680085 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 102949 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 27336312 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 828595 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 300374 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 16508550 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 196017158 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 17889321 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 9851688 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 154774770 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 26427025 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 243114 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 56891125 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 39780893 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 150628157 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 2138867 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 27113530 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 124075273 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 31437770 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 6241 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 24483458 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 2630072 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 642693 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 559165 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 4862604 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 5657845 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 4330093 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 343073 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 498131 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 25260320 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 861912 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 41442639 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 78274 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1902061 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 3789747 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 92749 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 395341861 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.104827 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.383209 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 435919640 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.020942 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.118068 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 9900868 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 404219752 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 17609153 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 3776585 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 413282 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1053225 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 148821 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 53082842 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 1693858 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 413282 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 13042184 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 210392870 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 23473030 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 17900158 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 170698116 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 51361658 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 445811 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 60462789 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 44486963 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 161544271 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 5689953 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 54453588 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 239756743 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 64654520 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 6270 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 48767925 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 5685663 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 754764 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 650155 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 9515727 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9671211 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 7398216 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 539915 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 877439 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 49754499 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1063600 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 65146152 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 226823 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 4308815 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 9268536 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 164257 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 435919640 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.149445 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.502702 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 362283147 91.64% 91.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 26570133 6.72% 98.36% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4792582 1.21% 99.57% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 1496663 0.38% 99.95% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 199327 0.05% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 391740283 89.87% 89.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 28930464 6.64% 96.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 10221316 2.34% 98.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 4337467 1.00% 99.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 689895 0.16% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 215 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 395341861 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 435919640 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 1195141 5.96% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 685 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 16909984 84.32% 90.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 1947822 9.71% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 4426779 17.51% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 691 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 17782110 70.33% 87.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 3074512 12.16% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 13868 0.03% 0.03% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 15563362 37.55% 37.59% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 33954 0.08% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1648 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 21553207 52.01% 89.68% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 4276600 10.32% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 14260 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 32351105 49.66% 49.68% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 60186 0.09% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1702 0.00% 49.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.78% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 25491005 39.13% 88.91% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7227894 11.09% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 41442639 # Type of FU issued -system.cpu1.iq.rate 0.104429 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 20053632 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.483889 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 498337881 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 28019357 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 25018416 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 21164 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 7936 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6759 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 61468547 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 13856 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 72058 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 65146152 # Type of FU issued +system.cpu1.iq.rate 0.149104 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 25284092 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.388113 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 591701467 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 55128847 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 48339304 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 21392 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 7974 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6777 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 90402329 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 13655 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 164874 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 455146 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 306 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 3014 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 163146 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 922858 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 700 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 9957 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 405915 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 15996057 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 1487 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 16016509 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 155340 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 300374 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 87167513 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 92299631 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 26204459 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 413282 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 90103879 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 101302025 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 50907640 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 5657845 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 4330093 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 630570 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 9334 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 92232105 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 3014 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 83298 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 118271 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 201569 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 41178523 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 21441390 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 243431 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 9671211 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 7398216 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 775761 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 15322 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 101224655 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 9957 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 133208 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 167801 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 301009 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 64655254 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25297716 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 454169 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 82227 # number of nop insts executed -system.cpu1.iew.exec_refs 25682989 # number of memory reference insts executed -system.cpu1.iew.exec_branches 3899404 # Number of branches executed -system.cpu1.iew.exec_stores 4241599 # Number of stores executed -system.cpu1.iew.exec_rate 0.103764 # Inst execution rate -system.cpu1.iew.wb_sent 41086324 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 25025175 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 11348419 # num instructions producing a value -system.cpu1.iew.wb_consumers 16538487 # num instructions consuming a value +system.cpu1.iew.exec_nop 89541 # number of nop insts executed +system.cpu1.iew.exec_refs 32443779 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6846575 # Number of branches executed +system.cpu1.iew.exec_stores 7146063 # Number of stores executed +system.cpu1.iew.exec_rate 0.147981 # Inst execution rate +system.cpu1.iew.wb_sent 64439493 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 48346081 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 25811466 # num instructions producing a value +system.cpu1.iew.wb_consumers 39458467 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.063060 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.686182 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.110653 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.654143 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1702265 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 769163 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 191007 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 394940200 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.061056 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 0.422241 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 3859068 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 899343 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 275462 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 435139005 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.106498 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 0.626723 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 381244473 96.53% 96.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 9114140 2.31% 98.84% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2236589 0.57% 99.41% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 955406 0.24% 99.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 446570 0.11% 99.76% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 403381 0.10% 99.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 181575 0.05% 99.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 97100 0.02% 99.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 260966 0.07% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 413392451 95.00% 95.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 12955608 2.98% 97.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 3521257 0.81% 98.79% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1360882 0.31% 99.10% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1313314 0.30% 99.40% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 777449 0.18% 99.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 559175 0.13% 99.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 305729 0.07% 99.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 953140 0.22% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 394940200 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 19609371 # Number of instructions committed -system.cpu1.commit.committedOps 24113599 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 435139005 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38843249 # Number of instructions committed +system.cpu1.commit.committedOps 46341542 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 9369646 # Number of memory references committed -system.cpu1.commit.loads 5202699 # Number of loads committed -system.cpu1.commit.membars 162322 # Number of memory barriers committed -system.cpu1.commit.branches 3698878 # Number of branches committed +system.cpu1.commit.refs 15740654 # Number of memory references committed +system.cpu1.commit.loads 8748353 # Number of loads committed +system.cpu1.commit.membars 195273 # Number of memory barriers committed +system.cpu1.commit.branches 6419002 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 21204966 # Number of committed integer instructions. -system.cpu1.commit.function_calls 385194 # Number of function calls committed. +system.cpu1.commit.int_insts 41058956 # Number of committed integer instructions. +system.cpu1.commit.function_calls 553431 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 14709151 61.00% 61.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 33154 0.14% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 1648 0.01% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 5202699 21.58% 82.72% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 4166947 17.28% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 30541068 65.90% 65.90% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 58118 0.13% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 1702 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 8748353 18.88% 84.91% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 6992301 15.09% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 24113599 # Class of committed instruction -system.cpu1.commit.bw_lim_events 260966 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 46341542 # Class of committed instruction +system.cpu1.commit.bw_lim_events 953140 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 419589246 # The number of ROB reads -system.cpu1.rob.rob_writes 52032512 # The number of ROB writes -system.cpu1.timesIdled 248745 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 1507220 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4845699469 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 19539732 # Number of Instructions Simulated -system.cpu1.committedOps 24043960 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 20.309853 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 20.309853 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.049237 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.049237 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 45343306 # number of integer regfile reads -system.cpu1.int_regfile_writes 15599183 # number of integer regfile writes -system.cpu1.fp_regfile_reads 5046 # number of floating regfile reads +system.cpu1.rob.rob_reads 483317632 # The number of ROB reads +system.cpu1.rob.rob_writes 101136219 # The number of ROB writes +system.cpu1.timesIdled 117466 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 997429 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4778390126 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38773610 # Number of Instructions Simulated +system.cpu1.committedOps 46271903 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 11.268413 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 11.268413 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.088744 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.088744 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 76047297 # number of integer regfile reads +system.cpu1.int_regfile_writes 30995697 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4960 # number of floating regfile reads system.cpu1.fp_regfile_writes 2260 # number of floating regfile writes -system.cpu1.cc_regfile_reads 139131439 # number of cc regfile reads -system.cpu1.cc_regfile_writes 9348976 # number of cc regfile writes -system.cpu1.misc_regfile_reads 454367618 # number of misc regfile reads -system.cpu1.misc_regfile_writes 623445 # number of misc regfile writes -system.cpu1.icache.tags.replacements 439266 # number of replacements -system.cpu1.icache.tags.tagsinuse 497.815366 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 8166304 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 439778 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 18.569151 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 119618152250 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 497.815366 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.972296 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.972296 # Average percentage of cache occupancy +system.cpu1.cc_regfile_reads 220730482 # number of cc regfile reads +system.cpu1.cc_regfile_writes 19377985 # number of cc regfile writes +system.cpu1.misc_regfile_reads 520419201 # number of misc regfile reads +system.cpu1.misc_regfile_writes 723683 # number of misc regfile writes +system.cpu1.toL2Bus.trans_dist::ReadReq 2172606 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1978157 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 758384 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 758384 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 291033 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 272197 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 56199 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 25233 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 54439 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 45 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 157045 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 149477 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1093505 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 4944143 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17380 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 65233 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 6120261 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 34983760 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 51460526 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 28972 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 118552 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 86591810 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 595717 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1871452 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.290652 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.454063 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 1327511 70.93% 70.93% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 543941 29.07% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1871452 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 2995139487 # Layer occupancy (ticks) +system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu1.toL2Bus.snoopLayer0.occupancy 46865000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer0.occupancy 820984463 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer1.occupancy 2122961296 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer2.occupancy 10148477 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer3.occupancy 36069550 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu1.icache.tags.replacements 546235 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.934216 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 16238797 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 546747 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 29.700752 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 73709463000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.934216 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974481 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.974481 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 509 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 9063984 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 9063984 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 8166304 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 8166304 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 8166304 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 8166304 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 8166304 # number of overall hits -system.cpu1.icache.overall_hits::total 8166304 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 457900 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 457900 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 457900 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 457900 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 457900 # number of overall misses -system.cpu1.icache.overall_misses::total 457900 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6264180115 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6264180115 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6264180115 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6264180115 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6264180115 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6264180115 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 8624204 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8624204 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8624204 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8624204 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8624204 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8624204 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.053095 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.053095 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.053095 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.053095 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.053095 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.053095 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13680.236111 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13680.236111 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13680.236111 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13680.236111 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13680.236111 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13680.236111 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 882 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 53 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 16.641509 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.icache.tags.tag_accesses 34148852 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 34148852 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 16238797 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 16238797 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 16238797 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 16238797 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 16238797 # number of overall hits +system.cpu1.icache.overall_hits::total 16238797 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 562244 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 562244 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 562244 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 562244 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 562244 # number of overall misses +system.cpu1.icache.overall_misses::total 562244 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4743193454 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4743193454 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4743193454 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4743193454 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4743193454 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4743193454 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 16801041 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 16801041 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 16801041 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 16801041 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 16801041 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 16801041 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.033465 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.033465 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.033465 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.033465 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.033465 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.033465 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8436.183319 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8436.183319 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8436.183319 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8436.183319 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8436.183319 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8436.183319 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 307905 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 7 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 40708 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.563747 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 18120 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 18120 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 18120 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 18120 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 18120 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 18120 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 439780 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 439780 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 439780 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 439780 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 439780 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 439780 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5188034078 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5188034078 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5188034078 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5188034078 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5188034078 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5188034078 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4304000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 4304000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 4304000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 4304000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.050994 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.050994 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.050994 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.050994 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.050994 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.050994 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11796.884983 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11796.884983 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11796.884983 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11796.884983 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11796.884983 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11796.884983 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 15474 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 15474 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 15474 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 15474 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 15474 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 15474 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 546770 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 546770 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 546770 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 546770 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 546770 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 546770 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3839673113 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3839673113 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3839673113 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3839673113 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3839673113 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3839673113 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5117249 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5117249 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5117249 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 5117249 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.032544 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.032544 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.032544 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.032544 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.032544 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.032544 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7022.464863 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7022.464863 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7022.464863 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 7022.464863 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7022.464863 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 7022.464863 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 227040 # number of replacements -system.cpu1.dcache.tags.tagsinuse 492.830733 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 7082160 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 227406 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 31.143242 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 99092137500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 492.830733 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.962560 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.962560 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 366 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 366 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.714844 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 32684037 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 32684037 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 3792757 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3792757 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3094601 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3094601 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 14161 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 14161 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 75622 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 75622 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 75613 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 75613 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 6887358 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 6887358 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 6901519 # number of overall hits -system.cpu1.dcache.overall_hits::total 6901519 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 187422 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 187422 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 806941 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 806941 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 41483 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 41483 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10414 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 10414 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9617 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 9617 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 994363 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 994363 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1035846 # number of overall misses -system.cpu1.dcache.overall_misses::total 1035846 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2444126213 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2444126213 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 27779707617 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 27779707617 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 86490246 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 86490246 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53209125 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 53209125 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 14000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 14000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 30223833830 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 30223833830 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 30223833830 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 30223833830 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3980179 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3980179 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 3901542 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3901542 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 55644 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 55644 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 86036 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 86036 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 85230 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 85230 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 7881721 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 7881721 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 7937365 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 7937365 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.047089 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.047089 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.206826 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.206826 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.745507 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.745507 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.121042 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.121042 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.112836 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.112836 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.126161 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.126161 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.130503 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.130503 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13040.764761 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13040.764761 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34425.946404 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 34425.946404 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8305.189745 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8305.189745 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5532.819486 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5532.819486 # average StoreCondReq miss latency +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 5063185 # number of hwpf identified +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 195793 # number of hwpf that were already in mshr +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4609637 # number of hwpf that were already in the cache +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 49643 # number of hwpf that were already in the prefetch queue +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 8256 # number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 199856 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 430863 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.l2cache.tags.replacements 189917 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15760.362755 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1051721 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 205349 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 5.121627 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 2533057390500 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 4796.141133 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 17.055492 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.249384 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 825.564654 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2172.411955 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 7947.940138 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.292733 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001041 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000076 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.050388 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.132594 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.485104 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.961936 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 8428 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 6994 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2154 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 2511 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 3763 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2597 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1568 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2829 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.514404 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.426880 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 21502320 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 21502320 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 29274 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7085 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 535244 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 196892 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 768495 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 291031 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 291031 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2209 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 2209 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1205 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 1205 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 122716 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 122716 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 29274 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7085 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 535244 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 319608 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 891211 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 29274 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7085 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 535244 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 319608 # number of overall hits +system.cpu1.l2cache.overall_hits::total 891211 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 364 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 158 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 11361 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 60780 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 72663 # number of ReadReq misses +system.cpu1.l2cache.Writeback_misses::writebacks 2 # number of Writeback misses +system.cpu1.l2cache.Writeback_misses::total 2 # number of Writeback misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 20588 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 20588 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 13188 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 13188 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 25387 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 25387 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 364 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 158 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 11361 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 86167 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 98050 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 364 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 158 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 11361 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 86167 # number of overall misses +system.cpu1.l2cache.overall_misses::total 98050 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 8462000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 3365000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 344449975 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1612650155 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 1968927130 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 357562229 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 357562229 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 267838079 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 267838079 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1192000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1192000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1149303620 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1149303620 # number of ReadExReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 8462000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 3365000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 344449975 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 2761953775 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 3118230750 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 8462000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 3365000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 344449975 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 2761953775 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 3118230750 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 29638 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7243 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 546605 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 257672 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 841158 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 291033 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 291033 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 22797 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 22797 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 14393 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 14393 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 148103 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 148103 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 29638 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7243 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 546605 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 405775 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 989261 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 29638 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7243 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 546605 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 405775 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 989261 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.012282 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.021814 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.020785 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.235881 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.086384 # miss rate for ReadReq accesses +system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000007 # miss rate for Writeback accesses +system.cpu1.l2cache.Writeback_miss_rate::total 0.000007 # miss rate for Writeback accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.903101 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.903101 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.916279 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.916279 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.171414 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.171414 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.012282 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.021814 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.020785 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.212352 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.099114 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.012282 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.021814 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.020785 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.212352 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.099114 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23247.252747 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 21297.468354 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 30318.631723 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 26532.579056 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 27096.694741 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 17367.506752 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 17367.506752 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20309.226494 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20309.226494 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 596000 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 596000 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 45271.344389 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 45271.344389 # average ReadExReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23247.252747 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 21297.468354 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30318.631723 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32053.498149 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 31802.455380 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23247.252747 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 21297.468354 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30318.631723 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32053.498149 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 31802.455380 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 8115 # number of cycles access was blocked +system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 442 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 18.359729 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.l2cache.fast_writes 0 # number of fast writes performed +system.cpu1.l2cache.cache_copies 0 # number of cache copies performed +system.cpu1.l2cache.writebacks::writebacks 108849 # number of writebacks +system.cpu1.l2cache.writebacks::total 108849 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 1 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 2808 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 143 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 2953 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1573 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 1573 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 1 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 2808 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1716 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 4526 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 1 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 2808 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1716 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 4526 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 363 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 157 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 8553 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 60637 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 69710 # number of ReadReq MSHR misses +system.cpu1.l2cache.Writeback_mshr_misses::writebacks 2 # number of Writeback MSHR misses +system.cpu1.l2cache.Writeback_mshr_misses::total 2 # number of Writeback MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 199848 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 199848 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 20588 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 20588 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 13188 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 13188 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 23814 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 23814 # number of ReadExReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 363 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 157 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 8553 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 84451 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 93524 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 363 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 157 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 8553 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 84451 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 199848 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 293372 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 5904000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 2254500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 234181256 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1184058953 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1426398709 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 10843374528 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 10843374528 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 344645957 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 344645957 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 188520557 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 188520557 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 996000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 996000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 690789082 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 690789082 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 5904000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 2254500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 234181256 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 1874848035 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 2117187791 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 5904000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 2254500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 234181256 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1874848035 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 10843374528 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 12960562319 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4572000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 174823243259 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 174827815259 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 29484635658 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 29484635658 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 4572000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 204307878917 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 204312450917 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.012248 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.021676 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.015647 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.235326 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.082874 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000007 # mshr miss rate for Writeback accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000007 # mshr miss rate for Writeback accesses +system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.903101 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.903101 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.916279 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.916279 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.160794 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.160794 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.012248 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.021676 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.015647 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.208123 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.094539 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.012248 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.021676 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.015647 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.208123 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.296557 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16264.462810 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14359.872611 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27380.013562 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 19527.004189 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 20461.895123 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 54258.108803 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 54258.108803 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16740.137799 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16740.137799 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14294.855702 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14294.855702 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 498000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 498000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29007.687999 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29007.687999 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16264.462810 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14359.872611 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27380.013562 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22200.424329 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22637.908890 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16264.462810 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14359.872611 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27380.013562 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22200.424329 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 54258.108803 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 44177.911726 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.tags.replacements 381661 # number of replacements +system.cpu1.dcache.tags.tagsinuse 481.780956 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 12332117 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 381992 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 32.283705 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 70951149500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.780956 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.940978 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.940978 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 331 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 331 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.646484 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 27770563 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 27770563 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 7205629 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 7205629 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4858222 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4858222 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 24502 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 24502 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 94117 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 94117 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 93451 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 93451 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12063851 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12063851 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12088353 # number of overall hits +system.cpu1.dcache.overall_hits::total 12088353 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 362275 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 362275 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 967298 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 967298 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 47536 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 47536 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14955 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 14955 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 14395 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 14395 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1329573 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1329573 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1377109 # number of overall misses +system.cpu1.dcache.overall_misses::total 1377109 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4296873688 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 4296873688 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 15627489636 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 15627489636 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 254785499 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 254785499 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 332075324 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 332075324 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1276000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1276000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 19924363324 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 19924363324 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 19924363324 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 19924363324 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 7567904 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 7567904 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5825520 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5825520 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 72038 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 72038 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 109072 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 109072 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 107846 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 107846 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 13393424 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 13393424 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 13465462 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 13465462 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.047870 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.047870 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.166045 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.166045 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.659874 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.659874 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.137111 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.137111 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.133477 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.133477 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.099271 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.099271 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.102270 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.102270 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11860.806536 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 11860.806536 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16155.817169 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 16155.817169 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17036.810364 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17036.810364 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23068.796388 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23068.796388 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30395.171411 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 30395.171411 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29177.922037 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 29177.922037 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 4476 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 723 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 6.190871 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14985.535449 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14985.535449 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14468.254382 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14468.254382 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 4991 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 2160220 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 228 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 94010 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 21.890351 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 22.978619 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 207281 # number of writebacks -system.cpu1.dcache.writebacks::total 207281 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 70540 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 70540 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 693700 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 693700 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 500 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 500 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 764240 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 764240 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 764240 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 764240 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 116882 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 116882 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 113241 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 113241 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23891 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 23891 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9914 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9914 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9617 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 9617 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 230123 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 230123 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 254014 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 254014 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1203808322 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1203808322 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3988299754 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3988299754 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 341716536 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 341716536 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 60834504 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 60834504 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 33974875 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 33974875 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 12000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 12000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5192108076 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 5192108076 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5533824612 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5533824612 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168973544758 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168973544758 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 522517625 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 522517625 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 169496062383 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 169496062383 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029366 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029366 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029025 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029025 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.429354 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.429354 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.115231 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.115231 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.112836 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112836 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029197 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.029197 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032002 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.032002 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10299.347393 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10299.347393 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35219.573776 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 35219.573776 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14303.149136 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 14303.149136 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6136.221908 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6136.221908 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3532.793491 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3532.793491 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 291033 # number of writebacks +system.cpu1.dcache.writebacks::total 291033 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 148293 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 148293 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 797245 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 797245 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1426 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1426 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 945538 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 945538 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 945538 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 945538 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 213982 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 213982 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 170053 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 170053 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 30328 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 30328 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13529 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13529 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 14395 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 14395 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 384035 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 384035 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 414363 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 414363 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2231950081 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2231950081 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2569103752 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2569103752 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 638180745 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 638180745 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 208910751 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 208910751 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 302166676 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 302166676 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1220000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1220000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4801053833 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4801053833 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5439234578 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5439234578 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 183653885735 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 183653885735 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 50893842775 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 50893842775 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 234547728510 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 234547728510 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028275 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.028275 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029191 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029191 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.421000 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.421000 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.124037 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.124037 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.133477 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.133477 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028673 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.028673 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030772 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.030772 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10430.550612 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10430.550612 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15107.664975 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15107.664975 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21042.625462 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21042.625462 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15441.699387 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15441.699387 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20991.085516 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20991.085516 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22562.317004 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22562.317004 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21785.510295 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21785.510295 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12501.604888 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12501.604888 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13126.738097 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13126.738097 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2330,18 +3179,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736665659303 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1736665659303 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736665659303 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1736665659303 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736182068909 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1736182068909 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736182068909 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1736182068909 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 52427 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 42962 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 40685 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 50554 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index e77a65365..8ecc8ed09 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,110 +1,110 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.542203 # Number of seconds simulated -sim_ticks 2542202956000 # Number of ticks simulated -final_tick 2542202956000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.542157 # Number of seconds simulated +sim_ticks 2542156879500 # Number of ticks simulated +final_tick 2542156879500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 47189 # Simulator instruction rate (inst/s) -host_op_rate 56852 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1989066585 # Simulator tick rate (ticks/s) -host_mem_usage 412724 # Number of bytes of host memory used -host_seconds 1278.09 # Real time elapsed on the host -sim_insts 60311945 # Number of instructions simulated -sim_ops 72661478 # Number of ops (including micro ops) simulated +host_inst_rate 53622 # Simulator instruction rate (inst/s) +host_op_rate 64601 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2260157205 # Simulator tick rate (ticks/s) +host_mem_usage 463148 # Number of bytes of host memory used +host_seconds 1124.77 # Real time elapsed on the host +sim_insts 60311972 # Number of instructions simulated +sim_ops 72661518 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 640 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 798576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9072728 # Number of bytes read from this memory -system.physmem.bytes_read::total 130982664 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 798576 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 798576 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 798448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9072920 # Number of bytes read from this memory +system.physmem.bytes_read::total 130982728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 798448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798448 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 3743232 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory system.physmem.bytes_written::total 6759304 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 10 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 14991 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141787 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15295607 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 14989 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141790 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15295608 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 58488 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory system.physmem.num_writes::total 812506 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47639992 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.clcd 47640855 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 252 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314128 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3568845 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51523292 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314128 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314128 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1472436 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1186401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2658837 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1472436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47639992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314083 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3568985 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51524251 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314083 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314083 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1472463 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1186422 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2658885 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1472463 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47640855 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 252 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314128 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4755246 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54182129 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15295607 # Number of read requests accepted +system.physmem.bw_total::cpu.inst 314083 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4755408 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54183136 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15295608 # Number of read requests accepted system.physmem.writeReqs 812506 # Number of write requests accepted -system.physmem.readBursts 15295607 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 15295608 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 812506 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 976934144 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1984704 # Total number of bytes read from write queue -system.physmem.bytesWritten 6778304 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 130982664 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 977064192 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1854720 # Total number of bytes read from write queue +system.physmem.bytesWritten 6781120 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 130982728 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 6759304 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 31011 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706576 # Number of DRAM write bursts merged with an existing one +system.physmem.servicedByWrQ 28980 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706520 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 4612 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 955786 # Per bank write bursts +system.physmem.perBankRdBursts::0 955787 # Per bank write bursts system.physmem.perBankRdBursts::1 955478 # Per bank write bursts -system.physmem.perBankRdBursts::2 953003 # Per bank write bursts -system.physmem.perBankRdBursts::3 951059 # Per bank write bursts -system.physmem.perBankRdBursts::4 958601 # Per bank write bursts -system.physmem.perBankRdBursts::5 955602 # Per bank write bursts -system.physmem.perBankRdBursts::6 952653 # Per bank write bursts -system.physmem.perBankRdBursts::7 950407 # Per bank write bursts -system.physmem.perBankRdBursts::8 956154 # Per bank write bursts +system.physmem.perBankRdBursts::2 953511 # Per bank write bursts +system.physmem.perBankRdBursts::3 951566 # Per bank write bursts +system.physmem.perBankRdBursts::4 958612 # Per bank write bursts +system.physmem.perBankRdBursts::5 955530 # Per bank write bursts +system.physmem.perBankRdBursts::6 953056 # Per bank write bursts +system.physmem.perBankRdBursts::7 951020 # Per bank write bursts +system.physmem.perBankRdBursts::8 956158 # Per bank write bursts system.physmem.perBankRdBursts::9 955874 # Per bank write bursts -system.physmem.perBankRdBursts::10 952889 # Per bank write bursts -system.physmem.perBankRdBursts::11 950148 # Per bank write bursts +system.physmem.perBankRdBursts::10 952686 # Per bank write bursts +system.physmem.perBankRdBursts::11 950200 # Per bank write bursts system.physmem.perBankRdBursts::12 956166 # Per bank write bursts system.physmem.perBankRdBursts::13 955918 # Per bank write bursts -system.physmem.perBankRdBursts::14 953918 # Per bank write bursts -system.physmem.perBankRdBursts::15 950940 # Per bank write bursts -system.physmem.perBankWrBursts::0 6546 # Per bank write bursts -system.physmem.perBankWrBursts::1 6352 # Per bank write bursts -system.physmem.perBankWrBursts::2 6488 # Per bank write bursts -system.physmem.perBankWrBursts::3 6518 # Per bank write bursts -system.physmem.perBankWrBursts::4 6421 # Per bank write bursts -system.physmem.perBankWrBursts::5 6701 # Per bank write bursts -system.physmem.perBankWrBursts::6 6665 # Per bank write bursts -system.physmem.perBankWrBursts::7 6611 # Per bank write bursts -system.physmem.perBankWrBursts::8 6966 # Per bank write bursts -system.physmem.perBankWrBursts::9 6759 # Per bank write bursts -system.physmem.perBankWrBursts::10 6421 # Per bank write bursts -system.physmem.perBankWrBursts::11 6055 # Per bank write bursts -system.physmem.perBankWrBursts::12 7037 # Per bank write bursts -system.physmem.perBankWrBursts::13 6645 # Per bank write bursts -system.physmem.perBankWrBursts::14 6920 # Per bank write bursts -system.physmem.perBankWrBursts::15 6806 # Per bank write bursts +system.physmem.perBankRdBursts::14 953812 # Per bank write bursts +system.physmem.perBankRdBursts::15 951254 # Per bank write bursts +system.physmem.perBankWrBursts::0 6556 # Per bank write bursts +system.physmem.perBankWrBursts::1 6344 # Per bank write bursts +system.physmem.perBankWrBursts::2 6481 # Per bank write bursts +system.physmem.perBankWrBursts::3 6512 # Per bank write bursts +system.physmem.perBankWrBursts::4 6422 # Per bank write bursts +system.physmem.perBankWrBursts::5 6709 # Per bank write bursts +system.physmem.perBankWrBursts::6 6691 # Per bank write bursts +system.physmem.perBankWrBursts::7 6631 # Per bank write bursts +system.physmem.perBankWrBursts::8 6968 # Per bank write bursts +system.physmem.perBankWrBursts::9 6764 # Per bank write bursts +system.physmem.perBankWrBursts::10 6424 # Per bank write bursts +system.physmem.perBankWrBursts::11 6068 # Per bank write bursts +system.physmem.perBankWrBursts::12 7033 # Per bank write bursts +system.physmem.perBankWrBursts::13 6638 # Per bank write bursts +system.physmem.perBankWrBursts::14 6915 # Per bank write bursts +system.physmem.perBankWrBursts::15 6799 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2542201638000 # Total gap between requests +system.physmem.totGap 2542155562500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 18 # Read request sizes (log2) system.physmem.readPktSize::3 15138826 # Read request sizes (log2) system.physmem.readPktSize::4 3351 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 153412 # Read request sizes (log2) +system.physmem.readPktSize::6 153413 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) @@ -112,26 +112,26 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 58488 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1110293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 964892 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 965548 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1076032 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 973735 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1036027 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2680967 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2587988 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3368391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 128855 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 111642 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 103064 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 98734 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20085 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 19255 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18985 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 85 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1110331 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 964948 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 965784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1077100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 974799 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1038209 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2680927 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2586042 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3366057 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 129275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 112161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 103418 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 99187 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20031 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 19249 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 19008 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 90 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -159,28 +159,28 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2611 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2919 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -208,50 +208,53 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1010606 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 973.388688 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 909.020446 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 200.819397 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22711 2.25% 2.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19828 1.96% 4.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8563 0.85% 5.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2249 0.22% 5.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2594 0.26% 5.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1688 0.17% 5.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8931 0.88% 6.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 959 0.09% 6.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 943083 93.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1010606 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6196 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2463.620239 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 113702.310017 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 6191 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1010646 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 973.481627 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 909.246732 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 200.676766 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22575 2.23% 2.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19975 1.98% 4.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8601 0.85% 5.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2200 0.22% 5.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2445 0.24% 5.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1700 0.17% 5.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8928 0.88% 6.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 928 0.09% 6.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 943294 93.34% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1010646 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6195 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2464.343987 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 113708.986245 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 6190 99.92% 99.92% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 2 0.03% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6196 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6196 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.093447 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.042337 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.354685 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3441 55.54% 55.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 45 0.73% 56.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1714 27.66% 83.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 868 14.01% 97.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 47 0.76% 98.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 22 0.36% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 27 0.44% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 21 0.34% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 10 0.16% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6196 # Writes before turning the bus around for reads -system.physmem.totQLat 395449280750 # Total ticks spent queuing -system.physmem.totMemAccLat 681660455750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76322980000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25906.31 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6195 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6195 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.103309 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.049475 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.400786 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3455 55.77% 55.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 44 0.71% 56.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1683 27.17% 83.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 856 13.82% 97.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 62 1.00% 98.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 32 0.52% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 30 0.48% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 14 0.23% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 13 0.21% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 3 0.05% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6195 # Writes before turning the bus around for reads +system.physmem.totQLat 395458190750 # Total ticks spent queuing +system.physmem.totMemAccLat 681707465750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76333140000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25903.44 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44656.31 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 384.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44653.44 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 384.34 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.67 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.52 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.66 # Average system write bandwidth in MiByte/s @@ -259,18 +262,18 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 3.02 # Data bus utilization in percentage system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.20 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.61 # Average write queue length when enqueuing -system.physmem.readRowHits 14269193 # Number of row buffer hits during reads -system.physmem.writeRowHits 90708 # Number of row buffer hits during writes +system.physmem.avgRdQLen 7.09 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.73 # Average write queue length when enqueuing +system.physmem.readRowHits 14271218 # Number of row buffer hits during reads +system.physmem.writeRowHits 90719 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.63 # Row buffer hit rate for writes -system.physmem.avgGap 157821.19 # Average gap between requests -system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2194513894000 # Time in different power states -system.physmem.memoryStateTime::REF 84889480000 # Time in different power states +system.physmem.writeRowHitRate 85.60 # Row buffer hit rate for writes +system.physmem.avgGap 157818.32 # Average gap between requests +system.physmem.pageHitRate 93.43 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2194559119750 # Time in different power states +system.physmem.memoryStateTime::REF 84888180000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 262799464750 # Time in different power states +system.physmem.memoryStateTime::ACT 262709081500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 48 # Number of bytes read from this memory @@ -284,49 +287,58 @@ system.realview.nvmem.bw_inst_read::cpu.inst 19 system.realview.nvmem.bw_inst_read::total 19 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 19 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 19 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55125441 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16348039 # Transaction distribution -system.membus.trans_dist::ReadResp 16348039 # Transaction distribution +system.membus.trans_dist::ReadReq 16348037 # Transaction distribution +system.membus.trans_dist::ReadResp 16348037 # Transaction distribution system.membus.trans_dist::WriteReq 763357 # Transaction distribution system.membus.trans_dist::WriteResp 763357 # Transaction distribution system.membus.trans_dist::Writeback 58488 # Transaction distribution system.membus.trans_dist::UpgradeReq 4612 # Transaction distribution system.membus.trans_dist::UpgradeResp 4612 # Transaction distribution -system.membus.trans_dist::ReadExReq 131651 # Transaction distribution -system.membus.trans_dist::ReadExResp 131651 # Transaction distribution +system.membus.trans_dist::ReadExReq 131654 # Transaction distribution +system.membus.trans_dist::ReadExResp 131654 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383056 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 6 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3780 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1889330 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4276174 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1889332 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4276176 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34553806 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390478 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 48 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16631440 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19029530 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140140058 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140140058 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1558440500 # Layer occupancy (ticks) +system.membus.pkt_count::total 34553808 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390478 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 48 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16631504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19029594 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 140140122 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 216513 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 216513 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 216513 # Request fanout histogram +system.membus.reqLayer0.occupancy 1556318500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 3500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3512000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3760500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17513415500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17512345000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4726913870 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4726136292 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37423565460 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37419189712 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -334,7 +346,6 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48580309 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16322168 # Transaction distribution system.iobus.trans_dist::ReadResp 16322168 # Transaction distribution system.iobus.trans_dist::WriteReq 8176 # Transaction distribution @@ -366,34 +377,33 @@ system.iobus.pkt_count_system.bridge.master::total 2383056 system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 32660688 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390478 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123501006 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123501006 # Total data (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 2390478 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 123501006 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks) @@ -440,22 +450,22 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374880000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38173420540 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38173439288 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 13201290 # Number of BP lookups -system.cpu.branchPred.condPredicted 9675974 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 704139 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8377301 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6024680 # Number of BTB hits +system.cpu.branchPred.lookups 13200672 # Number of BP lookups +system.cpu.branchPred.condPredicted 9675464 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 704019 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8378152 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6024616 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.916719 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1435837 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 30801 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 71.908650 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1435808 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 30777 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -479,25 +489,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 31642294 # DTB read hits -system.cpu.dtb.read_misses 39524 # DTB read misses -system.cpu.dtb.write_hits 11381361 # DTB write hits -system.cpu.dtb.write_misses 10135 # DTB write misses +system.cpu.dtb.read_hits 31644036 # DTB read hits +system.cpu.dtb.read_misses 39518 # DTB read misses +system.cpu.dtb.write_hits 11381434 # DTB write hits +system.cpu.dtb.write_misses 10146 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3437 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 348 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.flush_entries 3436 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 314 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 314 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 1342 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 31681818 # DTB read accesses -system.cpu.dtb.write_accesses 11391496 # DTB write accesses +system.cpu.dtb.read_accesses 31683554 # DTB read accesses +system.cpu.dtb.write_accesses 11391580 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 43023655 # DTB hits -system.cpu.dtb.misses 49659 # DTB misses -system.cpu.dtb.accesses 43073314 # DTB accesses +system.cpu.dtb.hits 43025470 # DTB hits +system.cpu.dtb.misses 49664 # DTB misses +system.cpu.dtb.accesses 43075134 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -519,8 +529,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 24159481 # ITB inst hits -system.cpu.itb.inst_misses 10516 # ITB inst misses +system.cpu.itb.inst_hits 24158829 # ITB inst hits +system.cpu.itb.inst_misses 10513 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -529,98 +539,98 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2464 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2463 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 4176 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 4177 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 24169997 # ITB inst accesses -system.cpu.itb.hits 24159481 # DTB hits -system.cpu.itb.misses 10516 # DTB misses -system.cpu.itb.accesses 24169997 # DTB accesses -system.cpu.numCycles 499350041 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 24169342 # ITB inst accesses +system.cpu.itb.hits 24158829 # DTB hits +system.cpu.itb.misses 10513 # DTB misses +system.cpu.itb.accesses 24169342 # DTB accesses +system.cpu.numCycles 499362415 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 43030629 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 74131140 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13201290 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 7460517 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 448266810 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1858598 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 133224 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 12550 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 145871 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 3032125 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 24158180 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 404816 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4527 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 495550550 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.179793 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 0.652924 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 43030394 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 74128653 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13200672 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 7460424 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 448275105 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1858360 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 133126 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 12568 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 145919 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 3031035 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 24157528 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 404783 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4525 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 495557370 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.179785 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 0.652906 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 454644690 91.75% 91.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13614673 2.75% 94.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6391682 1.29% 95.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 20899505 4.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 454652495 91.75% 91.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13614115 2.75% 94.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6392828 1.29% 95.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 20897932 4.22% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 495550550 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.026437 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.148455 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35577628 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 424964763 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 30286365 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4037656 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 684138 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1691487 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 250438 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 80256354 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2078563 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 684138 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 38799814 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 217885603 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 28702319 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 30653900 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 178824776 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 78213523 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 597412 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 61147213 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 42400387 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 160465829 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 14695892 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 82092463 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 364185184 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 97017359 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 495557370 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.026435 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.148447 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35569711 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 424983346 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 30281377 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4038894 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 684042 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1691471 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 250415 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 80255110 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2078434 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 684042 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 38792488 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 217877928 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 28703436 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 30648610 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 178850866 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 78212678 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 597297 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 61152111 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 42400388 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 160465834 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 14716938 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 82091302 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 364181024 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 97016550 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 9816 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 75931181 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6161276 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1134052 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 964724 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8995770 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 14558741 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 12101093 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 791110 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1256144 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 75819284 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1655722 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 93902738 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 178739 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4397586 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8688962 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 172255 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 495550550 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 75931219 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 6160077 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1133996 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 964709 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 9001428 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 14558433 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 12101238 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 791096 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1255692 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 75818942 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1655707 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 93904368 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 178701 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4397117 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 8687724 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 172240 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 495557370 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.189492 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.548412 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.548385 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 430558497 86.88% 86.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 42998311 8.68% 95.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 15714626 3.17% 98.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5641325 1.14% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 637755 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 430560734 86.88% 86.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 43002673 8.68% 95.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 15716973 3.17% 98.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5640247 1.14% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 636707 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 36 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -628,44 +638,44 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 495550550 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 495557370 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4849757 15.79% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 148 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 20356138 66.26% 82.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5517293 17.96% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4845097 15.77% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 148 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 20357888 66.27% 82.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5517607 17.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 28518 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49538159 52.75% 52.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91859 0.10% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49538039 52.75% 52.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91860 0.10% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.88% # Type of FU issued @@ -689,101 +699,101 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.88% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 32267131 34.36% 87.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 11974960 12.75% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 32268758 34.36% 87.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 11975082 12.75% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 93902738 # Type of FU issued -system.cpu.iq.rate 0.188050 # Inst issue rate -system.cpu.iq.fu_busy_cnt 30723336 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.327183 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 714225557 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 81867089 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 74968821 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 93904368 # Type of FU issued +system.cpu.iq.rate 0.188049 # Inst issue rate +system.cpu.iq.fu_busy_cnt 30720740 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.327149 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 714233003 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 81866264 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 74968812 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 32544 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 12124 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10212 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124576093 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 124575127 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 21463 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 210027 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 210020 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1045815 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 542 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6661 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 369450 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1045495 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 540 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6662 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 369586 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17074256 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1003626 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17074158 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1006174 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 684138 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 94162664 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 98281305 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 77651016 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 684042 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 94158200 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 98278744 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 77650660 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 14558741 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 12101093 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1114432 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 20278 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 98196726 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6661 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 210280 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 275497 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 485777 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93247730 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 32000327 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 605564 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 14558433 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 12101238 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1114427 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 20284 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 98194153 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6662 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 210239 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 275440 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 485679 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93249449 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 32002025 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 605470 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 176010 # number of nop insts executed -system.cpu.iew.exec_refs 43889216 # number of memory reference insts executed -system.cpu.iew.exec_branches 10791342 # Number of branches executed -system.cpu.iew.exec_stores 11888889 # Number of stores executed -system.cpu.iew.exec_rate 0.186738 # Inst execution rate -system.cpu.iew.wb_sent 92183788 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 74979033 # cumulative count of insts written-back -system.cpu.iew.wb_producers 35465784 # num instructions producing a value -system.cpu.iew.wb_consumers 52709939 # num instructions consuming a value +system.cpu.iew.exec_nop 176011 # number of nop insts executed +system.cpu.iew.exec_refs 43890987 # number of memory reference insts executed +system.cpu.iew.exec_branches 10791373 # Number of branches executed +system.cpu.iew.exec_stores 11888962 # Number of stores executed +system.cpu.iew.exec_rate 0.186737 # Inst execution rate +system.cpu.iew.wb_sent 92183769 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 74979024 # cumulative count of insts written-back +system.cpu.iew.wb_producers 35461894 # num instructions producing a value +system.cpu.iew.wb_consumers 52697256 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.150153 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.672848 # average fanout of values written-back +system.cpu.iew.wb_rate 0.150150 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.672936 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 3942514 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 3942249 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1483467 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 458978 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 494644570 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.147200 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 0.699335 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 458881 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 494573774 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.147222 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 0.699394 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 457921524 92.58% 92.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 22157230 4.48% 97.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 6973464 1.41% 98.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2402706 0.49% 98.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1803578 0.36% 99.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1042786 0.21% 99.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 592301 0.12% 99.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 490313 0.10% 99.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1260668 0.25% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 457850390 92.57% 92.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 22155471 4.48% 97.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 6977487 1.41% 98.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2402189 0.49% 98.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1803487 0.36% 99.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1041949 0.21% 99.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 590384 0.12% 99.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 490446 0.10% 99.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1261971 0.26% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 494644570 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60462326 # Number of instructions committed -system.cpu.commit.committedOps 72811859 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 494573774 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60462353 # Number of instructions committed +system.cpu.commit.committedOps 72811899 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 25244569 # Number of memory references committed -system.cpu.commit.loads 13512926 # Number of loads committed +system.cpu.commit.refs 25244590 # Number of memory references committed +system.cpu.commit.loads 13512938 # Number of loads committed system.cpu.commit.membars 403660 # Number of memory barriers committed -system.cpu.commit.branches 10308073 # Number of branches committed +system.cpu.commit.branches 10308077 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 64250122 # Number of committed integer instructions. +system.cpu.commit.int_insts 64250158 # Number of committed integer instructions. system.cpu.commit.function_calls 991634 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 47477289 65.21% 65.21% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 87890 0.12% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 47477309 65.21% 65.21% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 87889 0.12% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.33% # Class of committed instruction @@ -811,72 +821,85 @@ system.cpu.commit.op_class_0::SimdFloatMisc 2111 0.00% 65.33% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 13512926 18.56% 83.89% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 11731643 16.11% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 13512938 18.56% 83.89% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 11731652 16.11% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 72811859 # Class of committed instruction -system.cpu.commit.bw_lim_events 1260668 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 72811899 # Class of committed instruction +system.cpu.commit.bw_lim_events 1261971 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 568287463 # The number of ROB reads -system.cpu.rob.rob_writes 154414560 # The number of ROB writes -system.cpu.timesIdled 544007 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3799491 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4584972685 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60311945 # Number of Instructions Simulated -system.cpu.committedOps 72661478 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.279455 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.279455 # CPI: Total CPI of All Threads -system.cpu.ipc 0.120781 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.120781 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 109116898 # number of integer regfile reads -system.cpu.int_regfile_writes 47012340 # number of integer regfile writes +system.cpu.rob.rob_reads 568215140 # The number of ROB reads +system.cpu.rob.rob_writes 154414029 # The number of ROB writes +system.cpu.timesIdled 543953 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3805045 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4584951345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60311972 # Number of Instructions Simulated +system.cpu.committedOps 72661518 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 8.279657 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.279657 # CPI: Total CPI of All Threads +system.cpu.ipc 0.120778 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.120778 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 109116744 # number of integer regfile reads +system.cpu.int_regfile_writes 47012206 # number of integer regfile writes system.cpu.fp_regfile_reads 8305 # number of floating regfile reads system.cpu.fp_regfile_writes 2780 # number of floating regfile writes -system.cpu.cc_regfile_reads 320404185 # number of cc regfile reads -system.cpu.cc_regfile_writes 30332896 # number of cc regfile writes -system.cpu.misc_regfile_reads 605539146 # number of misc regfile reads -system.cpu.misc_regfile_writes 1173999 # number of misc regfile writes -system.cpu.toL2Bus.throughput 57498963 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2604292 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2604292 # Transaction distribution +system.cpu.cc_regfile_reads 320409300 # number of cc regfile reads +system.cpu.cc_regfile_writes 30332935 # number of cc regfile writes +system.cpu.misc_regfile_reads 605119297 # number of misc regfile reads +system.cpu.misc_regfile_writes 1173998 # number of misc regfile writes +system.cpu.toL2Bus.trans_dist::ReadReq 2604204 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2604204 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763357 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763357 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 599976 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 599947 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2950 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2952 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246570 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246570 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1926546 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5768452 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 27160 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 85384 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7807542 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61456864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84377274 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 37916 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 135596 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 146007650 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 146007650 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 166384 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3090458553 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadExReq 246567 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246567 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1926460 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5768361 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 27152 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 85364 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7807337 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61454112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84373434 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 37904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 135564 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 146001014 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 26770 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2266210 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 2266210 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2266210 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3090363565 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1447056987 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1446991237 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2544187527 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2544137605 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 17686240 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 17681240 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 51535649 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 51517661 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 959881 # number of replacements -system.cpu.icache.tags.tagsinuse 511.383361 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 23149457 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 960393 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 24.104150 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 11344582250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.383361 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 959838 # number of replacements +system.cpu.icache.tags.tagsinuse 511.383389 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 23148830 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 960350 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 24.104576 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 11339333250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.383389 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998796 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998796 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -885,242 +908,242 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 171 system.cpu.icache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 25115239 # Number of tag accesses -system.cpu.icache.tags.data_accesses 25115239 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 23149457 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 23149457 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 23149457 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 23149457 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 23149457 # number of overall hits -system.cpu.icache.overall_hits::total 23149457 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1005369 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1005369 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1005369 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1005369 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1005369 # number of overall misses -system.cpu.icache.overall_misses::total 1005369 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13656038478 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13656038478 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13656038478 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13656038478 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13656038478 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13656038478 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24154826 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24154826 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24154826 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24154826 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24154826 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24154826 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 25114544 # Number of tag accesses +system.cpu.icache.tags.data_accesses 25114544 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 23148830 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 23148830 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 23148830 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 23148830 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 23148830 # number of overall hits +system.cpu.icache.overall_hits::total 23148830 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1005344 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1005344 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1005344 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1005344 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1005344 # number of overall misses +system.cpu.icache.overall_misses::total 1005344 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13667748229 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13667748229 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13667748229 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13667748229 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13667748229 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13667748229 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24154174 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24154174 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24154174 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24154174 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24154174 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24154174 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.041622 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.041622 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.041622 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.041622 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.041622 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.041622 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13583.110756 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13583.110756 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13583.110756 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13583.110756 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13583.110756 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13583.110756 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1617 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13595.096036 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13595.096036 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13595.096036 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13595.096036 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13595.096036 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13595.096036 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1628 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 119 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 118 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 13.588235 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 13.796610 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 44956 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 44956 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 44956 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 44956 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 44956 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 44956 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 960413 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 960413 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 960413 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 960413 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 960413 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 960413 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11283890760 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11283890760 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11283890760 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11283890760 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11283890760 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11283890760 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 223026500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 223026500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 223026500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 223026500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.039761 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.039761 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.039761 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.039761 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.039761 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.039761 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11748.998358 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11748.998358 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11748.998358 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11748.998358 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11748.998358 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11748.998358 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 44974 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 44974 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 44974 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 44974 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 44974 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 44974 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 960370 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 960370 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 960370 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 960370 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 960370 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 960370 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11288731510 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11288731510 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11288731510 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11288731510 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11288731510 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11288731510 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 223034500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 223034500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 223034500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 223034500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.039760 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.039760 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.039760 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.039760 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.039760 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.039760 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11754.564918 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11754.564918 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11754.564918 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11754.564918 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11754.564918 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11754.564918 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 63302 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51128.734687 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1829071 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 128690 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 14.213000 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2530789670500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37302.599889 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 6.814194 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 63303 # number of replacements +system.cpu.l2cache.tags.tagsinuse 51126.923594 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1828959 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 128691 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 14.212019 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2530750696500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 37301.769799 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 6.815946 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000703 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 7723.154288 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6096.165612 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.569193 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 7722.177507 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6096.159639 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.569180 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000104 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117846 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117831 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.093020 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.780163 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.780135 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 65381 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 268 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3024 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6221 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55835 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 269 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3025 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6220 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55834 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997635 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 18316308 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 18316308 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 33888 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 9476 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 947771 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 377103 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1368238 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 599976 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 599976 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 18315394 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 18315394 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 33880 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 9473 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 947730 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 377075 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1368158 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 599947 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 599947 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 41 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 41 # number of UpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 113216 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 113216 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 33888 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 9476 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 947771 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 490319 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1481454 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 33888 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 9476 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 947771 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 490319 # number of overall hits -system.cpu.l2cache.overall_hits::total 1481454 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 113210 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 113210 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 33880 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 9473 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 947730 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 490285 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1481368 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 33880 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 9473 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 947730 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 490285 # number of overall hits +system.cpu.l2cache.overall_hits::total 1481368 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 11 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 11654 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 11652 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 10148 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 21816 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 21814 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 2909 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 2909 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133354 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133354 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133357 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133357 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 11 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 11654 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143502 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 155170 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 11652 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143505 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 155171 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 11 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 11654 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143502 # number of overall misses -system.cpu.l2cache.overall_misses::total 155170 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 790250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 238750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 830265249 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 761175750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1592469999 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 348485 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 348485 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9338459797 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9338459797 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 790250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 238750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 830265249 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10099635547 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10930929796 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 790250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 238750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 830265249 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10099635547 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10930929796 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 33899 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 9479 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 959425 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 387251 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1390054 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 599976 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 599976 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.inst 11652 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143505 # number of overall misses +system.cpu.l2cache.overall_misses::total 155171 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 790750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 238250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 835556749 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 759914000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1596499749 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 349485 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 349485 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9345897297 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9345897297 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 790750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 238250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 835556749 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10105811297 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10942397046 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 790750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 238250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 835556749 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10105811297 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10942397046 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 33891 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 9476 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 959382 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 387223 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1389972 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 599947 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 599947 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2950 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2950 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246570 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246570 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 33899 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 9479 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 959425 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 633821 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1636624 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 33899 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 9479 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 959425 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 633821 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1636624 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000324 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000316 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012147 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026205 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246567 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246567 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 33891 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 9476 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 959382 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 633790 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1636539 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 33891 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 9476 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 959382 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 633790 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1636539 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000325 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000317 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012145 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026207 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.015694 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986102 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986102 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.540836 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.540836 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000324 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000316 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012147 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.226408 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.094811 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000324 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000316 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012147 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.226408 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.094811 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 71840.909091 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 79583.333333 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71242.942252 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75007.464525 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72995.507838 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 119.795462 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 119.795462 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70027.594200 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70027.594200 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 71840.909091 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 79583.333333 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71242.942252 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70379.754617 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70444.865605 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 71840.909091 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 79583.333333 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71242.942252 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70379.754617 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70444.865605 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.540855 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.540855 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000325 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000317 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012145 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.226424 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.094817 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000325 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000317 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012145 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.226424 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.094817 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 71886.363636 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 79416.666667 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71709.298747 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74883.129681 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73186.932658 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 120.139223 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 120.139223 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70081.790210 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70081.790210 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 71886.363636 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 79416.666667 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71709.298747 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70421.318400 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70518.312352 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 71886.363636 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 79416.666667 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71709.298747 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70421.318400 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70518.312352 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1145,88 +1168,88 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 40 system.cpu.l2cache.overall_mshr_hits::total 55 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 10 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 11640 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 11638 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10108 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 21761 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 21759 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2909 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 2909 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133354 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133354 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133357 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133357 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 10 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 11640 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143462 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 155115 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 11638 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143465 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 155116 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 10 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 11640 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143462 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 155115 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 11638 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143465 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 155116 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 596250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 201250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 683475499 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 632292750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1316565749 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29106909 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29106909 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7676486703 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7676486703 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 688774749 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 631278500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1320850749 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29121909 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29121909 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7684221703 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7684221703 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 596250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 201250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 683475499 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8308779453 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8993052452 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 688774749 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8315500203 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9005072452 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 596250 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 201250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 683475499 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8308779453 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8993052452 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 174348000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167014389750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167188737750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17147727018 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17147727018 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 174348000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184162116768 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184336464768 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 688774749 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8315500203 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9005072452 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 174356000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167012344750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167186700750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17146783596 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17146783596 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 174356000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184159128346 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184333484346 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000295 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000316 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012132 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026102 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015655 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000317 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012131 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026104 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015654 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986102 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986102 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540836 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540836 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540855 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540855 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000295 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000316 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012132 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.226345 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.094777 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000317 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012131 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.226360 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.094783 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000295 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000316 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012132 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.226345 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.094777 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000317 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012131 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.226360 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.094783 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58717.826375 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62553.695093 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60501.160287 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10005.812650 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10005.812650 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57564.727740 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57564.727740 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59183.257347 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62453.353779 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60703.651317 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10010.969062 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10010.969062 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57621.434968 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57621.434968 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58717.826375 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57916.238816 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57976.678284 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59183.257347 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57961.873649 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58053.794915 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58717.826375 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57916.238816 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57976.678284 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59183.257347 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57961.873649 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58053.794915 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1236,184 +1259,184 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 633309 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.949942 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 19068560 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 633821 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 30.085087 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 633278 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.949941 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 19068568 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 633790 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 30.086571 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 267154250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.949942 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.949941 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999902 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999902 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 91797001 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 91797001 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 11311240 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11311240 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7209458 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7209458 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 60823 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 60823 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236444 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236444 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 91796938 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 91796938 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 11311263 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11311263 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7209463 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7209463 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 60828 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 60828 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236419 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236419 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 247594 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247594 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 18520698 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18520698 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18581521 # number of overall hits -system.cpu.dcache.overall_hits::total 18581521 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 573261 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 573261 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3012484 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3012484 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 126501 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 126501 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 12988 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 12988 # number of LoadLockedReq misses +system.cpu.dcache.demand_hits::cpu.data 18520726 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18520726 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18581554 # number of overall hits +system.cpu.dcache.overall_hits::total 18581554 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 573243 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 573243 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3012489 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3012489 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 126499 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 126499 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 12987 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 12987 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3585745 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3585745 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3712246 # number of overall misses -system.cpu.dcache.overall_misses::total 3712246 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7216358166 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7216358166 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 126016512064 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 126016512064 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 178185500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 178185500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 3585732 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3585732 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3712231 # number of overall misses +system.cpu.dcache.overall_misses::total 3712231 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7223298916 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7223298916 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 126143348315 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 126143348315 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 177246500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 177246500 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 26000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 133232870230 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 133232870230 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 133232870230 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 133232870230 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 11884501 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 11884501 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10221942 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10221942 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 187324 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 187324 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 249432 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 249432 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 133366647231 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 133366647231 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 133366647231 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 133366647231 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 11884506 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 11884506 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10221952 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10221952 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 187327 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 187327 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 249406 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 249406 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247596 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247596 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 22106443 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 22106443 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 22293767 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 22293767 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.048236 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.048236 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 22106458 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 22106458 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 22293785 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 22293785 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.048234 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.048234 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.294708 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.294708 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.675306 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.675306 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052070 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052070 # miss rate for LoadLockedReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.675284 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.675284 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052072 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052072 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000008 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.162204 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.162204 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.166515 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.166515 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12588.259390 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12588.259390 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41831.429499 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41831.429499 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13719.240838 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13719.240838 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.162203 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.162203 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.166514 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.166514 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12600.762532 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12600.762532 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41873.463543 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41873.463543 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13647.994148 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13647.994148 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37156.259084 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37156.259084 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35890.097324 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35890.097324 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 18826 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1227 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.343113 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37193.701936 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37193.701936 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35926.279165 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35926.279165 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 17394 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 459 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1226 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.187602 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 459 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 599976 # number of writebacks -system.cpu.dcache.writebacks::total 599976 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 271755 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 271755 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2763119 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2763119 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 599947 # number of writebacks +system.cpu.dcache.writebacks::total 599947 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 271762 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 271762 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2763128 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2763128 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1233 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 1233 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3034874 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3034874 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3034874 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3034874 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 301506 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 301506 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249365 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249365 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 74145 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 74145 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11755 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11755 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 3034890 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3034890 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3034890 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3034890 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 301481 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 301481 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249361 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249361 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 74144 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 74144 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11754 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11754 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 550871 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 550871 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 625016 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 625016 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3569781578 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3569781578 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10783879319 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10783879319 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1231283000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1231283000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 140188500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 140188500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 550842 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 550842 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 624986 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 624986 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3569589078 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3569589078 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10791306319 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10791306319 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1230913250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1230913250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 139261250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 139261250 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14353660897 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14353660897 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15584943897 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15584943897 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182408022250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182408022250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26599942575 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26599942575 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209007964825 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209007964825 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025370 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025370 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14360895397 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14360895397 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15591808647 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15591808647 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182406065750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182406065750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26598901323 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26598901323 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209004967073 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209004967073 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025368 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025368 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024395 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024395 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.395812 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.395812 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047127 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047127 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.395800 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.395800 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047128 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047128 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000008 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024919 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.024919 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028035 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028035 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11839.835950 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11839.835950 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43245.360492 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43245.360492 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16606.419853 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16606.419853 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11925.861336 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11925.861336 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024918 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024918 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028034 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028034 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11840.179242 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11840.179242 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43275.838319 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43275.838319 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16601.656911 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16601.656911 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11847.987919 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11847.987919 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26056.301561 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26056.301561 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24935.271892 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24935.271892 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26070.806868 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26070.806868 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24947.452658 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24947.452658 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1437,16 +1460,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736929447540 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1736929447540 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736929447540 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1736929447540 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736978742288 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1736978742288 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736978742288 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1736978742288 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83187 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83186 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 3b38aee5d..91e62d8ff 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,168 +1,180 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.400983 # Number of seconds simulated -sim_ticks 2400982506000 # Number of ticks simulated -final_tick 2400982506000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.400978 # Number of seconds simulated +sim_ticks 2400977890000 # Number of ticks simulated +final_tick 2400977890000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 112943 # Simulator instruction rate (inst/s) -host_op_rate 135898 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4496473277 # Simulator tick rate (ticks/s) -host_mem_usage 411684 # Number of bytes of host memory used -host_seconds 533.97 # Real time elapsed on the host -sim_insts 60307964 # Number of instructions simulated -sim_ops 72565708 # Number of ops (including micro ops) simulated +host_inst_rate 184738 # Simulator instruction rate (inst/s) +host_op_rate 222291 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7354994241 # Simulator tick rate (ticks/s) +host_mem_usage 464680 # Number of bytes of host memory used +host_seconds 326.44 # Real time elapsed on the host +sim_insts 60306316 # Number of instructions simulated +sim_ops 72565030 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 493064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6826968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 489736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6827544 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 75520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 799936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 188416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1451264 # Number of bytes read from this memory -system.physmem.bytes_read::total 124655200 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 493064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 75520 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 188416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 757000 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3741312 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1144164 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 79168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 799488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 187904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1451008 # Number of bytes read from this memory +system.physmem.bytes_read::total 124654688 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 489736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 79168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 187904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 756808 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3741376 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1144160 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 159264 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1712388 # Number of bytes written to this memory -system.physmem.bytes_written::total 6757128 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1712392 # Number of bytes written to this memory +system.physmem.bytes_written::total 6757192 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 13916 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 106697 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 13864 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 106706 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1180 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 12499 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2944 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 22676 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512311 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58458 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 286041 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1237 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 12492 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 8 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2936 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 22672 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512303 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58459 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 286040 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 39816 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 428097 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812412 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47821703 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::cpu2.data 428098 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812413 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47821795 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 205359 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2843406 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 203974 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2843651 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 31454 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 333170 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 293 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 78475 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 604446 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51918412 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 205359 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 31454 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 78475 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315288 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1558242 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 476540 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 32973 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 332984 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 213 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 78261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 604340 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51918299 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 203974 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 32973 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 78261 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315208 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1558272 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 476539 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 66333 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 713203 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2814318 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1558242 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47821703 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 713206 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2814350 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1558272 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47821795 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 205359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3319946 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 203974 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3320191 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 31454 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 399503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 293 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 78475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1317649 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54732730 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 13448319 # Number of read requests accepted -system.physmem.writeReqs 485647 # Number of write requests accepted -system.physmem.readBursts 13448319 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 485647 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 860692416 # Total number of bytes read from DRAM +system.physmem.bw_total::cpu1.inst 32973 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 399317 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 213 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 78261 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1317546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54732649 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 13446786 # Number of read requests accepted +system.physmem.writeReqs 485691 # Number of write requests accepted +system.physmem.readBursts 13446786 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 485691 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 860594304 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 3019520 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 109787968 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 3006628 # Total written bytes from the system interface side +system.physmem.bytesWritten 3023744 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 109777664 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 3009384 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 438446 # Number of DRAM write bursts merged with an existing one +system.physmem.mergedWrBursts 438423 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 2870 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 835559 # Per bank write bursts -system.physmem.perBankRdBursts::1 835684 # Per bank write bursts -system.physmem.perBankRdBursts::2 835582 # Per bank write bursts -system.physmem.perBankRdBursts::3 835955 # Per bank write bursts -system.physmem.perBankRdBursts::4 836860 # Per bank write bursts -system.physmem.perBankRdBursts::5 838029 # Per bank write bursts -system.physmem.perBankRdBursts::6 838426 # Per bank write bursts -system.physmem.perBankRdBursts::7 839444 # Per bank write bursts -system.physmem.perBankRdBursts::8 841128 # Per bank write bursts -system.physmem.perBankRdBursts::9 843519 # Per bank write bursts -system.physmem.perBankRdBursts::10 843777 # Per bank write bursts -system.physmem.perBankRdBursts::11 843721 # Per bank write bursts -system.physmem.perBankRdBursts::12 845312 # Per bank write bursts -system.physmem.perBankRdBursts::13 845603 # Per bank write bursts -system.physmem.perBankRdBursts::14 845260 # Per bank write bursts -system.physmem.perBankRdBursts::15 844460 # Per bank write bursts -system.physmem.perBankWrBursts::0 2621 # Per bank write bursts -system.physmem.perBankWrBursts::1 2605 # Per bank write bursts -system.physmem.perBankWrBursts::2 2850 # Per bank write bursts -system.physmem.perBankWrBursts::3 3117 # Per bank write bursts -system.physmem.perBankWrBursts::4 3557 # Per bank write bursts -system.physmem.perBankWrBursts::5 3522 # Per bank write bursts -system.physmem.perBankWrBursts::6 2837 # Per bank write bursts -system.physmem.perBankWrBursts::7 2549 # Per bank write bursts -system.physmem.perBankWrBursts::8 2654 # Per bank write bursts -system.physmem.perBankWrBursts::9 2632 # Per bank write bursts -system.physmem.perBankWrBursts::10 2402 # Per bank write bursts -system.physmem.perBankWrBursts::11 2522 # Per bank write bursts -system.physmem.perBankWrBursts::12 3817 # Per bank write bursts -system.physmem.perBankWrBursts::13 3843 # Per bank write bursts -system.physmem.perBankWrBursts::14 3141 # Per bank write bursts -system.physmem.perBankWrBursts::15 2511 # Per bank write bursts +system.physmem.perBankRdBursts::0 835534 # Per bank write bursts +system.physmem.perBankRdBursts::1 835708 # Per bank write bursts +system.physmem.perBankRdBursts::2 835573 # Per bank write bursts +system.physmem.perBankRdBursts::3 835895 # Per bank write bursts +system.physmem.perBankRdBursts::4 836820 # Per bank write bursts +system.physmem.perBankRdBursts::5 838059 # Per bank write bursts +system.physmem.perBankRdBursts::6 838590 # Per bank write bursts +system.physmem.perBankRdBursts::7 839423 # Per bank write bursts +system.physmem.perBankRdBursts::8 841113 # Per bank write bursts +system.physmem.perBankRdBursts::9 843484 # Per bank write bursts +system.physmem.perBankRdBursts::10 843775 # Per bank write bursts +system.physmem.perBankRdBursts::11 843709 # Per bank write bursts +system.physmem.perBankRdBursts::12 845212 # Per bank write bursts +system.physmem.perBankRdBursts::13 845578 # Per bank write bursts +system.physmem.perBankRdBursts::14 844651 # Per bank write bursts +system.physmem.perBankRdBursts::15 843662 # Per bank write bursts +system.physmem.perBankWrBursts::0 2614 # Per bank write bursts +system.physmem.perBankWrBursts::1 2619 # Per bank write bursts +system.physmem.perBankWrBursts::2 2845 # Per bank write bursts +system.physmem.perBankWrBursts::3 3084 # Per bank write bursts +system.physmem.perBankWrBursts::4 3522 # Per bank write bursts +system.physmem.perBankWrBursts::5 3545 # Per bank write bursts +system.physmem.perBankWrBursts::6 2950 # Per bank write bursts +system.physmem.perBankWrBursts::7 2539 # Per bank write bursts +system.physmem.perBankWrBursts::8 2638 # Per bank write bursts +system.physmem.perBankWrBursts::9 2619 # Per bank write bursts +system.physmem.perBankWrBursts::10 2391 # Per bank write bursts +system.physmem.perBankWrBursts::11 2507 # Per bank write bursts +system.physmem.perBankWrBursts::12 3740 # Per bank write bursts +system.physmem.perBankWrBursts::13 3837 # Per bank write bursts +system.physmem.perBankWrBursts::14 3267 # Per bank write bursts +system.physmem.perBankWrBursts::15 2529 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2398981428000 # Total gap between requests +system.physmem.totGap 2398976781000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 13409008 # Read request sizes (log2) +system.physmem.readPktSize::3 13407440 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 39311 # Read request sizes (log2) +system.physmem.readPktSize::6 39346 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 467913 # Write request sizes (log2) +system.physmem.writePktSize::2 467914 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 17734 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 878886 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 855155 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 852902 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 940592 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 861312 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 914649 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2399113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2323436 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3041002 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 91615 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 84284 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 79661 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 76726 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16593 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 16236 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 16118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 39 # What read queue length does an incoming req see +system.physmem.writePktSize::6 17777 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 878947 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 855123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 852879 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 944479 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 861163 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 917283 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2393694 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2315582 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3029092 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 97091 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 88809 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 83328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 80474 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16579 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 16189 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 16044 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 30 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -178,42 +190,42 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 95 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 95 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2603 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2604 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2620 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 2702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 2526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2513 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 2480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2025 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2614 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2606 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2624 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 2704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 2534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 2487 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -242,414 +254,411 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 866402 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 996.895132 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 964.187701 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 145.697526 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 8320 0.96% 0.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8911 1.03% 1.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6111 0.71% 2.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 785 0.09% 2.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 956 0.11% 2.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 773 0.09% 2.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7768 0.90% 3.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 290 0.03% 3.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 832488 96.09% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 866402 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 2583 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 5206.469222 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 249565.705681 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 2582 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 866162 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 997.062961 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 964.716097 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 145.162362 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8098 0.93% 0.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8963 1.03% 1.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6105 0.70% 2.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 860 0.10% 2.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 965 0.11% 2.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 764 0.09% 2.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7665 0.88% 3.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 291 0.03% 3.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 832451 96.11% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 866162 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 2588 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 5195.817620 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 249325.060826 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 2587 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.25829e+07-1.31072e+07 1 0.04% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 2583 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 2583 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.265583 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.091885 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.157240 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1 3 0.12% 0.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 1 0.04% 0.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 2 0.08% 0.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 2 0.08% 0.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 1 0.04% 0.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::6 1 0.04% 0.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8 2 0.08% 0.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::9 1 0.04% 0.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::13 3 0.12% 0.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 4 0.15% 0.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 537 20.79% 21.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 7 0.27% 21.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 754 29.19% 51.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1050 40.65% 91.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 100 3.87% 95.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 31 1.20% 96.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 20 0.77% 97.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 15 0.58% 98.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 9 0.35% 98.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 3 0.12% 98.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 7 0.27% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 5 0.19% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 5 0.19% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 5 0.19% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 6 0.23% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 4 0.15% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 5 0.19% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 2583 # Writes before turning the bus around for reads -system.physmem.totQLat 346447958000 # Total ticks spent queuing -system.physmem.totMemAccLat 598603939250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 67241595000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25761.43 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 2588 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 2588 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.255796 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.093626 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.104963 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1 2 0.08% 0.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 1 0.04% 0.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 3 0.12% 0.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 1 0.04% 0.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5 2 0.08% 0.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7 3 0.12% 0.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::13 2 0.08% 0.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::14 2 0.08% 0.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::15 3 0.12% 0.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 555 21.45% 22.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 6 0.23% 22.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 738 28.52% 50.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1040 40.19% 91.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 103 3.98% 95.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 50 1.93% 97.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 14 0.54% 97.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 11 0.43% 97.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 13 0.50% 98.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 5 0.19% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 7 0.27% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 6 0.23% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 5 0.19% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 6 0.23% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 4 0.15% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 5 0.19% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 1 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 2588 # Writes before turning the bus around for reads +system.physmem.totQLat 347055171000 # Total ticks spent queuing +system.physmem.totMemAccLat 599182408500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 67233930000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25809.53 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44511.43 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 358.48 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44559.53 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 358.43 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.26 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 45.73 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 45.72 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.25 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.81 # Data bus utilization in percentage system.physmem.busUtilRead 2.80 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 7.91 # Average read queue length when enqueuing -system.physmem.avgWrQLen 2.57 # Average write queue length when enqueuing -system.physmem.readRowHits 12588353 # Number of row buffer hits during reads -system.physmem.writeRowHits 40744 # Number of row buffer hits during writes +system.physmem.avgRdQLen 7.23 # Average read queue length when enqueuing +system.physmem.avgWrQLen 2.52 # Average write queue length when enqueuing +system.physmem.readRowHits 12587076 # Number of row buffer hits during reads +system.physmem.writeRowHits 40794 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.61 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 86.32 # Row buffer hit rate for writes -system.physmem.avgGap 172167.88 # Average gap between requests +system.physmem.writeRowHitRate 86.30 # Row buffer hit rate for writes +system.physmem.avgGap 172185.95 # Average gap between requests system.physmem.pageHitRate 93.58 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2165142880250 # Time in different power states +system.physmem.memoryStateTime::IDLE 2165163855000 # Time in different power states system.physmem.memoryStateTime::REF 80173860000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 155659356000 # Time in different power states +system.physmem.memoryStateTime::ACT 155638381250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55731244 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 13775425 # Transaction distribution -system.membus.trans_dist::ReadResp 13775425 # Transaction distribution -system.membus.trans_dist::WriteReq 471057 # Transaction distribution -system.membus.trans_dist::WriteResp 471057 # Transaction distribution -system.membus.trans_dist::Writeback 17734 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2870 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2870 # Transaction distribution -system.membus.trans_dist::ReadExReq 31339 # Transaction distribution -system.membus.trans_dist::ReadExResp 31339 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 722736 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 440 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 15564561 # Transaction distribution +system.membus.trans_dist::ReadResp 15564561 # Transaction distribution +system.membus.trans_dist::WriteReq 763190 # Transaction distribution +system.membus.trans_dist::WriteResp 763190 # Transaction distribution +system.membus.trans_dist::Writeback 58459 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4572 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4572 # Transaction distribution +system.membus.trans_dist::ReadExReq 131741 # Transaction distribution +system.membus.trans_dist::ReadExResp 131741 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382948 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3510 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1037922 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1761100 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26818016 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 26818016 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28579116 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 726717 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 880 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5522532 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 6250133 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107272064 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 107272064 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 113522197 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 133809743 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 411651000 # Layer occupancy (ticks) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1895349 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4281819 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 28704768 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 28704768 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 32986587 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2390317 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 7020 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16592808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18990169 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 114819072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 114819072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 133809241 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 216296 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 216296 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 216296 # Request fanout histogram +system.membus.reqLayer0.occupancy 410119000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 449000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 415500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 14677819500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 14677410500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1677943291 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1676192784 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 33210614750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33189927250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 63162 # number of replacements -system.l2c.tags.tagsinuse 50410.338960 # Cycle average of tags in use -system.l2c.tags.total_refs 1759139 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 128553 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.684154 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2389834567500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36865.555388 # Average occupied blocks per requestor +system.l2c.tags.replacements 63154 # number of replacements +system.l2c.tags.tagsinuse 50400.562310 # Cycle average of tags in use +system.l2c.tags.total_refs 1759923 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 128542 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.691424 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2389821916000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36854.968320 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000123 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4868.284859 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3674.892610 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4866.476746 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3677.784289 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993335 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 794.582710 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 806.547655 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 9.832999 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1730.563101 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1659.086161 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.562524 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu1.inst 799.149653 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 805.381857 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.908524 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1731.923626 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1656.975819 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.562362 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.074284 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.056074 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.074257 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.056119 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.012124 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.012307 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000150 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.026406 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.025316 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.769201 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 11 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65380 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3043 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6074 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55872 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000168 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.997620 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17759906 # Number of tag accesses -system.l2c.tags.data_accesses 17759906 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 8189 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2843 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 435869 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 178927 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 2011 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 887 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 119100 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 59229 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 19905 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 6074 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 331991 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 135602 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1300627 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 597941 # number of Writeback hits -system.l2c.Writeback_hits::total 597941 # number of Writeback hits +system.l2c.tags.occ_percent::cpu1.inst 0.012194 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.012289 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000105 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.026427 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.025283 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.769052 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65379 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 353 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3042 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6071 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55876 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000137 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.997604 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 17767412 # Number of tag accesses +system.l2c.tags.data_accesses 17767412 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 8212 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 2860 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 436288 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 179343 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 2016 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 871 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 118139 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 58618 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 19846 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 6099 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 333250 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 135884 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1301426 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 598065 # number of Writeback hits +system.l2c.Writeback_hits::total 598065 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 9 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 14 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 27 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 52345 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 17186 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 43999 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113530 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 8189 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 2843 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 435869 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 231272 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 2011 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 887 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 119100 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 76415 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 19905 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 6074 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 331991 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 179601 # number of demand (read+write) hits -system.l2c.demand_hits::total 1414157 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 8189 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 2843 # number of overall hits -system.l2c.overall_hits::cpu0.inst 435869 # number of overall hits -system.l2c.overall_hits::cpu0.data 231272 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 2011 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 887 # number of overall hits -system.l2c.overall_hits::cpu1.inst 119100 # number of overall hits -system.l2c.overall_hits::cpu1.data 76415 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 19905 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 6074 # number of overall hits -system.l2c.overall_hits::cpu2.inst 331991 # number of overall hits -system.l2c.overall_hits::cpu2.data 179601 # number of overall hits -system.l2c.overall_hits::total 1414157 # number of overall hits +system.l2c.UpgradeReq_hits::cpu2.data 13 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 52319 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 17211 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 44017 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 113547 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 8212 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 2860 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 436288 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 231662 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 2016 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 871 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 118139 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 75829 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 19846 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 6099 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 333250 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 179901 # number of demand (read+write) hits +system.l2c.demand_hits::total 1414973 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 8212 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 2860 # number of overall hits +system.l2c.overall_hits::cpu0.inst 436288 # number of overall hits +system.l2c.overall_hits::cpu0.data 231662 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 2016 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 871 # number of overall hits +system.l2c.overall_hits::cpu1.inst 118139 # number of overall hits +system.l2c.overall_hits::cpu1.data 75829 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 19846 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 6099 # number of overall hits +system.l2c.overall_hits::cpu2.inst 333250 # number of overall hits +system.l2c.overall_hits::cpu2.data 179901 # number of overall hits +system.l2c.overall_hits::total 1414973 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7290 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6276 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 7238 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6279 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1180 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1222 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 11 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 2947 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 2622 # number of ReadReq misses -system.l2c.ReadReq_misses::total 21552 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1087 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 481 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 1336 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2904 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 101003 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 11529 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 20863 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133395 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu1.inst 1237 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1211 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 8 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 2939 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 2619 # number of ReadReq misses +system.l2c.ReadReq_misses::total 21535 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1091 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 479 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 1337 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2907 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 101010 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 11535 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 20861 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133406 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7290 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 107279 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 7238 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 107289 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1180 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 12751 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 11 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 2947 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 23485 # number of demand (read+write) misses -system.l2c.demand_misses::total 154947 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1237 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 12746 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.dtb.walker 8 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 2939 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 23480 # number of demand (read+write) misses +system.l2c.demand_misses::total 154941 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7290 # number of overall misses -system.l2c.overall_misses::cpu0.data 107279 # number of overall misses +system.l2c.overall_misses::cpu0.inst 7238 # number of overall misses +system.l2c.overall_misses::cpu0.data 107289 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1180 # number of overall misses -system.l2c.overall_misses::cpu1.data 12751 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 11 # number of overall misses -system.l2c.overall_misses::cpu2.inst 2947 # number of overall misses -system.l2c.overall_misses::cpu2.data 23485 # number of overall misses -system.l2c.overall_misses::total 154947 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1237 # number of overall misses +system.l2c.overall_misses::cpu1.data 12746 # number of overall misses +system.l2c.overall_misses::cpu2.dtb.walker 8 # number of overall misses +system.l2c.overall_misses::cpu2.inst 2939 # number of overall misses +system.l2c.overall_misses::cpu2.data 23480 # number of overall misses +system.l2c.overall_misses::total 154941 # number of overall misses system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 74500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 84908250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 91869750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 850000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 219075000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 202750495 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 599527995 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 46998 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 162493 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 209491 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 821599498 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 1528087699 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 2349687197 # number of ReadExReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 87455000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 91702500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 793250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 215412250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 203455994 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 598893494 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 68997 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 185992 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 254989 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 818099996 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 1544671950 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 2362771946 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 74500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 84908250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 913469248 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 850000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 219075000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 1730838194 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2949215192 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 87455000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 909802496 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 793250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 215412250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1748127944 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2961665440 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 74500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 84908250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 913469248 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 850000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 219075000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 1730838194 # number of overall miss cycles -system.l2c.overall_miss_latency::total 2949215192 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 8190 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 2845 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 443159 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 185203 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 2012 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 887 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 120280 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 60451 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 19916 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 6074 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 334938 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 138224 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1322179 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 597941 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 597941 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1096 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 485 # number of UpgradeReq accesses(hits+misses) +system.l2c.overall_miss_latency::cpu1.inst 87455000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 909802496 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.dtb.walker 793250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 215412250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1748127944 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2961665440 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 8213 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 2862 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 443526 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 185622 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 2017 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 871 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 119376 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 59829 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 19854 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 6099 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 336189 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 138503 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1322961 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 598065 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 598065 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1100 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 483 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu2.data 1350 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2931 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 153348 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 28715 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 64862 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246925 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 8190 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 2845 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 443159 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 338551 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 2012 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 887 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 120280 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 89166 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 19916 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 6074 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 334938 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 203086 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1569104 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 8190 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 2845 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 443159 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 338551 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 2012 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 887 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 120280 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 89166 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 19916 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 6074 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 334938 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 203086 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1569104 # number of overall (read+write) accesses +system.l2c.UpgradeReq_accesses::total 2933 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 153329 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 28746 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 64878 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246953 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 8213 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 2862 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 443526 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 338951 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 2017 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 871 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 119376 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 88575 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 19854 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 6099 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 336189 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 203381 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1569914 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 8213 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 2862 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 443526 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 338951 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 2017 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 871 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 119376 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 88575 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 19854 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 6099 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 336189 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 203381 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1569914 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000122 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000703 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.016450 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.033887 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000497 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.009810 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.020215 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000552 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.008799 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.018969 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016300 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.991788 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991753 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.989630 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.990788 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.658652 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.401497 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.321652 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.540225 # miss rate for ReadExReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000699 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.016319 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.033827 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000496 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010362 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.020241 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000403 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.008742 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.018909 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016278 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.991818 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991718 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.990370 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.991135 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.658779 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.401273 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.321542 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.540208 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000122 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000703 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.016450 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.316877 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000497 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.009810 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.143003 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000552 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.008799 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.115641 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.098749 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000699 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.016319 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.316532 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000496 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010362 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.143901 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000403 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.008742 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.115448 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.098694 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000122 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000703 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.016450 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.316877 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000497 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.009810 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.143003 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000552 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.008799 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.115641 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.098749 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000699 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.016319 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.316532 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000496 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010362 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.143901 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000403 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.008742 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.115448 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.098694 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 74500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71956.144068 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 75179.828151 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 77272.727273 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 74338.310146 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 77326.657132 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 27817.742901 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 97.708940 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 121.626497 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 72.138774 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71263.726082 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 73243.910224 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 17614.507268 # average ReadExReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70699.272433 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 75724.607762 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 99156.250000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 73294.402858 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 77684.610157 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 27810.238867 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 144.043841 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 139.111444 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 87.715514 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 70923.276636 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 74045.920617 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 17711.137025 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 71956.144068 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 71639.028155 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 77272.727273 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 74338.310146 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 73699.731488 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 19033.703086 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 70699.272433 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 71379.452063 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 99156.250000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 73294.402858 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 74451.786371 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 19114.794922 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 71956.144068 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 71639.028155 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 77272.727273 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 74338.310146 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 73699.731488 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 19033.703086 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 70699.272433 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 71379.452063 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 99156.250000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 73294.402858 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 74451.786371 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 19114.794922 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -658,8 +667,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 58458 # number of writebacks -system.l2c.writebacks::total 58458 # number of writebacks +system.l2c.writebacks::writebacks 58459 # number of writebacks +system.l2c.writebacks::total 58459 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu2.inst 3 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu2.data 8 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits @@ -670,122 +679,122 @@ system.l2c.overall_mshr_hits::cpu2.inst 3 # nu system.l2c.overall_mshr_hits::cpu2.data 8 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 1180 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1222 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 11 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 2944 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 2614 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 7972 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 481 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 1336 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 1817 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 11529 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 20863 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 32392 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 1237 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1211 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 8 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 2936 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 2611 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 8004 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 479 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 1337 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 1816 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 11535 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 20861 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 32396 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1180 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 12751 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.dtb.walker 11 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 2944 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 23477 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 40364 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1237 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 12746 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 8 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 2936 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 23472 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 40400 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1180 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 12751 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.dtb.walker 11 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 2944 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 23477 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 40364 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1237 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 12746 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 8 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 2936 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 23472 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 40400 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 69967750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 76634250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 715000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 182019500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 169748495 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 499147495 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4810481 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 13374835 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 18185316 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 675391502 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1269014301 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1944405803 # number of ReadExReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 71795000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 76590000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 694750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 178440250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 170505244 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 498087744 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4790479 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 13376836 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 18167315 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 671834504 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1285363050 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1957197554 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 69967750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 752025752 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 715000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 182019500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 1438762796 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 2443553298 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 71795000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 748424504 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 694750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 178440250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 1455868294 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 2455285298 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 69967750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 752025752 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 715000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 182019500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 1438762796 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 2443553298 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25042687500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 25560602500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 50603290000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 991271590 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 9138698000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 10129969590 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 26033959090 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 34699300500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 60733259590 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000497 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009810 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.020215 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000552 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.008790 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018911 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.006029 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991753 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.989630 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.619925 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.401497 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.321652 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.131182 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000497 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009810 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.143003 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000552 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.008790 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.115601 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.025724 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000497 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009810 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.143003 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000552 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.008790 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.115601 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.025724 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_latency::cpu1.inst 71795000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 748424504 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 694750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 178440250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 1455868294 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 2455285298 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 24982050000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 25464087500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 50446137500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 975342097 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 9141414000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 10116756097 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 25957392097 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 34605501500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 60562893597 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000496 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010362 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.020241 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000403 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.008733 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018852 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.006050 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991718 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.990370 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.619161 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.401273 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.321542 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.131183 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000496 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010362 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.143901 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000403 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.008733 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.115409 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.025734 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000496 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010362 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.143901 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000403 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.008733 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.115409 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.025734 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59294.703390 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62712.152209 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 65000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 61827.275815 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 64938.215379 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 62612.580908 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58039.611964 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63245.251858 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 86843.750000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 60776.651907 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 65302.659517 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 62229.853073 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10011.104042 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10008.429279 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58581.967387 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 60826.070124 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 60027.346351 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10005.112939 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.028084 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58243.129952 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61615.600882 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 60414.790530 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59294.703390 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58977.786213 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 65000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 61827.275815 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61283.928781 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 60537.937221 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58039.611964 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58718.382551 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 86843.750000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 60776.651907 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62025.745314 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 60774.388564 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59294.703390 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58977.786213 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 65000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 61827.275815 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61283.928781 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 60537.937221 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58039.611964 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58718.382551 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 86843.750000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 60776.651907 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62025.745314 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 60774.388564 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -802,57 +811,69 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 59108244 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1059674 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1059674 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 471057 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 471057 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 275568 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1835 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1835 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 93577 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 93577 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 911138 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2522746 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20145 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 55378 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 3509407 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29133952 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 38939733 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 27844 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 87712 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 68189241 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 141801951 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 115908 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2288858155 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::ReadReq 2539315 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2539315 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 763190 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 763190 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 598065 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2933 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2933 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 246953 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 246953 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1813392 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5760169 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 30385 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 80672 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7684618 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 57608092 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 84067517 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 48464 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 138604 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 141862677 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 18229 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2196613 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 2196613 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 2196613 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2287106157 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2052757055 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2054352798 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1915102818 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1912625851 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 13212439 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 13149443 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 33686507 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 33486737 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48817267 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 13767391 # Transaction distribution -system.iobus.trans_dist::ReadResp 13767391 # Transaction distribution -system.iobus.trans_dist::WriteReq 2985 # Transaction distribution -system.iobus.trans_dist::WriteResp 2985 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 12256 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3140 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 288 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 706746 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 15535704 # Transaction distribution +system.iobus.trans_dist::ReadResp 15535704 # Transaction distribution +system.iobus.trans_dist::WriteReq 8154 # Transaction distribution +system.iobus.trans_dist::WriteResp 8154 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30010 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 492 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1000 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 732 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -862,45 +883,44 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 722736 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26818016 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 26818016 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 27540752 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 16027 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6280 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 36 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 576 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 703222 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 726717 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107272064 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107272064 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 107998781 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 117209403 # Total data (bytes) -system.iobus.reqLayer0.occupancy 8657000 # Layer occupancy (ticks) +system.iobus.pkt_count_system.bridge.master::total 2382948 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 28704768 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 28704768 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 31087716 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39305 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15868 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 984 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2000 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 390 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 2390317 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 114819072 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::total 114819072 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 117209389 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 8534000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 1570000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 1569000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 144000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 143000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -908,7 +928,7 @@ system.iobus.reqLayer5.occupancy 8000 # La system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 353820000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 352708000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) @@ -940,11 +960,11 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 13409008000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 719751000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 13407440000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) +system.iobus.respLayer0.occupancy 717460000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 33775984250 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 33785464750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -969,25 +989,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 6543805 # DTB read hits -system.cpu0.dtb.read_misses 5435 # DTB read misses -system.cpu0.dtb.write_hits 6063639 # DTB write hits -system.cpu0.dtb.write_misses 1808 # DTB write misses +system.cpu0.dtb.read_hits 6552093 # DTB read hits +system.cpu0.dtb.read_misses 5443 # DTB read misses +system.cpu0.dtb.write_hits 6067983 # DTB write hits +system.cpu0.dtb.write_misses 1816 # DTB write misses system.cpu0.dtb.flush_tlb 554 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 493 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 23 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5223 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 496 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 5219 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 107 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 108 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 162 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 6549240 # DTB read accesses -system.cpu0.dtb.write_accesses 6065447 # DTB write accesses +system.cpu0.dtb.read_accesses 6557536 # DTB read accesses +system.cpu0.dtb.write_accesses 6069799 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12607444 # DTB hits -system.cpu0.dtb.misses 7243 # DTB misses -system.cpu0.dtb.accesses 12614687 # DTB accesses +system.cpu0.dtb.hits 12620076 # DTB hits +system.cpu0.dtb.misses 7259 # DTB misses +system.cpu0.dtb.accesses 12627335 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1009,55 +1029,55 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 30119411 # ITB inst hits -system.cpu0.itb.inst_misses 2986 # ITB inst misses +system.cpu0.itb.inst_hits 30154576 # ITB inst hits +system.cpu0.itb.inst_misses 2994 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 554 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 493 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 23 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2362 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 496 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2367 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30122397 # ITB inst accesses -system.cpu0.itb.hits 30119411 # DTB hits -system.cpu0.itb.misses 2986 # DTB misses -system.cpu0.itb.accesses 30122397 # DTB accesses -system.cpu0.numCycles 109377986 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 30157570 # ITB inst accesses +system.cpu0.itb.hits 30154576 # DTB hits +system.cpu0.itb.misses 2994 # DTB misses +system.cpu0.itb.accesses 30157570 # DTB accesses +system.cpu0.numCycles 109411317 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29708958 # Number of instructions committed -system.cpu0.committedOps 36436691 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 32091710 # Number of integer alu accesses +system.cpu0.committedInsts 29741333 # Number of instructions committed +system.cpu0.committedOps 36475405 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 32123717 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 4289 # Number of float alu accesses -system.cpu0.num_func_calls 1119227 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3806697 # number of instructions that are conditional controls -system.cpu0.num_int_insts 32091710 # number of integer instructions +system.cpu0.num_func_calls 1120042 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3813280 # number of instructions that are conditional controls +system.cpu0.num_int_insts 32123717 # number of integer instructions system.cpu0.num_fp_insts 4289 # number of float instructions -system.cpu0.num_int_register_reads 59433720 # number of times the integer registers were read -system.cpu0.num_int_register_writes 21150393 # number of times the integer registers were written +system.cpu0.num_int_register_reads 59486063 # number of times the integer registers were read +system.cpu0.num_int_register_writes 21170898 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3327 # number of times the floating registers were read system.cpu0.num_fp_register_writes 964 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 109113758 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 14198144 # number of times the CC registers were written -system.cpu0.num_mem_refs 13068134 # number of memory refs -system.cpu0.num_load_insts 6718957 # Number of load instructions -system.cpu0.num_store_insts 6349177 # Number of store instructions -system.cpu0.num_idle_cycles 107075141.411044 # Number of idle cycles -system.cpu0.num_busy_cycles 2302844.588956 # Number of busy cycles -system.cpu0.not_idle_fraction 0.021054 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.978946 # Percentage of idle cycles -system.cpu0.Branches 5297571 # Number of branches fetched -system.cpu0.op_class::No_OpClass 11842 0.03% 0.03% # Class of executed instruction -system.cpu0.op_class::IntAlu 23375924 64.04% 64.07% # Class of executed instruction -system.cpu0.op_class::IntMult 45526 0.12% 64.20% # Class of executed instruction +system.cpu0.num_cc_register_reads 109224829 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 14221647 # number of times the CC registers were written +system.cpu0.num_mem_refs 13081203 # number of memory refs +system.cpu0.num_load_insts 6727170 # Number of load instructions +system.cpu0.num_store_insts 6354033 # Number of store instructions +system.cpu0.num_idle_cycles 107121976.742744 # Number of idle cycles +system.cpu0.num_busy_cycles 2289340.257256 # Number of busy cycles +system.cpu0.not_idle_fraction 0.020924 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.979076 # Percentage of idle cycles +system.cpu0.Branches 5305474 # Number of branches fetched +system.cpu0.op_class::No_OpClass 11839 0.03% 0.03% # Class of executed instruction +system.cpu0.op_class::IntAlu 23401650 64.04% 64.07% # Class of executed instruction +system.cpu0.op_class::IntMult 45463 0.12% 64.20% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 64.20% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction @@ -1081,414 +1101,414 @@ system.cpu0.op_class::SimdFloatAlu 0 0.00% 64.20% # Cl system.cpu0.op_class::SimdFloatCmp 0 0.00% 64.20% # Class of executed instruction system.cpu0.op_class::SimdFloatCvt 0 0.00% 64.20% # Class of executed instruction system.cpu0.op_class::SimdFloatDiv 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 1430 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 1432 0.00% 64.20% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::MemRead 6718957 18.41% 82.61% # Class of executed instruction -system.cpu0.op_class::MemWrite 6349177 17.39% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 6727170 18.41% 82.61% # Class of executed instruction +system.cpu0.op_class::MemWrite 6354033 17.39% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 36502856 # Class of executed instruction +system.cpu0.op_class::total 36541587 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 82922 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 899179 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.616650 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 41225487 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 899691 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 45.821829 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7765042250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 495.273634 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 5.912581 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 10.430435 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.967331 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.011548 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.020372 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999251 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 82908 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 899905 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.617888 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 41210869 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 900417 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 45.768648 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 7755633000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 495.394938 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 5.639138 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 10.583812 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.967568 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.011014 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.020672 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999254 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 210 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 164 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 216 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 154 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 43052663 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 43052663 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 29678002 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7860593 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3686892 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 41225487 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29678002 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7860593 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3686892 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 41225487 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29678002 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7860593 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 3686892 # number of overall hits -system.cpu0.icache.overall_hits::total 41225487 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 443773 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 120537 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 363173 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 927483 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 443773 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 120537 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 363173 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 927483 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 443773 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 120537 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 363173 # number of overall misses -system.cpu0.icache.overall_misses::total 927483 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1643390750 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4873068412 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6516459162 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1643390750 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4873068412 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6516459162 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1643390750 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4873068412 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6516459162 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 30121775 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7981130 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 4050065 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 42152970 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 30121775 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7981130 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 4050065 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 42152970 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 30121775 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7981130 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 4050065 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 42152970 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014733 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015103 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.089671 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.022003 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014733 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015103 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.089671 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.022003 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014733 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015103 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.089671 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.022003 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13633.911164 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13418.036065 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 7025.960758 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13633.911164 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13418.036065 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 7025.960758 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13633.911164 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13418.036065 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 7025.960758 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3564 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 43039595 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 43039595 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 29712798 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 7804770 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 3693301 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 41210869 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29712798 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 7804770 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 3693301 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 41210869 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29712798 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 7804770 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 3693301 # number of overall hits +system.cpu0.icache.overall_hits::total 41210869 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 444147 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 119626 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 364535 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 928308 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 444147 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 119626 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 364535 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 928308 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 444147 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 119626 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 364535 # number of overall misses +system.cpu0.icache.overall_misses::total 928308 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1633550000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4883016924 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6516566924 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 1633550000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 4883016924 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6516566924 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 1633550000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 4883016924 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6516566924 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 30156945 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 7924396 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 4057836 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 42139177 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 30156945 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 7924396 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 4057836 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 42139177 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 30156945 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 7924396 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 4057836 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 42139177 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014728 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015096 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.089835 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.022030 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014728 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015096 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.089835 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.022030 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014728 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015096 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.089835 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.022030 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13655.476234 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13395.193669 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 7019.832775 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13655.476234 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13395.193669 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 7019.832775 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13655.476234 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13395.193669 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 7019.832775 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3227 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 217 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 203 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.423963 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.896552 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 27790 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 27790 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 27790 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 27790 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 27790 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 27790 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 120537 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 335383 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 455920 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 120537 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 335383 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 455920 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 120537 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 335383 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 455920 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1401871250 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3957248170 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5359119420 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1401871250 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3957248170 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5359119420 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1401871250 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3957248170 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5359119420 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015103 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.082809 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010816 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015103 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.082809 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.010816 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015103 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.082809 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.010816 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11630.215204 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11799.191283 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11754.517064 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11630.215204 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11799.191283 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11754.517064 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11630.215204 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11799.191283 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11754.517064 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 27890 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 27890 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 27890 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 27890 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 27890 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 27890 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 119626 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 336645 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 456271 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 119626 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 336645 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 456271 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 119626 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 336645 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 456271 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1393831000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3968205684 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5362036684 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1393831000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3968205684 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5362036684 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1393831000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3968205684 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5362036684 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015096 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.082962 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010828 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015096 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.082962 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010828 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015096 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.082962 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010828 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11651.572401 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11787.508158 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11751.868263 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11651.572401 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11787.508158 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11751.868263 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11651.572401 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11787.508158 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11751.868263 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 630291 # number of replacements +system.cpu0.dcache.tags.replacements 630395 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997117 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 21342473 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 630803 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 33.833817 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 21342587 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 630907 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 33.828420 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 21757000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.608321 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 7.871908 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.516888 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.971891 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015375 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.012728 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.646695 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 7.878290 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.472132 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.971966 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015387 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.012641 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 298 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 207 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 92219903 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 92219903 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5361652 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1457794 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4730320 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 11549766 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5493900 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1274863 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2443484 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9212247 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 53400 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 14515 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 23676 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 91591 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 122744 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 31335 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 84381 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 238460 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 128815 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 32780 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 85814 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247409 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10855552 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 2732657 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 7173804 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 20762013 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10908952 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 2747172 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 7197480 # number of overall hits -system.cpu0.dcache.overall_hits::total 20853604 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 142161 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 45809 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 256649 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 444619 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 154444 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 29861 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 820607 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1004912 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 36971 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 17584 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 41738 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 96293 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6071 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1446 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 4461 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11978 # number of LoadLockedReq misses -system.cpu0.dcache.demand_misses::cpu0.data 296605 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 75670 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1077256 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1449531 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 333576 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 93254 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1118994 # number of overall misses -system.cpu0.dcache.overall_misses::total 1545824 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 618572999 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 3601097882 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4219670881 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1127965983 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 26744225136 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 27872191119 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 19459500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 65741241 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 85200741 # number of LoadLockedReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 1746538982 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 30345323018 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 32091862000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 1746538982 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 30345323018 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 32091862000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5503813 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1503603 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4986969 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 11994385 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5648344 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1304724 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 3264091 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10217159 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 90371 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 32099 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 65414 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 187884 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 128815 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 32781 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 88842 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 250438 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 128815 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 32780 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 85814 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247409 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11152157 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 2808327 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 8251060 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 22211544 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11242528 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 2840426 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 8316474 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 22399428 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025830 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.030466 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.051464 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.037069 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027343 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.022887 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.251404 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.098355 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.409102 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.547805 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.638059 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.512513 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.047130 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044111 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050213 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.tags.tag_accesses 92223227 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 92223227 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5368302 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1446025 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4735634 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 11549961 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5498373 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1267433 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 2446281 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9212087 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 53662 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 14249 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu2.data 23655 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 91566 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 122592 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 31381 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 84607 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 238580 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 128647 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 32825 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 85920 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247392 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10866675 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 2713458 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 7181915 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 20762048 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10920337 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 2727707 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 7205570 # number of overall hits +system.cpu0.dcache.overall_hits::total 20853614 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 142563 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 45260 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 257630 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 445453 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 154429 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 29884 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 820485 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1004798 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 37003 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 17467 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu2.data 41789 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 96259 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6056 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1445 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 4483 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 11984 # number of LoadLockedReq misses +system.cpu0.dcache.demand_misses::cpu0.data 296992 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 75144 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1078115 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1450251 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 333995 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 92611 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1119904 # number of overall misses +system.cpu0.dcache.overall_misses::total 1546510 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 611214249 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 3612191655 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4223405904 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1124082233 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 26974160361 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 28098242594 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 19515250 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 65554993 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 85070243 # number of LoadLockedReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 1735296482 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 30586352016 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 32321648498 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 1735296482 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 30586352016 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 32321648498 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5510865 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 1491285 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 4993264 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 11995414 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5652802 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 1297317 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 3266766 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10216885 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 90665 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 31716 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 65444 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 187825 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 128648 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 32826 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 89090 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 250564 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 128647 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 32825 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 85920 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247392 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11163667 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 2788602 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 8260030 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 22212299 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11254332 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 2820318 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 8325474 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 22400124 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025869 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.030350 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.051596 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.037135 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027319 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.023035 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.251161 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.098347 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.408129 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.550731 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.638546 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.512493 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.047074 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044020 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050320 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047828 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026596 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.026945 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.130560 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.065260 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029671 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.032831 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.134551 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.069012 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13503.307189 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14031.217273 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 9490.532076 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37773.885101 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32590.783574 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 27735.952122 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13457.468880 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14736.884331 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7113.102438 # average LoadLockedReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23080.996194 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 28169.091672 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 22139.479597 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18728.837176 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 27118.396540 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 20760.359523 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 38637 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 6212 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 5775 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 192 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 6.690390 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 32.354167 # average number of cycles each access was blocked +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026603 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.026947 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.130522 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.065290 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029677 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.032837 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.134515 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.069040 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13504.512793 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14020.850270 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 9481.148188 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37614.851861 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32875.872638 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 27964.070981 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13505.363322 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14623.018737 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7098.651786 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23092.947967 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 28370.212840 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 22286.934122 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18737.476995 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 27311.583864 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 20899.734562 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 35984 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 7309 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 5054 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 190 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7.119905 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 38.468421 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 597941 # number of writebacks -system.cpu0.dcache.writebacks::total 597941 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 82 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 146159 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 146241 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 661 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 754425 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 755086 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 467 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 467 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 743 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 900584 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 901327 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 743 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 900584 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 901327 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 45727 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 110490 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 156217 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29200 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 66182 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 95382 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 13278 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 23770 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 37048 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1446 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3994 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5440 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 74927 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 176672 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 251599 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 88205 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 200442 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 288647 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 526256000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1348662754 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1874918754 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1036082517 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2113089467 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3149171984 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 204786500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 440091753 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 644878253 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 16565500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 51817259 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 68382759 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1562338517 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3461752221 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 5024090738 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1767125017 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3901843974 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 5668968991 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27358748000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 27904372000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 55263120000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1501669410 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 14569249955 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 16070919365 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28860417410 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42473621955 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71334039365 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.030412 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.022156 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.013024 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.022380 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.020276 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.009335 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.413658 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.363378 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.197185 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044111 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.044956 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.021722 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026680 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.021412 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011327 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.031053 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024102 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.012886 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11508.649157 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12206.197430 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12002.014851 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35482.277979 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 31928.461923 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33016.418024 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15422.992921 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 18514.587842 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17406.560489 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11456.085754 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12973.775413 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12570.360110 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20851.475663 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19594.232368 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19968.643508 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20034.295301 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19466.199569 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19639.798754 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 598065 # number of writebacks +system.cpu0.dcache.writebacks::total 598065 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 80 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 146918 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 146998 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 655 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 754285 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 754940 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 469 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 469 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 735 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 901203 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 901938 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 735 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 901203 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 901938 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 45180 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 110712 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 155892 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29229 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 66200 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 95429 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 13204 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 23805 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 37009 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1445 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 4014 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5459 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 74409 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 176912 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 251321 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 87613 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 200717 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 288330 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 520028500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1350346488 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1870374988 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1032772017 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2131682211 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3164454228 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 203990750 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 439543502 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 643534252 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 16622750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 51408007 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 68030757 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1552800517 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3482028699 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5034829216 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1756791267 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3921572201 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5678363468 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27292544500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 27798821000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 55091365500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1484661903 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 14572262972 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 16056924875 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28777206403 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42371083972 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71148290375 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.030296 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.022172 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.012996 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.022530 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.020265 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.009340 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.416320 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.363746 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.197040 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044020 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.045056 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.021787 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026683 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.021418 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011314 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.031065 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024109 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.012872 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11510.148296 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12196.929764 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11997.889488 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35333.812891 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32200.637628 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33160.299574 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15449.163132 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 18464.335308 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17388.587965 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11503.633218 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12807.176632 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12462.128045 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20868.450282 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19682.264058 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20033.460061 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20051.719117 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19537.817928 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19693.973808 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1522,25 +1542,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 1746639 # DTB read hits -system.cpu1.dtb.read_misses 1917 # DTB read misses -system.cpu1.dtb.write_hits 1378449 # DTB write hits +system.cpu1.dtb.read_hits 1733555 # DTB read hits +system.cpu1.dtb.read_misses 1889 # DTB read misses +system.cpu1.dtb.write_hits 1370998 # DTB write hits system.cpu1.dtb.write_misses 367 # DTB write misses system.cpu1.dtb.flush_tlb 552 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 251 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 10 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1626 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 248 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 1592 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 33 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 28 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 77 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 1748556 # DTB read accesses -system.cpu1.dtb.write_accesses 1378816 # DTB write accesses +system.cpu1.dtb.read_accesses 1735444 # DTB read accesses +system.cpu1.dtb.write_accesses 1371365 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3125088 # DTB hits -system.cpu1.dtb.misses 2284 # DTB misses -system.cpu1.dtb.accesses 3127372 # DTB accesses +system.cpu1.dtb.hits 3104553 # DTB hits +system.cpu1.dtb.misses 2256 # DTB misses +system.cpu1.dtb.accesses 3106809 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1562,55 +1582,55 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 7981130 # ITB inst hits -system.cpu1.itb.inst_misses 1058 # ITB inst misses +system.cpu1.itb.inst_hits 7924396 # ITB inst hits +system.cpu1.itb.inst_misses 1030 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 552 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 251 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 10 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 834 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 248 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 806 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7982188 # ITB inst accesses -system.cpu1.itb.hits 7981130 # DTB hits -system.cpu1.itb.misses 1058 # DTB misses -system.cpu1.itb.accesses 7982188 # DTB accesses -system.cpu1.numCycles 582833153 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7925426 # ITB inst accesses +system.cpu1.itb.hits 7924396 # DTB hits +system.cpu1.itb.misses 1030 # DTB misses +system.cpu1.itb.accesses 7925426 # DTB accesses +system.cpu1.numCycles 582686408 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7797141 # Number of instructions committed -system.cpu1.committedOps 9191219 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 8219243 # Number of integer alu accesses +system.cpu1.committedInsts 7745878 # Number of instructions committed +system.cpu1.committedOps 9129746 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 8166989 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1689 # Number of float alu accesses -system.cpu1.num_func_calls 289029 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 993030 # number of instructions that are conditional controls -system.cpu1.num_int_insts 8219243 # number of integer instructions +system.cpu1.num_func_calls 287006 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 983778 # number of instructions that are conditional controls +system.cpu1.num_int_insts 8166989 # number of integer instructions system.cpu1.num_fp_insts 1689 # number of float instructions -system.cpu1.num_int_register_reads 14554839 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5500250 # number of times the integer registers were written +system.cpu1.num_int_register_reads 14466592 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5466665 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1177 # number of times the floating registers were read system.cpu1.num_fp_register_writes 512 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 33218155 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 3793046 # number of times the CC registers were written -system.cpu1.num_mem_refs 3251661 # number of memory refs -system.cpu1.num_load_insts 1804549 # Number of load instructions -system.cpu1.num_store_insts 1447112 # Number of store instructions -system.cpu1.num_idle_cycles 548698663.963538 # Number of idle cycles -system.cpu1.num_busy_cycles 34134489.036462 # Number of busy cycles -system.cpu1.not_idle_fraction 0.058566 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.941434 # Percentage of idle cycles -system.cpu1.Branches 1360376 # Number of branches fetched -system.cpu1.op_class::No_OpClass 4595 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 6078995 65.05% 65.10% # Class of executed instruction -system.cpu1.op_class::IntMult 10163 0.11% 65.20% # Class of executed instruction +system.cpu1.num_cc_register_reads 32997995 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 3759402 # number of times the CC registers were written +system.cpu1.num_mem_refs 3229777 # number of memory refs +system.cpu1.num_load_insts 1791377 # Number of load instructions +system.cpu1.num_store_insts 1438400 # Number of store instructions +system.cpu1.num_idle_cycles 548052403.807954 # Number of idle cycles +system.cpu1.num_busy_cycles 34634004.192046 # Number of busy cycles +system.cpu1.not_idle_fraction 0.059438 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.940562 # Percentage of idle cycles +system.cpu1.Branches 1348409 # Number of branches fetched +system.cpu1.op_class::No_OpClass 4600 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 6037827 65.04% 65.09% # Class of executed instruction +system.cpu1.op_class::IntMult 10088 0.11% 65.20% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 65.20% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 65.20% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 65.20% # Class of executed instruction @@ -1634,26 +1654,26 @@ system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.20% # Cl system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.20% # Class of executed instruction system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.20% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 281 0.00% 65.21% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 273 0.00% 65.21% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 65.21% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.21% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.21% # Class of executed instruction -system.cpu1.op_class::MemRead 1804549 19.31% 84.52% # Class of executed instruction -system.cpu1.op_class::MemWrite 1447112 15.48% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 1791377 19.30% 84.50% # Class of executed instruction +system.cpu1.op_class::MemWrite 1438400 15.50% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 9345695 # Class of executed instruction +system.cpu1.op_class::total 9282565 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 5844133 # Number of BP lookups -system.cpu2.branchPred.condPredicted 4389690 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 248799 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3701982 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2861782 # Number of BTB hits +system.cpu2.branchPred.lookups 5846326 # Number of BP lookups +system.cpu2.branchPred.condPredicted 4388844 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 249586 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3633950 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2855743 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 77.304050 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 588875 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 15609 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 78.585093 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 589622 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 15464 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1677,25 +1697,25 @@ system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 13926534 # DTB read hits -system.cpu2.dtb.read_misses 28241 # DTB read misses -system.cpu2.dtb.write_hits 3979346 # DTB write hits -system.cpu2.dtb.write_misses 9743 # DTB write misses +system.cpu2.dtb.read_hits 13911313 # DTB read hits +system.cpu2.dtb.read_misses 27890 # DTB read misses +system.cpu2.dtb.write_hits 3983127 # DTB write hits +system.cpu2.dtb.write_misses 9793 # DTB write misses system.cpu2.dtb.flush_tlb 550 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 695 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2739 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 445 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 255 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 2737 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 484 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 262 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 656 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 13954775 # DTB read accesses -system.cpu2.dtb.write_accesses 3989089 # DTB write accesses +system.cpu2.dtb.perms_faults 640 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 13939203 # DTB read accesses +system.cpu2.dtb.write_accesses 3992920 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 17905880 # DTB hits -system.cpu2.dtb.misses 37984 # DTB misses -system.cpu2.dtb.accesses 17943864 # DTB accesses +system.cpu2.dtb.hits 17894440 # DTB hits +system.cpu2.dtb.misses 37683 # DTB misses +system.cpu2.dtb.accesses 17932123 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1717,8 +1737,8 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.inst_hits 4053038 # ITB inst hits -system.cpu2.itb.inst_misses 6578 # ITB inst misses +system.cpu2.itb.inst_hits 4060759 # ITB inst hits +system.cpu2.itb.inst_misses 6577 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits @@ -1727,266 +1747,266 @@ system.cpu2.itb.flush_tlb 550 # Nu system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu2.itb.flush_tlb_mva_asid 695 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 2058 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 2055 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 2441 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 2376 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4059616 # ITB inst accesses -system.cpu2.itb.hits 4053038 # DTB hits -system.cpu2.itb.misses 6578 # DTB misses -system.cpu2.itb.accesses 4059616 # DTB accesses -system.cpu2.numCycles 88208146 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4067336 # ITB inst accesses +system.cpu2.itb.hits 4060759 # DTB hits +system.cpu2.itb.misses 6577 # DTB misses +system.cpu2.itb.accesses 4067336 # DTB accesses +system.cpu2.numCycles 88050542 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 10487397 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32911643 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 5844133 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 3450657 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 74966701 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 679472 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 80302 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 630 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 972 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 72243 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 1263867 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 410 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4050067 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 153217 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2804 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 87212188 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 0.443226 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 1.629212 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 10519234 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32939379 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 5846326 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 3445365 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 74770225 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 681136 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 80231 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 505 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 954 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 72091 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 1265694 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 337 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4057838 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 153485 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2814 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 87049769 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 0.444404 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 1.631683 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 79899565 91.62% 91.62% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 625094 0.72% 92.33% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 698013 0.80% 93.13% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 764181 0.88% 94.01% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 868461 1.00% 95.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 574503 0.66% 95.66% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 981504 1.13% 96.79% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 301305 0.35% 97.13% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2499562 2.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 79735168 91.60% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 627849 0.72% 92.32% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 697488 0.80% 93.12% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 764418 0.88% 94.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 855506 0.98% 94.98% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 578096 0.66% 95.64% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 986877 1.13% 96.78% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 299514 0.34% 97.12% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2504853 2.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 87212188 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.066254 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.373113 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8569138 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 72587758 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 4831209 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 941079 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 281926 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 736866 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 58789 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 34844703 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 196626 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 281926 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 9031224 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 19204705 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 13140033 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5253439 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 40299841 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 33794581 # Number of instructions processed by rename +system.cpu2.fetch.rateDist::total 87049769 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.066397 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.374096 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 8593092 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 72401111 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 4830102 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 941679 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 282689 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 738219 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 58888 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 34839136 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 197306 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 282689 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 9053752 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 19270728 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 13147343 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5254066 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 40040151 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 33787886 # Number of instructions processed by rename system.cpu2.rename.ROBFullEvents 74120 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 29618551 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 37683898 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 1100267 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 36626919 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 154339316 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 41664821 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 4127 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 28795876 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 7831027 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 344066 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 286541 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 5082070 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6089915 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 4400227 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 719431 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 1142118 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32029170 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 669683 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 38616590 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 44993 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 5567256 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 12099893 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 238978 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 87212188 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.442789 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.239118 # Number of insts issued each cycle +system.cpu2.rename.IQFullEvents 29496747 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 37523489 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 1004110 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 36611560 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 154353600 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 41662755 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 4122 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 28819307 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 7792237 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 344984 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 287406 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 5085187 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6095255 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 4404078 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 715172 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 1132058 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32032092 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 661150 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 38610720 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 45237 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 5536917 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 12037471 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 230168 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 87049769 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.443548 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.240485 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 73763195 84.58% 84.58% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 4095516 4.70% 89.28% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2328743 2.67% 91.95% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2051674 2.35% 94.30% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2976748 3.41% 97.71% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 798764 0.92% 98.63% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 739781 0.85% 99.48% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 293068 0.34% 99.81% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 164699 0.19% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 73601742 84.55% 84.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 4103417 4.71% 89.27% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2329810 2.68% 91.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2044829 2.35% 94.29% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2965004 3.41% 97.70% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 800473 0.92% 98.62% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 744836 0.86% 99.47% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 295465 0.34% 99.81% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 164193 0.19% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 87212188 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 87049769 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 122993 5.40% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 1 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1970586 86.46% 91.85% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 185678 8.15% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 123164 5.43% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 2 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1963174 86.51% 91.94% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 182867 8.06% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 12081 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 20207276 52.33% 52.36% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 34218 0.09% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 404 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 14176555 36.71% 89.16% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 4186056 10.84% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 12079 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 20212271 52.35% 52.38% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 34343 0.09% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 410 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 14161220 36.68% 89.15% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 4190397 10.85% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 38616590 # Type of FU issued -system.cpu2.iq.rate 0.437789 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 2279258 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.059023 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 166760031 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 38278238 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 29588244 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 9588 # Number of floating instruction queue reads +system.cpu2.iq.FU_type_0::total 38610720 # Type of FU issued +system.cpu2.iq.rate 0.438506 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 2269207 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.058771 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 166576049 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 38242231 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 29605417 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 9604 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 5150 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 4304 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 40878658 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 5109 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 176007 # Number of loads that had data forwarded from stores +system.cpu2.iq.int_alu_accesses 40862730 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 5118 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 177793 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1107424 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 2018 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 18033 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 469449 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1108149 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 2013 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 17977 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 469749 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5207867 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 3518142 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5186465 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 3515984 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 281926 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 17856855 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 716566 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32817404 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 57776 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6089915 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 4400227 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 491578 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 63121 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 616282 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 18033 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 121106 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 106258 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 227364 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 38297957 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 14051286 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 280797 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 282689 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 17818885 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 827114 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32812972 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 58820 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6095255 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 4404078 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 482366 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 63304 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 726253 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 17977 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 122015 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 106758 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 228773 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 38292590 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 14036165 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 280577 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 118551 # number of nop insts executed -system.cpu2.iew.exec_refs 18186993 # number of memory reference insts executed -system.cpu2.iew.exec_branches 4220297 # Number of branches executed -system.cpu2.iew.exec_stores 4135707 # Number of stores executed -system.cpu2.iew.exec_rate 0.434177 # Inst execution rate -system.cpu2.iew.wb_sent 34852514 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 29592548 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 17266310 # num instructions producing a value -system.cpu2.iew.wb_consumers 30698955 # num instructions consuming a value +system.cpu2.iew.exec_nop 119730 # number of nop insts executed +system.cpu2.iew.exec_refs 18176329 # number of memory reference insts executed +system.cpu2.iew.exec_branches 4221740 # Number of branches executed +system.cpu2.iew.exec_stores 4140164 # Number of stores executed +system.cpu2.iew.exec_rate 0.434893 # Inst execution rate +system.cpu2.iew.wb_sent 34848706 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 29609721 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 17270580 # num instructions producing a value +system.cpu2.iew.wb_consumers 30711387 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.335485 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.562440 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.336281 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.562351 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 5479640 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 430705 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 190919 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 86342246 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.312843 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.237203 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 5477647 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 430982 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 191637 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 86152512 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.313795 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.238508 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 77364915 89.60% 89.60% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4177735 4.84% 94.44% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1290086 1.49% 95.94% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 753837 0.87% 96.81% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 490440 0.57% 97.38% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 381562 0.44% 97.82% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 374801 0.43% 98.25% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 197147 0.23% 98.48% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1311723 1.52% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 77159399 89.56% 89.56% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4186602 4.86% 94.42% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1295333 1.50% 95.92% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 754876 0.88% 96.80% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 491618 0.57% 97.37% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 381305 0.44% 97.81% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 375733 0.44% 98.25% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 196216 0.23% 98.48% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1311430 1.52% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 86342246 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 22875674 # Number of instructions committed -system.cpu2.commit.committedOps 27011607 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 86152512 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 22893469 # Number of instructions committed +system.cpu2.commit.committedOps 27034243 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8913269 # Number of memory references committed -system.cpu2.commit.loads 4982491 # Number of loads committed -system.cpu2.commit.membars 117220 # Number of memory barriers committed -system.cpu2.commit.branches 3644555 # Number of branches committed +system.cpu2.commit.refs 8921435 # Number of memory references committed +system.cpu2.commit.loads 4987106 # Number of loads committed +system.cpu2.commit.membars 117312 # Number of memory barriers committed +system.cpu2.commit.branches 3648396 # Number of branches committed system.cpu2.commit.fp_insts 4270 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 23908542 # Number of committed integer instructions. -system.cpu2.commit.function_calls 341319 # Number of function calls committed. +system.cpu2.commit.int_insts 23927319 # Number of committed integer instructions. +system.cpu2.commit.function_calls 341825 # Number of function calls committed. system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 18065773 66.88% 66.88% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 32161 0.12% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 18080099 66.88% 66.88% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 32299 0.12% 67.00% # Class of committed instruction system.cpu2.commit.op_class_0::IntDiv 0 0.00% 67.00% # Class of committed instruction system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 67.00% # Class of committed instruction system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 67.00% # Class of committed instruction @@ -2010,36 +2030,36 @@ system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 67.00% # system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 67.00% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 67.00% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 404 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 410 0.00% 67.00% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 67.00% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.00% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 4982491 18.45% 85.45% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 3930778 14.55% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 4987106 18.45% 85.45% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 3934329 14.55% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 27011607 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1311723 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 27034243 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1311430 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 116854146 # The number of ROB reads -system.cpu2.rob.rob_writes 65855440 # The number of ROB writes -system.cpu2.timesIdled 179134 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 995958 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3544369510 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 22801865 # Number of Instructions Simulated -system.cpu2.committedOps 26937798 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 3.868462 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 3.868462 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.258501 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.258501 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 45014030 # number of integer regfile reads -system.cpu2.int_regfile_writes 19144459 # number of integer regfile writes -system.cpu2.fp_regfile_reads 47113 # number of floating regfile reads +system.cpu2.rob.rob_reads 116684345 # The number of ROB reads +system.cpu2.rob.rob_writes 65897015 # The number of ROB writes +system.cpu2.timesIdled 179321 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1000773 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3544672545 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 22819105 # Number of Instructions Simulated +system.cpu2.committedOps 26959879 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 3.858633 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 3.858633 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.259159 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.259159 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 45005013 # number of integer regfile reads +system.cpu2.int_regfile_writes 19153075 # number of integer regfile writes +system.cpu2.fp_regfile_reads 47120 # number of floating regfile reads system.cpu2.fp_regfile_writes 45464 # number of floating regfile writes -system.cpu2.cc_regfile_reads 130800569 # number of cc regfile reads -system.cpu2.cc_regfile_writes 12559359 # number of cc regfile writes -system.cpu2.misc_regfile_reads 124603397 # number of misc regfile reads -system.cpu2.misc_regfile_writes 350092 # number of misc regfile writes +system.cpu2.cc_regfile_reads 130804455 # number of cc regfile reads +system.cpu2.cc_regfile_writes 12559622 # number of cc regfile writes +system.cpu2.misc_regfile_reads 122469878 # number of misc regfile reads +system.cpu2.misc_regfile_writes 350259 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2056,10 +2076,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1536004079250 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1536004079250 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1536004079250 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1536004079250 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1536462300750 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1536462300750 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1536462300750 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1536462300750 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 055919fe9..9300fd8b1 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,154 +1,154 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.539697 # Number of seconds simulated -sim_ticks 2539696838000 # Number of ticks simulated -final_tick 2539696838000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.539695 # Number of seconds simulated +sim_ticks 2539695141000 # Number of ticks simulated +final_tick 2539695141000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 33216 # Simulator instruction rate (inst/s) -host_op_rate 40018 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1398403355 # Simulator tick rate (ticks/s) -host_mem_usage 411672 # Number of bytes of host memory used -host_seconds 1816.14 # Real time elapsed on the host -sim_insts 60325607 # Number of instructions simulated -sim_ops 72677421 # Number of ops (including micro ops) simulated +host_inst_rate 55026 # Simulator instruction rate (inst/s) +host_op_rate 66292 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2316696588 # Simulator tick rate (ticks/s) +host_mem_usage 466732 # Number of bytes of host memory used +host_seconds 1096.26 # Real time elapsed on the host +sim_insts 60322278 # Number of instructions simulated +sim_ops 72673006 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 960 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 469568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 3933400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 314240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5155776 # Number of bytes read from this memory -system.physmem.bytes_read::total 130985112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 469568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 314240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 783808 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3774400 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1328880 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1687192 # Number of bytes written to this memory -system.physmem.bytes_written::total 6790472 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 471296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 3922776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 314048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5167104 # Number of bytes read from this memory +system.physmem.bytes_read::total 130987352 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 471296 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 314048 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 785344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3775232 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1328636 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1687436 # Number of bytes written to this memory +system.physmem.bytes_written::total 6791304 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 15 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7337 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 61485 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4910 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 80559 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293132 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58975 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 332220 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 421798 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812993 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47687002 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 353 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 7364 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 61319 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 9 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4907 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 80736 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293167 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58988 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 332159 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 421859 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813006 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47687034 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 378 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 184891 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1548768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 252 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 123731 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2030075 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51575097 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 184891 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 123731 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 308623 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1486162 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 523244 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 664328 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2673733 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1486162 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47687002 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 353 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 185572 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1544585 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 123656 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2034537 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51576014 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 185572 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 123656 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 309228 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1486490 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 523148 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 664425 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2674063 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1486490 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47687034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 378 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 184891 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2072011 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 252 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 123731 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2694403 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54248831 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293132 # Number of read requests accepted -system.physmem.writeReqs 812993 # Number of write requests accepted -system.physmem.readBursts 15293132 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 812993 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 975241856 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 3518592 # Total number of bytes read from write queue -system.physmem.bytesWritten 6826496 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 130985112 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6790472 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 54978 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706304 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4635 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 954958 # Per bank write bursts -system.physmem.perBankRdBursts::1 950647 # Per bank write bursts -system.physmem.perBankRdBursts::2 950811 # Per bank write bursts -system.physmem.perBankRdBursts::3 950999 # Per bank write bursts -system.physmem.perBankRdBursts::4 954856 # Per bank write bursts -system.physmem.perBankRdBursts::5 951881 # Per bank write bursts -system.physmem.perBankRdBursts::6 951736 # Per bank write bursts -system.physmem.perBankRdBursts::7 951699 # Per bank write bursts -system.physmem.perBankRdBursts::8 955454 # Per bank write bursts -system.physmem.perBankRdBursts::9 951840 # Per bank write bursts -system.physmem.perBankRdBursts::10 951452 # Per bank write bursts -system.physmem.perBankRdBursts::11 951010 # Per bank write bursts -system.physmem.perBankRdBursts::12 955349 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 185572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2067733 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 123656 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2698962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54250077 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293167 # Number of read requests accepted +system.physmem.writeReqs 813006 # Number of write requests accepted +system.physmem.readBursts 15293167 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813006 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 975220032 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3542656 # Total number of bytes read from write queue +system.physmem.bytesWritten 6827904 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 130987352 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6791304 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 55354 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706297 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4647 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 954783 # Per bank write bursts +system.physmem.perBankRdBursts::1 950591 # Per bank write bursts +system.physmem.perBankRdBursts::2 950729 # Per bank write bursts +system.physmem.perBankRdBursts::3 950904 # Per bank write bursts +system.physmem.perBankRdBursts::4 954888 # Per bank write bursts +system.physmem.perBankRdBursts::5 951868 # Per bank write bursts +system.physmem.perBankRdBursts::6 951800 # Per bank write bursts +system.physmem.perBankRdBursts::7 951730 # Per bank write bursts +system.physmem.perBankRdBursts::8 955391 # Per bank write bursts +system.physmem.perBankRdBursts::9 951917 # Per bank write bursts +system.physmem.perBankRdBursts::10 951458 # Per bank write bursts +system.physmem.perBankRdBursts::11 951066 # Per bank write bursts +system.physmem.perBankRdBursts::12 955340 # Per bank write bursts system.physmem.perBankRdBursts::13 951888 # Per bank write bursts -system.physmem.perBankRdBursts::14 952124 # Per bank write bursts -system.physmem.perBankRdBursts::15 951450 # Per bank write bursts -system.physmem.perBankWrBursts::0 6588 # Per bank write bursts -system.physmem.perBankWrBursts::1 6390 # Per bank write bursts -system.physmem.perBankWrBursts::2 6534 # Per bank write bursts -system.physmem.perBankWrBursts::3 6563 # Per bank write bursts -system.physmem.perBankWrBursts::4 6471 # Per bank write bursts +system.physmem.perBankRdBursts::14 951979 # Per bank write bursts +system.physmem.perBankRdBursts::15 951481 # Per bank write bursts +system.physmem.perBankWrBursts::0 6606 # Per bank write bursts +system.physmem.perBankWrBursts::1 6389 # Per bank write bursts +system.physmem.perBankWrBursts::2 6527 # Per bank write bursts +system.physmem.perBankWrBursts::3 6560 # Per bank write bursts +system.physmem.perBankWrBursts::4 6487 # Per bank write bursts system.physmem.perBankWrBursts::5 6764 # Per bank write bursts -system.physmem.perBankWrBursts::6 6747 # Per bank write bursts -system.physmem.perBankWrBursts::7 6681 # Per bank write bursts -system.physmem.perBankWrBursts::8 6996 # Per bank write bursts -system.physmem.perBankWrBursts::9 6810 # Per bank write bursts -system.physmem.perBankWrBursts::10 6454 # Per bank write bursts -system.physmem.perBankWrBursts::11 6114 # Per bank write bursts -system.physmem.perBankWrBursts::12 7081 # Per bank write bursts -system.physmem.perBankWrBursts::13 6669 # Per bank write bursts -system.physmem.perBankWrBursts::14 6965 # Per bank write bursts -system.physmem.perBankWrBursts::15 6837 # Per bank write bursts +system.physmem.perBankWrBursts::6 6744 # Per bank write bursts +system.physmem.perBankWrBursts::7 6672 # Per bank write bursts +system.physmem.perBankWrBursts::8 7003 # Per bank write bursts +system.physmem.perBankWrBursts::9 6796 # Per bank write bursts +system.physmem.perBankWrBursts::10 6466 # Per bank write bursts +system.physmem.perBankWrBursts::11 6118 # Per bank write bursts +system.physmem.perBankWrBursts::12 7066 # Per bank write bursts +system.physmem.perBankWrBursts::13 6690 # Per bank write bursts +system.physmem.perBankWrBursts::14 6968 # Per bank write bursts +system.physmem.perBankWrBursts::15 6830 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2539695718000 # Total gap between requests +system.physmem.totGap 2539694027000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 18 # Read request sizes (log2) system.physmem.readPktSize::3 15138826 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154288 # Read request sizes (log2) +system.physmem.readPktSize::6 154323 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 58975 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1062531 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1005454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 961588 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1062790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 969024 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1031345 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2691523 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2602840 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3403260 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 108695 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 99295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 93778 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 90278 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 18929 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18461 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18290 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 57 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 13 # What read queue length does an incoming req see +system.physmem.writePktSize::6 58988 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1062880 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1005296 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 961490 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1064387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 969141 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1032129 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2687855 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2599195 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3397795 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 112262 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 102458 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 95445 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 91862 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 18918 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18413 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18221 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 49 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -161,43 +161,43 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 294 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 285 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 278 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 275 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 273 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 272 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 265 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6096 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 6085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5876 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5773 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -225,24 +225,24 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1008721 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 973.577780 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 909.477346 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 200.561203 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22290 2.21% 2.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 20048 1.99% 4.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8821 0.87% 5.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2154 0.21% 5.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2027 0.20% 5.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1663 0.16% 5.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9185 0.91% 6.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 821 0.08% 6.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 941712 93.36% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1008721 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6071 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2509.988470 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 47472.970867 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-65535 6043 99.54% 99.54% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1008813 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 973.468756 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 909.284641 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 200.732372 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22320 2.21% 2.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 20114 1.99% 4.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8797 0.87% 5.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2199 0.22% 5.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2055 0.20% 5.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1694 0.17% 5.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9190 0.91% 6.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 817 0.08% 6.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 941627 93.34% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1008813 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6078 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2507.042448 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 47447.723031 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-65535 6050 99.54% 99.54% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::65536-131071 3 0.05% 99.59% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::131072-196607 8 0.13% 99.72% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-262143 5 0.08% 99.80% # Reads before turning the bus around for writes @@ -252,50 +252,51 @@ system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.85% system.physmem.rdPerTurnAround::983040-1.04858e+06 2 0.03% 99.88% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 6 0.10% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6071 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6071 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.569428 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.390583 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.344347 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1 4 0.07% 0.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 2 0.03% 0.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 6 0.10% 0.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 3 0.05% 0.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 4 0.07% 0.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::6 3 0.05% 0.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 1 0.02% 0.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8 3 0.05% 0.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::9 4 0.07% 0.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::10 3 0.05% 0.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::11 3 0.05% 0.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::13 1 0.02% 0.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::14 3 0.05% 0.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 10 0.16% 0.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2784 45.86% 46.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 49 0.81% 47.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1358 22.37% 69.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1417 23.34% 93.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 155 2.55% 95.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 60 0.99% 96.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 36 0.59% 97.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 21 0.35% 97.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 24 0.40% 98.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 17 0.28% 98.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 23 0.38% 98.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 14 0.23% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 10 0.16% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 12 0.20% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 16 0.26% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 11 0.18% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 14 0.23% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6071 # Writes before turning the bus around for reads -system.physmem.totQLat 392019251500 # Total ticks spent queuing -system.physmem.totMemAccLat 677734639000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76190770000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25726.16 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6078 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6078 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.552813 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.369881 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.322612 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1 5 0.08% 0.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 4 0.07% 0.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 4 0.07% 0.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 4 0.07% 0.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5 2 0.03% 0.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::6 2 0.03% 0.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7 3 0.05% 0.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8 1 0.02% 0.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::9 6 0.10% 0.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::10 3 0.05% 0.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::11 2 0.03% 0.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12 3 0.05% 0.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::13 3 0.05% 0.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::14 2 0.03% 0.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::15 13 0.21% 0.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2782 45.77% 46.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 46 0.76% 47.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1401 23.05% 70.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1370 22.54% 93.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 152 2.50% 95.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 75 1.23% 96.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 36 0.59% 97.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 22 0.36% 97.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 24 0.39% 98.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 25 0.41% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 13 0.21% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 15 0.25% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 16 0.26% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 12 0.20% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 9 0.15% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 11 0.18% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 12 0.20% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6078 # Writes before turning the bus around for reads +system.physmem.totQLat 392436805250 # Total ticks spent queuing +system.physmem.totMemAccLat 678145799000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76189065000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25754.14 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44476.16 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 384.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44504.14 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 383.99 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.69 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.58 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s @@ -303,18 +304,18 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 3.02 # Data bus utilization in percentage system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 5.74 # Average read queue length when enqueuing -system.physmem.avgWrQLen 14.90 # Average write queue length when enqueuing -system.physmem.readRowHits 14244888 # Number of row buffer hits during reads -system.physmem.writeRowHits 91209 # Number of row buffer hits during writes +system.physmem.avgRdQLen 6.40 # Average read queue length when enqueuing +system.physmem.avgWrQLen 14.87 # Average write queue length when enqueuing +system.physmem.readRowHits 14244486 # Number of row buffer hits during reads +system.physmem.writeRowHits 91200 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.49 # Row buffer hit rate for writes -system.physmem.avgGap 157685.09 # Average gap between requests +system.physmem.writeRowHitRate 85.47 # Row buffer hit rate for writes +system.physmem.avgGap 157684.51 # Average gap between requests system.physmem.pageHitRate 93.43 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2193828681000 # Time in different power states -system.physmem.memoryStateTime::REF 84806020000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2193361967750 # Time in different power states +system.physmem.memoryStateTime::REF 84805760000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 261061225250 # Time in different power states +system.physmem.memoryStateTime::ACT 261520412250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory @@ -328,280 +329,291 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55193080 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16345666 # Transaction distribution -system.membus.trans_dist::ReadResp 16345666 # Transaction distribution +system.membus.trans_dist::ReadReq 16345693 # Transaction distribution +system.membus.trans_dist::ReadResp 16345693 # Transaction distribution system.membus.trans_dist::WriteReq 763357 # Transaction distribution system.membus.trans_dist::WriteResp 763357 # Transaction distribution -system.membus.trans_dist::Writeback 58975 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4635 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4635 # Transaction distribution -system.membus.trans_dist::ReadExReq 131547 # Transaction distribution -system.membus.trans_dist::ReadExResp 131547 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383056 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::Writeback 58988 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4647 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4647 # Transaction distribution +system.membus.trans_dist::ReadExReq 131549 # Transaction distribution +system.membus.trans_dist::ReadExResp 131549 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383044 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3780 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1884913 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4271753 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885020 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4271848 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34549385 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390478 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16665056 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19063162 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140173690 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140173690 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1487406000 # Layer occupancy (ticks) +system.membus.pkt_count::total 34549480 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2390454 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16668128 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19066210 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 140176738 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 217843 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 217843 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 217843 # Request fanout histogram +system.membus.reqLayer0.occupancy 1488348000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3427500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3508000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17563315500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17564779000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4754319520 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4755343440 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37450374673 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37440252152 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 64063 # number of replacements -system.l2c.tags.tagsinuse 51393.584080 # Cycle average of tags in use -system.l2c.tags.total_refs 1901876 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 129454 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 14.691520 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2528371598500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37072.406553 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 9.476763 # Average occupied blocks per requestor +system.l2c.tags.replacements 64097 # number of replacements +system.l2c.tags.tagsinuse 51403.492359 # Cycle average of tags in use +system.l2c.tags.total_refs 1900046 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 129489 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 14.673416 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2528369126500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 37092.927950 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 9.579992 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000251 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5409.710973 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3302.260075 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 6.209843 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2641.050651 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2952.468970 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.565680 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000145 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 5418.531577 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3300.356905 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 6.423602 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2630.879076 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2944.793006 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.565993 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000146 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.082546 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.050388 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000095 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.040299 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.045051 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.784204 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.082680 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.050359 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000098 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.040144 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.044934 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.784355 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65378 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65379 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 438 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3140 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5952 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55810 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 434 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3142 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5950 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55813 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.997589 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 18903981 # Number of tag accesses -system.l2c.tags.data_accesses 18903981 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 27725 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 7459 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 477090 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 174144 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 29829 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 8048 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 498641 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 211687 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1434623 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 606690 # number of Writeback hits -system.l2c.Writeback_hits::total 606690 # number of Writeback hits +system.l2c.tags.occ_task_id_percent::1024 0.997604 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 18888451 # Number of tag accesses +system.l2c.tags.data_accesses 18888451 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 27538 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 7475 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 477559 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 174980 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 30012 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 8090 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 496617 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 210611 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1432882 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 606482 # number of Writeback hits +system.l2c.Writeback_hits::total 606482 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 30 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 33 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 55364 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 57398 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112762 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 27725 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 7459 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 477090 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 229508 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 29829 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 8048 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 498641 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 269085 # number of demand (read+write) hits -system.l2c.demand_hits::total 1547385 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 27725 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 7459 # number of overall hits -system.l2c.overall_hits::cpu0.inst 477090 # number of overall hits -system.l2c.overall_hits::cpu0.data 229508 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 29829 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 8048 # number of overall hits -system.l2c.overall_hits::cpu1.inst 498641 # number of overall hits -system.l2c.overall_hits::cpu1.data 269085 # number of overall hits -system.l2c.overall_hits::total 1547385 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 14 # number of ReadReq misses +system.l2c.SCUpgradeReq_hits::cpu1.data 1 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 55610 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 57109 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112719 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 27538 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 7475 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 477559 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 230590 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 30012 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 8090 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 496617 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 267720 # number of demand (read+write) hits +system.l2c.demand_hits::total 1545601 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 27538 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 7475 # number of overall hits +system.l2c.overall_hits::cpu0.inst 477559 # number of overall hits +system.l2c.overall_hits::cpu0.data 230590 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 30012 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 8090 # number of overall hits +system.l2c.overall_hits::cpu1.inst 496617 # number of overall hits +system.l2c.overall_hits::cpu1.data 267720 # number of overall hits +system.l2c.overall_hits::total 1545601 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 15 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7229 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6022 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 10 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 4914 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4504 # number of ReadReq misses -system.l2c.ReadReq_misses::total 22694 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 7255 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6034 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 9 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 4911 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4500 # number of ReadReq misses +system.l2c.ReadReq_misses::total 22725 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 1367 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1538 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2905 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 56297 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 76980 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133277 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 14 # number of demand (read+write) misses +system.l2c.UpgradeReq_misses::cpu1.data 1537 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2904 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 56126 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 77166 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133292 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 15 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7229 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 62319 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 10 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 4914 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 81484 # number of demand (read+write) misses -system.l2c.demand_misses::total 155971 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 14 # number of overall misses +system.l2c.demand_misses::cpu0.inst 7255 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 62160 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 9 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 4911 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 81666 # number of demand (read+write) misses +system.l2c.demand_misses::total 156017 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 15 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7229 # number of overall misses -system.l2c.overall_misses::cpu0.data 62319 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 10 # number of overall misses -system.l2c.overall_misses::cpu1.inst 4914 # number of overall misses -system.l2c.overall_misses::cpu1.data 81484 # number of overall misses -system.l2c.overall_misses::total 155971 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1336000 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu0.inst 7255 # number of overall misses +system.l2c.overall_misses::cpu0.data 62160 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 9 # number of overall misses +system.l2c.overall_misses::cpu1.inst 4911 # number of overall misses +system.l2c.overall_misses::cpu1.data 81666 # number of overall misses +system.l2c.overall_misses::total 156017 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1563750 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 82000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 518356500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 443449495 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 747000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 356901000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 338441743 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1659313738 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 162993 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 254989 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 417982 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 4027199927 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 5731646841 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9758846768 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 1336000 # number of demand (read+write) miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 521104500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 442572744 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 713750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 356046000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 335278744 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1657361488 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 185992 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 279488 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 465480 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 4022661419 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 5771447585 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9794109004 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 1563750 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 82000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 518356500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 4470649422 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 747000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 356901000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 6070088584 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 11418160506 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 1336000 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu0.inst 521104500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 4465234163 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 713750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 356046000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 6106726329 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 11451470492 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 1563750 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 82000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 518356500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 4470649422 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 747000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 356901000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 6070088584 # number of overall miss cycles -system.l2c.overall_miss_latency::total 11418160506 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 27739 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 7460 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 484319 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 180166 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 29839 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 8048 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 503555 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 216191 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1457317 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 606690 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 606690 # number of Writeback accesses(hits+misses) +system.l2c.overall_miss_latency::cpu0.inst 521104500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 4465234163 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 713750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 356046000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 6106726329 # number of overall miss cycles +system.l2c.overall_miss_latency::total 11451470492 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 27553 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 7476 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 484814 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 181014 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 30021 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 8090 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 501528 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 215111 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1455607 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 606482 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 606482 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 1384 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1551 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2935 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1553 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2937 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 111661 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 134378 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246039 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 27739 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 7460 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 484319 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 291827 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 29839 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 8048 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 503555 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 350569 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1703356 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 27739 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 7460 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 484319 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 291827 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 29839 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 8048 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 503555 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 350569 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1703356 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000505 # miss rate for ReadReq accesses +system.l2c.SCUpgradeReq_accesses::cpu1.data 1 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 111736 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 134275 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246011 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 27553 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 7476 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 484814 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 292750 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 30021 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 8090 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 501528 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 349386 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1701618 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 27553 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 7476 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 484814 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 292750 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 30021 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 8090 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 501528 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 349386 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1701618 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000544 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000134 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014926 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.033425 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000335 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.009759 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.020833 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.015572 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.014965 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.033334 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000300 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.009792 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.020919 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.015612 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.987717 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991618 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.989779 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.504178 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.572862 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.541691 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000505 # miss rate for demand accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989697 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.988764 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.502309 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.574686 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.541813 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000544 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.000134 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014926 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.213548 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000335 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.009759 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.232434 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.091567 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000505 # miss rate for overall accesses +system.l2c.demand_miss_rate::cpu0.inst 0.014965 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.212331 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000300 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.009792 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.233741 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.091687 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000544 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.000134 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014926 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.213548 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000335 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.009759 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.232434 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.091567 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 95428.571429 # average ReadReq miss latency +system.l2c.overall_miss_rate::cpu0.inst 0.014965 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.212331 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000300 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.009792 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.233741 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.091687 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 104250 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 82000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71705.145940 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 73638.242278 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 74700 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72629.426129 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 75142.482904 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 73116.847537 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 119.234089 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 165.792588 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 143.883649 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 71534.893991 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 74456.311263 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 73222.287176 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 95428.571429 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71826.946933 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 73346.493868 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79305.555556 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72499.694563 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 74506.387556 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 72931.198592 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 136.058522 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 181.839948 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 160.289256 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 71671.977675 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 74792.623500 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 73478.595895 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 104250 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 82000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 71705.145940 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 71738.144418 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 74700 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 72629.426129 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 74494.239164 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 73206.945560 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 95428.571429 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 71826.946933 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 71834.526432 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79305.555556 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 72499.694563 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 74776.851187 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 73398.863534 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 104250 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 82000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 71705.145940 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 71738.144418 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 74700 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 72629.426129 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 74494.239164 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 73206.945560 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 71826.946933 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 71834.526432 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79305.555556 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 72499.694563 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 74776.851187 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 73398.863534 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -610,154 +622,154 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 58975 # number of writebacks -system.l2c.writebacks::total 58975 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 39 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 58988 # number of writebacks +system.l2c.writebacks::total 58988 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 38 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 4 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.data 18 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 39 # number of demand (read+write) MSHR hits +system.l2c.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 6 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 38 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.data 18 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 39 # number of overall MSHR hits +system.l2c.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 6 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 38 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.data 18 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 68 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 14 # number of ReadReq MSHR misses +system.l2c.overall_mshr_hits::total 66 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 15 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 7222 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 5983 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 10 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 4910 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4486 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 22626 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 7249 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 5996 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 9 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 4907 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 4482 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 22659 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu0.data 1367 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1538 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2905 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 56297 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 76980 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 133277 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 14 # number of demand (read+write) MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1537 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2904 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 56126 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 77166 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 133292 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 15 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 7222 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 62280 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 10 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 4910 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 81466 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 155903 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 14 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 7249 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 62122 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 9 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 4907 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 81648 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 155951 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 15 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 7222 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 62280 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 10 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 4910 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 81466 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 155903 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1163500 # number of ReadReq MSHR miss cycles +system.l2c.overall_mshr_misses::cpu0.inst 7249 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 62122 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 9 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 4907 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 81648 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 155951 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1379250 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 70000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 427109500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 366125745 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 625000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 294835000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 281582243 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1371510988 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13679367 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 15384538 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 29063905 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3324764073 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4773094655 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8097858728 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1163500 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 429544750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 365182494 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 603750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 294088000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 278470744 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1369338988 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13675367 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 15376536 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 29051903 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3321727581 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4810247909 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8131975490 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1379250 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 70000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 427109500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 3690889818 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 625000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 294835000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 5054676898 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 9469369716 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1163500 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 429544750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 3686910075 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 603750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 294088000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 5088718653 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 9501314478 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1379250 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 70000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 427109500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 3690889818 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 625000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 294835000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 5054676898 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 9469369716 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6117750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83698669250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 83244575500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 166949362500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 7714617000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 9329751845 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 17044368845 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6117750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 91413286250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 92574327345 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 183993731345 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000505 # mshr miss rate for ReadReq accesses +system.l2c.overall_mshr_miss_latency::cpu0.inst 429544750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 3686910075 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 603750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 294088000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 5088718653 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 9501314478 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 6123500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83706366250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 83236564000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166949053750 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 7705500500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 9339419914 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 17044920414 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6123500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 91411866750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 92575983914 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 183993974164 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000544 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000134 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014912 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.033208 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000335 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009751 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.020750 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015526 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014952 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.033125 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000300 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009784 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.020836 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015567 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.987717 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991618 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.989779 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.504178 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.572862 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541691 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000505 # mshr miss rate for demand accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989697 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.988764 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.502309 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.574686 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541813 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000544 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000134 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014912 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.213414 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000335 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009751 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.232382 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.091527 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000505 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014952 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.212202 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000300 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009784 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.233690 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.091649 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000544 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000134 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014912 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.213414 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000335 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009751 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.232382 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.091527 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 83107.142857 # average ReadReq mshr miss latency +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014952 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.212202 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000300 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009784 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.233690 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091649 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 91950 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59140.058156 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61194.341467 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60047.861507 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62769.113464 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 60616.591002 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10006.852231 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.950585 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.786575 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59057.570972 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62004.347298 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 60759.611396 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 83107.142857 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59255.724928 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 60904.351901 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59932.341553 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62130.911200 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 60432.454566 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10003.926116 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10004.252440 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.098829 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59183.401294 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62336.364578 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 61008.728881 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 91950 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59140.058156 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 59262.842293 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60047.861507 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62046.459848 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 60738.855032 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 83107.142857 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59255.724928 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 59349.507018 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59932.341553 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62325.086383 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 60924.998737 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 91950 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59140.058156 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 59262.842293 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60047.861507 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62046.459848 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 60738.855032 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59255.724928 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 59349.507018 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59932.341553 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62325.086383 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 60924.998737 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -776,46 +788,58 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58696725 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2675214 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2675214 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2673184 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2673184 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763357 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763357 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 606690 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2935 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2937 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 246039 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 246039 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1976942 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5792286 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42218 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 136665 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7948111 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 63231360 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85355770 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 62032 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 230312 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 148879474 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148879474 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 192412 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4956067661 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::Writeback 606482 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2937 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2940 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 246011 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 246011 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1973853 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5791552 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42247 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 136455 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7944107 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 63133312 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85325794 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 62264 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 230296 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 148751666 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 33359 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2344441 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 2344441 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 2344441 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4954098182 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4453658755 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4446552172 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4478828129 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4477877910 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 26774357 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 26748853 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 79740148 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 79493732 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48628247 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16322168 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322168 # Transaction distribution +system.iobus.trans_dist::ReadReq 16322162 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322162 # Transaction distribution system.iobus.trans_dist::WriteReq 8176 # Transaction distribution system.iobus.trans_dist::WriteResp 8176 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7928 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 520 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1028 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -837,41 +861,40 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2383056 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2383044 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32660688 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390478 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123501006 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123501006 # Total data (bytes) +system.iobus.pkt_count::total 32660676 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15856 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 2390454 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 123500982 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3969000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 520000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -915,21 +938,21 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374880000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2374868000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38124261327 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38127481848 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 7765284 # Number of BP lookups -system.cpu0.branchPred.condPredicted 5771603 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 325703 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4845901 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3829041 # Number of BTB hits +system.cpu0.branchPred.lookups 7736387 # Number of BP lookups +system.cpu0.branchPred.condPredicted 5741528 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 324689 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4736478 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 3796485 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 79.016080 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 808445 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 22619 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 80.154178 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 808967 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 22406 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -953,25 +976,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 27181562 # DTB read hits -system.cpu0.dtb.read_misses 37782 # DTB read misses -system.cpu0.dtb.write_hits 5596065 # DTB write hits -system.cpu0.dtb.write_misses 10098 # DTB write misses +system.cpu0.dtb.read_hits 27184101 # DTB read hits +system.cpu0.dtb.read_misses 37692 # DTB read misses +system.cpu0.dtb.write_hits 5601213 # DTB write hits +system.cpu0.dtb.write_misses 10069 # DTB write misses system.cpu0.dtb.flush_tlb 510 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 731 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 726 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5491 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 645 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 284 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 5493 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 558 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 288 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 704 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 27219344 # DTB read accesses -system.cpu0.dtb.write_accesses 5606163 # DTB write accesses +system.cpu0.dtb.perms_faults 698 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 27221793 # DTB read accesses +system.cpu0.dtb.write_accesses 5611282 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 32777627 # DTB hits -system.cpu0.dtb.misses 47880 # DTB misses -system.cpu0.dtb.accesses 32825507 # DTB accesses +system.cpu0.dtb.hits 32785314 # DTB hits +system.cpu0.dtb.misses 47761 # DTB misses +system.cpu0.dtb.accesses 32833075 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -993,712 +1016,720 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 5349242 # ITB inst hits -system.cpu0.itb.inst_misses 7594 # ITB inst misses +system.cpu0.itb.inst_hits 5349776 # ITB inst hits +system.cpu0.itb.inst_misses 7612 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 510 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 731 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 726 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2632 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2622 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 2439 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 2424 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 5356836 # ITB inst accesses -system.cpu0.itb.hits 5349242 # DTB hits -system.cpu0.itb.misses 7594 # DTB misses -system.cpu0.itb.accesses 5356836 # DTB accesses -system.cpu0.numCycles 234138431 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 5357388 # ITB inst accesses +system.cpu0.itb.hits 5349776 # DTB hits +system.cpu0.itb.misses 7612 # DTB misses +system.cpu0.itb.accesses 5357388 # DTB accesses +system.cpu0.numCycles 234157878 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 14733348 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 42294638 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7765284 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4637486 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 215157682 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 899672 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 103093 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 978 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1882 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 100153 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1830103 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 127 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 5346345 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 204670 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3021 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 232377075 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.216391 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.156919 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 14748705 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 42201957 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7736387 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4605452 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 215146781 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 898208 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 106243 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 1405 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1864 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 95051 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1850622 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 160 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 5346983 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 204760 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2833 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 232399808 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.216000 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.156571 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 222728537 95.85% 95.85% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 885926 0.38% 96.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 959241 0.41% 96.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1030592 0.44% 97.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1233052 0.53% 97.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 718062 0.31% 97.93% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1129349 0.49% 98.41% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 448984 0.19% 98.60% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3243332 1.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 222777653 95.86% 95.86% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 886693 0.38% 96.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 957710 0.41% 96.65% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1031526 0.44% 97.10% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1201262 0.52% 97.61% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 716459 0.31% 97.92% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1131800 0.49% 98.41% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 450199 0.19% 98.60% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3246506 1.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 232377075 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.033165 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.180639 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12160999 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 212353937 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6177683 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1309281 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 372986 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 974074 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 78107 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 45045632 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 258698 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 372986 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12774661 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 53419035 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 30524585 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6795741 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 128487965 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 43632543 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1343 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 95385189 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 124519108 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 1934134 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 46283925 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 200651385 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 53129662 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 5272 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 36330469 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 9953456 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 576590 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 492282 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 7436987 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7977179 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6240861 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1088795 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1688387 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 41277277 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1012498 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 59014531 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 58753 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 7256631 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 15830718 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 292140 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 232377075 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.253960 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 0.959343 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 232399808 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.033039 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.180229 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12178110 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 212389955 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6147086 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1310186 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 372224 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 973042 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 78155 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 44916036 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 260169 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 372224 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12790792 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 53545394 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 30504571 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6768689 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 128415973 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 43504199 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1378 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 95402427 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 124537502 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 1839930 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 46109442 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 200228601 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 53009049 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 5261 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 36340147 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 9769295 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 578634 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 493652 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 7443860 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7970278 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6245265 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1090249 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1688574 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 41187030 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 989826 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 58971927 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 58739 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 7127220 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 15644672 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 268943 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 232399808 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.253752 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 0.958915 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 212079469 91.27% 91.27% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6238226 2.68% 93.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 2924438 1.26% 95.21% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2416467 1.04% 96.25% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6166815 2.65% 98.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1071194 0.46% 99.36% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 901941 0.39% 99.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 385048 0.17% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 193477 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 212110796 91.27% 91.27% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6244814 2.69% 93.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 2921782 1.26% 95.21% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2401444 1.03% 96.25% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6174292 2.66% 98.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1067597 0.46% 99.36% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 901998 0.39% 99.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 384604 0.17% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 192481 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 232377075 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 232399808 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 114630 2.27% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 3 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4666706 92.48% 94.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 264598 5.24% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 115073 2.28% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 2 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4670641 92.37% 94.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 270791 5.36% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 15012 0.03% 0.03% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 25515552 43.24% 43.26% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 47770 0.08% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 902 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 27508063 46.61% 89.96% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5927232 10.04% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 15020 0.03% 0.03% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 25465355 43.18% 43.21% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 47791 0.08% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 896 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 27510585 46.65% 89.94% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5932280 10.06% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 59014531 # Type of FU issued -system.cpu0.iq.rate 0.252050 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 5045937 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.085503 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 355498871 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 49563440 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 38260615 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 11956 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6482 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5191 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 64039026 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6430 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 226085 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 58971927 # Type of FU issued +system.cpu0.iq.rate 0.251847 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 5056507 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.085744 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 355447115 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 49321417 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 38218166 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 11793 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6394 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5095 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 64007055 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6359 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 225424 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1459518 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2588 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 24632 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 672041 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1448099 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2516 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 24796 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 671952 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17098280 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 3147229 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17102895 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 3149110 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 372986 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 50915247 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1803662 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 42401043 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 79571 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7977179 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6240861 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 734817 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 139591 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 1596321 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 24632 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 160350 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 132588 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 292938 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 58604130 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 27345857 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 362682 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 372224 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 50935329 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1903194 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 42289333 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 78950 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7970278 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6245265 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 710795 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 138182 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 1696089 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 24796 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 159500 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 133057 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 292557 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 58565137 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 27348453 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 359214 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 111268 # number of nop insts executed -system.cpu0.iew.exec_refs 33208867 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5668977 # Number of branches executed -system.cpu0.iew.exec_stores 5863010 # Number of stores executed -system.cpu0.iew.exec_rate 0.250297 # Inst execution rate -system.cpu0.iew.wb_sent 55434698 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 38265806 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 21645924 # num instructions producing a value -system.cpu0.iew.wb_consumers 38521221 # num instructions consuming a value +system.cpu0.iew.exec_nop 112477 # number of nop insts executed +system.cpu0.iew.exec_refs 33216509 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5651382 # Number of branches executed +system.cpu0.iew.exec_stores 5868056 # Number of stores executed +system.cpu0.iew.exec_rate 0.250110 # Inst execution rate +system.cpu0.iew.wb_sent 55395790 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 38223261 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 21614386 # num instructions producing a value +system.cpu0.iew.wb_consumers 38462259 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.163432 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.561922 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.163237 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.561964 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 7110536 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 720358 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 248726 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 231246727 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.150700 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 0.849611 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 7051288 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 720883 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 247682 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 231240606 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.150761 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 0.850016 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 218753445 94.60% 94.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6297983 2.72% 97.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1708084 0.74% 98.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1059115 0.46% 98.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 644957 0.28% 98.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 581299 0.25% 99.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 449364 0.19% 99.24% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 245033 0.11% 99.35% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1507447 0.65% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 218744105 94.60% 94.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6302358 2.73% 97.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1708730 0.74% 98.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1054896 0.46% 98.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 648771 0.28% 98.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 578680 0.25% 99.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 445136 0.19% 99.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 245162 0.11% 99.35% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1512768 0.65% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 231246727 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 29059194 # Number of instructions committed -system.cpu0.commit.committedOps 34848810 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 231240606 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 29065490 # Number of instructions committed +system.cpu0.commit.committedOps 34862084 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 12086481 # Number of memory references committed -system.cpu0.commit.loads 6517661 # Number of loads committed -system.cpu0.commit.membars 192728 # Number of memory barriers committed -system.cpu0.commit.branches 4958536 # Number of branches committed -system.cpu0.commit.fp_insts 5174 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 30757342 # Number of committed integer instructions. -system.cpu0.commit.function_calls 472350 # Number of function calls committed. +system.cpu0.commit.refs 12095492 # Number of memory references committed +system.cpu0.commit.loads 6522179 # Number of loads committed +system.cpu0.commit.membars 193065 # Number of memory barriers committed +system.cpu0.commit.branches 4958543 # Number of branches committed +system.cpu0.commit.fp_insts 5094 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 30770331 # Number of committed integer instructions. +system.cpu0.commit.function_calls 472637 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 22717072 65.19% 65.19% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 44355 0.13% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 902 0.00% 65.32% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 65.32% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.32% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.32% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 6517661 18.70% 84.02% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5568820 15.98% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 22721291 65.17% 65.17% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 44405 0.13% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 896 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 6522179 18.71% 84.01% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5573313 15.99% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 34848810 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1507447 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 34862084 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1512768 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 270795640 # The number of ROB reads -system.cpu0.rob.rob_writes 85052492 # The number of ROB writes -system.cpu0.timesIdled 264396 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 1761356 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2270391996 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 28992496 # Number of Instructions Simulated -system.cpu0.committedOps 34782112 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 8.075829 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 8.075829 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.123826 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.123826 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 66468797 # number of integer regfile reads -system.cpu0.int_regfile_writes 24185826 # number of integer regfile writes -system.cpu0.fp_regfile_reads 44758 # number of floating regfile reads -system.cpu0.fp_regfile_writes 41844 # number of floating regfile writes -system.cpu0.cc_regfile_reads 196782773 # number of cc regfile reads -system.cpu0.cc_regfile_writes 15711716 # number of cc regfile writes -system.cpu0.misc_regfile_reads 291428250 # number of misc regfile reads -system.cpu0.misc_regfile_writes 565781 # number of misc regfile writes -system.cpu0.icache.tags.replacements 988317 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.592753 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 9970376 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 988829 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.083013 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6654117250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 184.676713 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 326.916040 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.360697 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.638508 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 270737391 # The number of ROB reads +system.cpu0.rob.rob_writes 84952654 # The number of ROB writes +system.cpu0.timesIdled 265059 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 1758070 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2270312982 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 28998871 # Number of Instructions Simulated +system.cpu0.committedOps 34795465 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 8.074724 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 8.074724 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.123843 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.123843 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 66418764 # number of integer regfile reads +system.cpu0.int_regfile_writes 24158486 # number of integer regfile writes +system.cpu0.fp_regfile_reads 44743 # number of floating regfile reads +system.cpu0.fp_regfile_writes 41780 # number of floating regfile writes +system.cpu0.cc_regfile_reads 196661933 # number of cc regfile reads +system.cpu0.cc_regfile_writes 15655112 # number of cc regfile writes +system.cpu0.misc_regfile_reads 292292897 # number of misc regfile reads +system.cpu0.misc_regfile_writes 565980 # number of misc regfile writes +system.cpu0.icache.tags.replacements 986757 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.592826 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 9965260 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 987269 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.093764 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6651821250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 184.507996 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 327.084830 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.360367 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.638838 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999205 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 155 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 157 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 12025421 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 12025421 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 4823915 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5146461 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 9970376 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 4823915 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5146461 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 9970376 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 4823915 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5146461 # number of overall hits -system.cpu0.icache.overall_hits::total 9970376 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 522311 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 543898 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1066209 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 522311 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 543898 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1066209 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 522311 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 543898 # number of overall misses -system.cpu0.icache.overall_misses::total 1066209 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7237674573 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 7341681631 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14579356204 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7237674573 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 7341681631 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14579356204 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7237674573 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 7341681631 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14579356204 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5346226 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5690359 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 11036585 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5346226 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5690359 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 11036585 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5346226 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5690359 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 11036585 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.097697 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.095582 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.096607 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.097697 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.095582 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.096607 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.097697 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.095582 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.096607 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13857.021148 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13498.269218 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13674.013448 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13857.021148 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13498.269218 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13674.013448 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13857.021148 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13498.269218 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13674.013448 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4158 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 12017349 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 12017349 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 4823854 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 5141406 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 9965260 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 4823854 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 5141406 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 9965260 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 4823854 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 5141406 # number of overall hits +system.cpu0.icache.overall_hits::total 9965260 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 523011 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 541799 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1064810 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 523011 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 541799 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1064810 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 523011 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 541799 # number of overall misses +system.cpu0.icache.overall_misses::total 1064810 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7244933790 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 7308182079 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14553115869 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7244933790 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 7308182079 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14553115869 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7244933790 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 7308182079 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14553115869 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 5346865 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 5683205 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 11030070 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 5346865 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 5683205 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 11030070 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 5346865 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 5683205 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 11030070 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.097816 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.095333 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.096537 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.097816 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.095333 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.096537 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.097816 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.095333 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.096537 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13852.354520 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13488.733052 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13667.335834 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13852.354520 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13488.733052 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13667.335834 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13852.354520 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13488.733052 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13667.335834 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4607 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 274 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 283 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.175182 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.279152 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 37549 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39824 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 77373 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 37549 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 39824 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 77373 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 37549 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 39824 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 77373 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 484762 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 504074 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 988836 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 484762 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 504074 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 988836 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 484762 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 504074 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 988836 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5888564763 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5971220456 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11859785219 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5888564763 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5971220456 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11859785219 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5888564763 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5971220456 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11859785219 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8523250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8523250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8523250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 8523250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090674 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.088584 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.089596 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090674 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.088584 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.089596 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090674 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.088584 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.089596 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12147.331604 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11845.920353 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11993.682693 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12147.331604 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11845.920353 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11993.682693 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12147.331604 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11845.920353 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11993.682693 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 37777 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39754 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 77531 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 37777 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 39754 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 77531 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 37777 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 39754 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 77531 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 485234 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 502045 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 987279 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 485234 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 502045 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 987279 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 485234 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 502045 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 987279 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5896477037 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5947728017 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11844205054 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5896477037 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5947728017 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11844205054 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5896477037 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5947728017 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11844205054 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8530500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8530500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8530500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 8530500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090751 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.088338 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.089508 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090751 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.088338 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.089508 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090751 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.088338 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.089508 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12151.821672 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11847.001797 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11996.816557 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12151.821672 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11847.001797 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11996.816557 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12151.821672 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11847.001797 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11996.816557 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 641884 # number of replacements +system.cpu0.dcache.tags.replacements 641624 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.993418 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 19756750 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 642396 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 30.754784 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 19749835 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 642136 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 30.756467 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 42094250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 133.972457 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 378.020960 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.261665 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.738322 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 133.332182 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 378.661236 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.260414 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.739573 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 293 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 95317436 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 95317436 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5857300 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6196947 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 12054247 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3502178 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3641154 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 7143332 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 35246 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 29793 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 65039 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 110182 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 133190 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 243372 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 112371 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 135291 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247662 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9359478 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 9838101 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 19197579 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9394724 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 9867894 # number of overall hits -system.cpu0.dcache.overall_hits::total 19262618 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 295687 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 396301 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 691988 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1362259 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1719020 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 3081279 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 73803 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 54706 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 128509 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6350 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6980 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13330 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 95284916 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 95284916 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5852905 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6194424 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 12047329 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3505923 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3637478 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 7143401 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 35429 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 29531 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 64960 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 110357 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 133056 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 243413 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 112492 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 135154 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247646 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9358828 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 9831902 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 19190730 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9394257 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 9861433 # number of overall hits +system.cpu0.dcache.overall_hits::total 19255690 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 296259 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 395495 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 691754 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1362667 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1717725 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 3080392 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 74316 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 54156 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 128472 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6370 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6955 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13325 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1657946 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 2115321 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3773267 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1731749 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 2170027 # number of overall misses -system.cpu0.dcache.overall_misses::total 3901776 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4378228092 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 5755162638 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 10133390730 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 57860586634 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 86029827577 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 143890414211 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 92678240 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 94350988 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 187029228 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_misses::cpu1.data 1 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1658926 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 2113220 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3772146 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1733242 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 2167376 # number of overall misses +system.cpu0.dcache.overall_misses::total 3900618 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4388776307 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 5728170629 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 10116946936 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 57800783004 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 86624659870 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 144425442874 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 92286740 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 93793740 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 186080480 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 26000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 62238814726 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 91784990215 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 154023804941 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 62238814726 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 91784990215 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 154023804941 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6152987 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 6593248 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 12746235 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4864437 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 5360174 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10224611 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 109049 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 84499 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 193548 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 116532 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 140170 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 256702 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 112373 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 135291 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247664 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11017424 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 11953422 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 22970846 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11126473 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 12037921 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 23164394 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.048056 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.060107 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.054290 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.280045 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.320702 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.301359 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.676787 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.647416 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.663964 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054491 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049797 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.051928 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 13000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 39000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 62189559311 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 92352830499 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 154542389810 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 62189559311 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 92352830499 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 154542389810 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6149164 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 6589919 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 12739083 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4868590 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 5355203 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10223793 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 109745 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 83687 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 193432 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 116727 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 140011 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 256738 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 112494 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 135155 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247649 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11017754 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 11945122 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 22962876 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11127499 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 12028809 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 23156308 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.048179 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.060015 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.054302 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.279889 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.320758 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.301296 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.677170 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.647126 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.664171 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054572 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049675 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.051901 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000018 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.150484 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.176964 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.164263 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.155642 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.180266 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.168439 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14806.968490 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14522.200645 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14643.882163 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42473.998435 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 50045.856114 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 46698.275038 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14594.998425 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13517.333524 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14030.699775 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000007 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000012 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.150568 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.176911 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.164271 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.155762 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.180182 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.168447 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14813.984746 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14483.547527 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14625.064598 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42417.393981 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 50429.876651 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 46885.410322 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14487.714286 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13485.800144 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13964.763977 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37539.711623 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 43390.572975 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 40819.747169 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35939.858909 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 42296.704241 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 39475.306871 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 204060 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 43131 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 27157 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 778 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7.514085 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 55.438303 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37487.844130 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 43702.421186 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 40969.355325 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35880.482536 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 42610.433307 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 39619.975555 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 200600 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 41919 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 27184 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 783 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7.379341 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 53.536398 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 606690 # number of writebacks -system.cpu0.dcache.writebacks::total 606690 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 164206 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 218384 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 382590 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1249257 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1583126 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 2832383 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 616 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 758 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1374 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1413463 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 1801510 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 3214973 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1413463 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 1801510 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 3214973 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 131481 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 177917 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 309398 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 113002 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 135894 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 248896 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 42994 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 32087 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 75081 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 5734 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 6222 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11956 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 606482 # number of writebacks +system.cpu0.dcache.writebacks::total 606482 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 164188 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 218355 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 382543 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1249592 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1581925 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 2831517 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 626 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 765 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1391 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1413780 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1800280 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 3214060 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1413780 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1800280 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3214060 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 132071 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 177140 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 309211 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 113075 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 135800 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 248875 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 43244 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 31809 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 75053 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 5744 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 6190 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11934 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 244483 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 313811 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 558294 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 287477 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 345898 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 633375 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1725190273 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2222171472 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3947361745 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4787330436 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6538944348 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11326274784 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 807768256 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 644366504 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1452134760 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 73471759 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72597010 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 146068769 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 1 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 245146 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 312940 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 558086 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 288390 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 344749 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 633139 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1730710058 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2210787235 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3941497293 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4783325934 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6576818347 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11360144281 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 814553760 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 636336252 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1450890012 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72971510 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72018008 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 144989518 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 22000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6512520709 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8761115820 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 15273636529 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7320288965 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9405482324 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 16725771289 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91407551750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90929310002 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182336861752 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 11972132389 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 14721058995 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26693191384 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 103379684139 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 105650368997 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209030053136 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.021369 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026985 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024274 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023230 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025353 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 11000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 33000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6514035992 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8787605582 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15301641574 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7328589752 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9423941834 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16752531586 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91416176750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90920349500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182336526250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 11961680895 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 14731919998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26693600893 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 103377857645 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 105652269498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209030127143 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.021478 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026880 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024273 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023225 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025359 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024343 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.394263 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.379732 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.387919 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.049205 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044389 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046575 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.394041 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.380095 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.388007 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.049209 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044211 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046483 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000018 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.022191 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026253 # mshr miss rate for demand accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000007 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000012 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.022250 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026198 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.024304 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025837 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028734 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.027343 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13121.213506 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12489.933351 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12758.200586 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42365.006248 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 48117.976864 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45506.053870 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18787.929851 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20081.855705 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19340.908619 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12813.351761 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11667.793314 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12217.193794 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025917 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028660 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.027342 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13104.391259 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12480.451818 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12746.950442 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42302.241291 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 48430.179286 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45645.984052 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18836.226066 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20004.912195 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19331.539206 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12703.953691 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11634.573183 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12149.280878 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26637.928645 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27918.447154 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27357.694206 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25463.911774 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 27191.490914 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26407.375234 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26572.067225 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 28080.800096 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27418.071003 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25412.080003 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 27335.661116 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26459.484546 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1709,15 +1740,15 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 8288231 # Number of BP lookups -system.cpu1.branchPred.condPredicted 6165176 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 342380 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 5156418 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 4057157 # Number of BTB hits +system.cpu1.branchPred.lookups 8293404 # Number of BP lookups +system.cpu1.branchPred.condPredicted 6173471 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 340831 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 5168505 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 4065400 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 78.681693 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 881950 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 23449 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 78.657175 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 881063 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 23561 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1741,25 +1772,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 28293531 # DTB read hits -system.cpu1.dtb.read_misses 40544 # DTB read misses -system.cpu1.dtb.write_hits 6190636 # DTB write hits -system.cpu1.dtb.write_misses 14491 # DTB write misses +system.cpu1.dtb.read_hits 28281448 # DTB read hits +system.cpu1.dtb.read_misses 40913 # DTB read misses +system.cpu1.dtb.write_hits 6183126 # DTB write hits +system.cpu1.dtb.write_misses 14267 # DTB write misses system.cpu1.dtb.flush_tlb 506 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 708 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 713 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5400 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 865 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 285 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 5407 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 858 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 300 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 723 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 28334075 # DTB read accesses -system.cpu1.dtb.write_accesses 6205127 # DTB write accesses +system.cpu1.dtb.perms_faults 709 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 28322361 # DTB read accesses +system.cpu1.dtb.write_accesses 6197393 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 34484167 # DTB hits -system.cpu1.dtb.misses 55035 # DTB misses -system.cpu1.dtb.accesses 34539202 # DTB accesses +system.cpu1.dtb.hits 34464574 # DTB hits +system.cpu1.dtb.misses 55180 # DTB misses +system.cpu1.dtb.accesses 34519754 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1781,124 +1812,124 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 5693555 # ITB inst hits -system.cpu1.itb.inst_misses 8207 # ITB inst misses +system.cpu1.itb.inst_hits 5686404 # ITB inst hits +system.cpu1.itb.inst_misses 8235 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 506 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 708 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 713 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2675 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2681 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 2702 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 2705 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5701762 # ITB inst accesses -system.cpu1.itb.hits 5693555 # DTB hits -system.cpu1.itb.misses 8207 # DTB misses -system.cpu1.itb.accesses 5701762 # DTB accesses -system.cpu1.numCycles 237058963 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5694639 # ITB inst accesses +system.cpu1.itb.hits 5686404 # DTB hits +system.cpu1.itb.misses 8235 # DTB misses +system.cpu1.itb.accesses 5694639 # DTB accesses +system.cpu1.numCycles 237046957 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 15389347 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 44896719 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 8288231 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4939107 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 217242159 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 949095 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 106364 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 1987 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 1943 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 92979 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 2091650 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 112 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5690360 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 215494 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3361 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 235400962 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.228809 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.188674 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 15347817 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 44890949 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 8293404 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4946463 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 217272167 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 945647 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 107708 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 1915 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 1869 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 102411 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 2087291 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 117 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5683206 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 214159 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3400 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 235393992 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.228723 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.188286 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 225085908 95.62% 95.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 947634 0.40% 96.02% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1047135 0.44% 96.47% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1048515 0.45% 96.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1240998 0.53% 97.44% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 829745 0.35% 97.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1296822 0.55% 98.34% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 452969 0.19% 98.53% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3451236 1.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 225080067 95.62% 95.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 947919 0.40% 96.02% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1046635 0.44% 96.47% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1047767 0.45% 96.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1244626 0.53% 97.44% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 829831 0.35% 97.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1297650 0.55% 98.34% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 454057 0.19% 98.54% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3445440 1.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 235400962 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.034963 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.189391 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 12590716 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 214453384 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 6500032 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1465156 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 389454 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1047596 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 86470 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 48240012 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 288766 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 389454 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 13272686 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 54002992 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 31282477 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 7201814 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 129249426 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 46761611 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 1258 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 95572539 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 124561907 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 2450017 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 49620172 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 215588900 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 57377506 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 4944 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 39615169 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 10004995 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 609511 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 515718 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8221045 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 8459299 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6818667 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1033426 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1557443 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 44314605 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1045489 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 62743783 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 61525 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 7205140 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 16025571 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 281591 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 235400962 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.266540 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.981476 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 235393992 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.034986 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.189376 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 12555511 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 214484659 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 6498538 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1464859 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 388308 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1045918 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 85921 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 48232824 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 288029 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 388308 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 13237235 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 54097542 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 31323893 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 7199069 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 129145928 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 46754074 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 1435 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 95558668 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 124530529 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 2374363 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 49626992 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 215510826 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 57366811 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 4976 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 39600958 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 10026026 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 608668 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 515191 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8234978 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 8452340 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6808261 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1032874 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1526046 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 44303656 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1049317 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 62721282 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 61124 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 7218810 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 16029580 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 286052 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 235393992 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.266452 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.981415 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 213793871 90.82% 90.82% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6637383 2.82% 93.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3199231 1.36% 95.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2579548 1.10% 96.10% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6422119 2.73% 98.82% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1152982 0.49% 99.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1001630 0.43% 99.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 407456 0.17% 99.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 206742 0.09% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 213794873 90.82% 90.82% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6639662 2.82% 93.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3193505 1.36% 95.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2580445 1.10% 96.10% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6412648 2.72% 98.82% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1155018 0.49% 99.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1003845 0.43% 99.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 407445 0.17% 99.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 206551 0.09% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 235400962 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 235393992 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 146491 2.81% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 1 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 146677 2.81% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 3 0.00% 2.81% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 2.81% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 2.81% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 2.81% # attempts to use FU when none available @@ -1926,184 +1957,184 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 2.81% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 2.81% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.81% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4788852 91.80% 94.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 281237 5.39% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4785763 91.77% 94.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 282272 5.41% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 13506 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 27516436 43.86% 43.88% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46370 0.07% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1209 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 28654021 45.67% 89.62% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6512241 10.38% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 13498 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 27514443 43.87% 43.89% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46382 0.07% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1213 0.00% 43.97% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.97% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 43.97% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.97% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 28642016 45.67% 89.63% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6503730 10.37% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 62743783 # Type of FU issued -system.cpu1.iq.rate 0.264676 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 5216581 # FU busy when requested +system.cpu1.iq.FU_type_0::total 62721282 # Type of FU issued +system.cpu1.iq.rate 0.264594 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 5214715 # FU busy when requested system.cpu1.iq.fu_busy_rate 0.083141 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 366155152 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 52582376 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 41291326 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11482 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6074 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5054 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 67940659 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6199 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 226253 # Number of loads that had data forwarded from stores +system.cpu1.iq.int_inst_queue_reads 366100496 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 52588764 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 41277568 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11899 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6202 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5156 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 67916046 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6453 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 226153 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 1460814 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2639 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 24306 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 652998 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 1459547 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2673 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 24270 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 647934 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 17101900 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 3881798 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 17097171 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 3878321 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 389454 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 50160792 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 3093797 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 45494090 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 85835 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 8459299 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6818667 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 741438 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 149727 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2862513 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 24306 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 166054 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 139765 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 305819 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 62318890 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 28486625 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 369994 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 388308 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 50150951 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 3201381 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 45487056 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 83691 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 8452340 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6808261 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 746320 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 150012 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2969807 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 24270 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 165680 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 138748 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 304428 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 62296746 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 28474223 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 369499 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 133996 # number of nop insts executed -system.cpu1.iew.exec_refs 34929125 # number of memory reference insts executed -system.cpu1.iew.exec_branches 6064585 # Number of branches executed -system.cpu1.iew.exec_stores 6442500 # Number of stores executed -system.cpu1.iew.exec_rate 0.262884 # Inst execution rate -system.cpu1.iew.wb_sent 58464614 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 41296380 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 23329556 # num instructions producing a value -system.cpu1.iew.wb_consumers 41830645 # num instructions consuming a value +system.cpu1.iew.exec_nop 134083 # number of nop insts executed +system.cpu1.iew.exec_refs 34908741 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6065757 # Number of branches executed +system.cpu1.iew.exec_stores 6434518 # Number of stores executed +system.cpu1.iew.exec_rate 0.262803 # Inst execution rate +system.cpu1.iew.wb_sent 58446379 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 41282724 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 23334628 # num instructions producing a value +system.cpu1.iew.wb_consumers 41837805 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.174203 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.557714 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.174154 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.557740 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 7169441 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 763898 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 257160 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 234250313 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.162130 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 0.884909 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 7166738 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 763265 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 256189 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 234203986 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.162086 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 0.884581 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 220821840 94.27% 94.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6746509 2.88% 97.15% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1771690 0.76% 97.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1085849 0.46% 98.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 731494 0.31% 98.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 648369 0.28% 98.96% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 505518 0.22% 99.17% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 281725 0.12% 99.29% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1657319 0.71% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 220778060 94.27% 94.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6743716 2.88% 97.15% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1772623 0.76% 97.90% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1087484 0.46% 98.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 731864 0.31% 98.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 647370 0.28% 98.96% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 507514 0.22% 99.17% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 282341 0.12% 99.29% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1653014 0.71% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 234250313 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 31416794 # Number of instructions committed -system.cpu1.commit.committedOps 37978992 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 234203986 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 31407169 # Number of instructions committed +system.cpu1.commit.committedOps 37961303 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13164154 # Number of memory references committed -system.cpu1.commit.loads 6998485 # Number of loads committed -system.cpu1.commit.membars 211048 # Number of memory barriers committed -system.cpu1.commit.branches 5351716 # Number of branches committed -system.cpu1.commit.fp_insts 5038 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 33506635 # Number of committed integer instructions. -system.cpu1.commit.function_calls 519749 # Number of function calls committed. +system.cpu1.commit.refs 13153120 # Number of memory references committed +system.cpu1.commit.loads 6992793 # Number of loads committed +system.cpu1.commit.membars 210663 # Number of memory barriers committed +system.cpu1.commit.branches 5351172 # Number of branches committed +system.cpu1.commit.fp_insts 5118 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 33489601 # Number of committed integer instructions. +system.cpu1.commit.function_calls 519360 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 24770094 65.22% 65.22% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 43535 0.11% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 1209 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 6998485 18.43% 83.77% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 6165669 16.23% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 24763487 65.23% 65.23% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 43483 0.11% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 1213 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 6992793 18.42% 83.77% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 6160327 16.23% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 37978992 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1657319 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 37961303 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1653014 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 276790751 # The number of ROB reads -system.cpu1.rob.rob_writes 91451122 # The number of ROB writes -system.cpu1.timesIdled 270857 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 1658001 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2279071980 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 31333111 # Number of Instructions Simulated -system.cpu1.committedOps 37895309 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 7.565765 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 7.565765 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.132174 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.132174 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 71132794 # number of integer regfile reads -system.cpu1.int_regfile_writes 26016814 # number of integer regfile writes -system.cpu1.fp_regfile_reads 44316 # number of floating regfile reads -system.cpu1.fp_regfile_writes 42056 # number of floating regfile writes -system.cpu1.cc_regfile_reads 209312794 # number of cc regfile reads -system.cpu1.cc_regfile_writes 17049814 # number of cc regfile writes -system.cpu1.misc_regfile_reads 299103919 # number of misc regfile reads -system.cpu1.misc_regfile_writes 609097 # number of misc regfile writes +system.cpu1.rob.rob_reads 276729293 # The number of ROB reads +system.cpu1.rob.rob_writes 91408516 # The number of ROB writes +system.cpu1.timesIdled 270232 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1652965 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2279190242 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 31323407 # Number of Instructions Simulated +system.cpu1.committedOps 37877541 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 7.567726 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 7.567726 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.132140 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.132140 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 71111518 # number of integer regfile reads +system.cpu1.int_regfile_writes 26004877 # number of integer regfile writes +system.cpu1.fp_regfile_reads 44415 # number of floating regfile reads +system.cpu1.fp_regfile_writes 42120 # number of floating regfile writes +system.cpu1.cc_regfile_reads 209232786 # number of cc regfile reads +system.cpu1.cc_regfile_writes 17062784 # number of cc regfile writes +system.cpu1.misc_regfile_reads 298304880 # number of misc regfile reads +system.cpu1.misc_regfile_writes 608841 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2120,17 +2151,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1732377463327 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1732377463327 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1732377463327 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1732377463327 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1732753268848 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1732753268848 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1732753268848 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1732753268848 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83365 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83356 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 936db738a..231f5f650 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,159 +1,147 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.626162 # Number of seconds simulated -sim_ticks 2626161554000 # Number of ticks simulated -final_tick 2626161554000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.627904 # Number of seconds simulated +sim_ticks 2627903712000 # Number of ticks simulated +final_tick 2627903712000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 476066 # Simulator instruction rate (inst/s) -host_op_rate 568569 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20761634862 # Simulator tick rate (ticks/s) -host_mem_usage 472496 # Number of bytes of host memory used -host_seconds 126.49 # Real time elapsed on the host -sim_insts 60218144 # Number of instructions simulated -sim_ops 71918894 # Number of ops (including micro ops) simulated +host_inst_rate 497056 # Simulator instruction rate (inst/s) +host_op_rate 593637 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 21691918305 # Simulator tick rate (ticks/s) +host_mem_usage 460332 # Number of bytes of host memory used +host_seconds 121.15 # Real time elapsed on the host +sim_insts 60216663 # Number of instructions simulated +sim_ops 71917112 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 306888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4490328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 306056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4559448 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 399040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4560448 # Number of bytes read from this memory -system.physmem.bytes_read::total 134013152 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 306888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 399040 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.inst 399872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4486720 # Number of bytes read from this memory +system.physmem.bytes_read::total 134008544 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 306056 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 399872 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 705928 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3677952 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1536620 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1479452 # Number of bytes written to this memory -system.physmem.bytes_written::total 6694024 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 3673856 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1536536 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1479536 # Number of bytes written to this memory +system.physmem.bytes_written::total 6689928 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 11007 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 70187 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10994 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 71267 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6235 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 71257 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15690721 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57468 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 384155 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 369863 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811486 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47314780 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 6248 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 70105 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15690649 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57404 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 384134 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 369884 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811422 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47283413 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 116858 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1709845 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 116464 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1735013 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 151948 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1736545 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51030049 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 116858 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 151948 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 268806 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1400505 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 585120 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 563351 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2548976 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1400505 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47314780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 152164 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1707338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50994465 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 116464 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 152164 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 268628 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1398018 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 584700 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 563010 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2545728 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1398018 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47283413 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 116858 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2294965 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 116464 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2319714 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 151948 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2299897 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53579025 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15690721 # Number of read requests accepted -system.physmem.writeReqs 811486 # Number of write requests accepted -system.physmem.readBursts 15690721 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 811486 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1004205504 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 640 # Total number of bytes read from write queue -system.physmem.bytesWritten 6711360 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 134013152 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6694024 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 10 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706602 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4522 # Number of requests that are neither read nor write +system.physmem.bw_total::cpu1.inst 152164 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2270348 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53540193 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15690649 # Number of read requests accepted +system.physmem.writeReqs 811422 # Number of write requests accepted +system.physmem.readBursts 15690649 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 811422 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1004200960 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue +system.physmem.bytesWritten 6711168 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 134008544 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6689928 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706554 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4516 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 980414 # Per bank write bursts -system.physmem.perBankRdBursts::1 980046 # Per bank write bursts -system.physmem.perBankRdBursts::2 979991 # Per bank write bursts +system.physmem.perBankRdBursts::1 980044 # Per bank write bursts +system.physmem.perBankRdBursts::2 979984 # Per bank write bursts system.physmem.perBankRdBursts::3 980262 # Per bank write bursts system.physmem.perBankRdBursts::4 986671 # Per bank write bursts system.physmem.perBankRdBursts::5 980424 # Per bank write bursts -system.physmem.perBankRdBursts::6 980568 # Per bank write bursts +system.physmem.perBankRdBursts::6 980555 # Per bank write bursts system.physmem.perBankRdBursts::7 980428 # Per bank write bursts -system.physmem.perBankRdBursts::8 980784 # Per bank write bursts +system.physmem.perBankRdBursts::8 980781 # Per bank write bursts system.physmem.perBankRdBursts::9 980432 # Per bank write bursts system.physmem.perBankRdBursts::10 979731 # Per bank write bursts -system.physmem.perBankRdBursts::11 979594 # Per bank write bursts -system.physmem.perBankRdBursts::12 980346 # Per bank write bursts -system.physmem.perBankRdBursts::13 980257 # Per bank write bursts +system.physmem.perBankRdBursts::11 979566 # Per bank write bursts +system.physmem.perBankRdBursts::12 980337 # Per bank write bursts +system.physmem.perBankRdBursts::13 980248 # Per bank write bursts system.physmem.perBankRdBursts::14 980396 # Per bank write bursts system.physmem.perBankRdBursts::15 980367 # Per bank write bursts -system.physmem.perBankWrBursts::0 6649 # Per bank write bursts -system.physmem.perBankWrBursts::1 6328 # Per bank write bursts -system.physmem.perBankWrBursts::2 6318 # Per bank write bursts +system.physmem.perBankWrBursts::0 6669 # Per bank write bursts +system.physmem.perBankWrBursts::1 6337 # Per bank write bursts +system.physmem.perBankWrBursts::2 6309 # Per bank write bursts system.physmem.perBankWrBursts::3 6427 # Per bank write bursts -system.physmem.perBankWrBursts::4 6389 # Per bank write bursts -system.physmem.perBankWrBursts::5 6673 # Per bank write bursts -system.physmem.perBankWrBursts::6 6856 # Per bank write bursts -system.physmem.perBankWrBursts::7 6766 # Per bank write bursts -system.physmem.perBankWrBursts::8 7040 # Per bank write bursts -system.physmem.perBankWrBursts::9 6684 # Per bank write bursts -system.physmem.perBankWrBursts::10 6144 # Per bank write bursts -system.physmem.perBankWrBursts::11 6041 # Per bank write bursts -system.physmem.perBankWrBursts::12 6664 # Per bank write bursts -system.physmem.perBankWrBursts::13 6480 # Per bank write bursts -system.physmem.perBankWrBursts::14 6708 # Per bank write bursts -system.physmem.perBankWrBursts::15 6698 # Per bank write bursts +system.physmem.perBankWrBursts::4 6393 # Per bank write bursts +system.physmem.perBankWrBursts::5 6675 # Per bank write bursts +system.physmem.perBankWrBursts::6 6845 # Per bank write bursts +system.physmem.perBankWrBursts::7 6769 # Per bank write bursts +system.physmem.perBankWrBursts::8 7058 # Per bank write bursts +system.physmem.perBankWrBursts::9 6682 # Per bank write bursts +system.physmem.perBankWrBursts::10 6146 # Per bank write bursts +system.physmem.perBankWrBursts::11 6016 # Per bank write bursts +system.physmem.perBankWrBursts::12 6658 # Per bank write bursts +system.physmem.perBankWrBursts::13 6472 # Per bank write bursts +system.physmem.perBankWrBursts::14 6707 # Per bank write bursts +system.physmem.perBankWrBursts::15 6699 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2626157242500 # Total gap between requests +system.physmem.totGap 2627899414000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 6644 # Read request sizes (log2) system.physmem.readPktSize::3 15532042 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 152035 # Read request sizes (log2) +system.physmem.readPktSize::6 151963 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 57468 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1139192 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 982322 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 987642 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1099516 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 997956 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1065450 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2766854 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2672571 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3490866 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 121692 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 109210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 101989 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 98650 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19380 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18786 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18596 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 38 # What read queue length does an incoming req see +system.physmem.writePktSize::6 57404 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1139478 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 982369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 987635 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1091943 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 997696 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1062131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2775683 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2686264 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3513182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 110777 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 100216 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 94857 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 91541 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19322 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18831 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18688 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -169,40 +157,40 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 345 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 338 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 333 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 329 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 328 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 323 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5813 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5801 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5824 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -233,349 +221,371 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1040256 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 971.796235 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 905.926694 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 203.945376 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22813 2.19% 2.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22914 2.20% 4.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8969 0.86% 5.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2415 0.23% 5.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2270 0.22% 5.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1819 0.17% 5.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9086 0.87% 6.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 877 0.08% 6.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 969093 93.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1040256 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5997 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2616.425880 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 48628.845120 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-65535 5973 99.60% 99.60% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::131072-196607 7 0.12% 99.72% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-262143 4 0.07% 99.78% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1040215 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 971.829985 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 906.043406 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 203.863923 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22728 2.18% 2.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22848 2.20% 4.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9187 0.88% 5.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2378 0.23% 5.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2112 0.20% 5.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1712 0.16% 5.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9383 0.90% 6.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 867 0.08% 6.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 969000 93.15% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1040215 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6002 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2614.234255 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 48623.103038 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-65535 5977 99.58% 99.58% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::131072-196607 9 0.15% 99.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-262143 3 0.05% 99.78% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::393216-458751 2 0.03% 99.82% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.83% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.85% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.87% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 7 0.12% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5997 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5997 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.486243 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.330739 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.155795 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1 3 0.05% 0.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 3 0.05% 0.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 4 0.07% 0.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 5 0.08% 0.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 8 0.13% 0.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::6 1 0.02% 0.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 4 0.07% 0.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::9 6 0.10% 0.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::10 3 0.05% 0.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::11 2 0.03% 0.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12 3 0.05% 0.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::13 2 0.03% 0.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 11 0.18% 0.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2055 34.27% 35.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 30 0.50% 35.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3613 60.25% 95.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 37 0.62% 96.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 21 0.35% 96.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 16 0.27% 97.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 14 0.23% 97.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 18 0.30% 97.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 13 0.22% 97.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 29 0.48% 98.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 18 0.30% 98.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 15 0.25% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 9 0.15% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 11 0.18% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 15 0.25% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 16 0.27% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 11 0.18% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5997 # Writes before turning the bus around for reads -system.physmem.totQLat 404022182250 # Total ticks spent queuing -system.physmem.totMemAccLat 698223013500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 78453555000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25749.13 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6002 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6002 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.471176 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.313667 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.128575 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1 4 0.07% 0.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 1 0.02% 0.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 5 0.08% 0.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 9 0.15% 0.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5 6 0.10% 0.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::6 1 0.02% 0.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7 2 0.03% 0.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8 2 0.03% 0.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::9 6 0.10% 0.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::10 3 0.05% 0.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::11 2 0.03% 0.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12 2 0.03% 0.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::13 2 0.03% 0.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::14 2 0.03% 0.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::15 12 0.20% 0.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2065 34.41% 35.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 28 0.47% 35.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3575 59.56% 95.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 74 1.23% 96.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 26 0.43% 97.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 13 0.22% 97.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 8 0.13% 97.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 17 0.28% 97.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 20 0.33% 98.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 23 0.38% 98.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 19 0.32% 98.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 14 0.23% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 21 0.35% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 6 0.10% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 12 0.20% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 10 0.17% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 12 0.20% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6002 # Writes before turning the bus around for reads +system.physmem.totQLat 402684411250 # Total ticks spent queuing +system.physmem.totMemAccLat 696883911250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 78453200000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25663.99 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44499.13 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 382.39 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.56 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.03 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44413.99 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 382.13 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.55 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.99 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.55 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.01 # Data bus utilization in percentage system.physmem.busUtilRead 2.99 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.57 # Average read queue length when enqueuing -system.physmem.avgWrQLen 16.75 # Average write queue length when enqueuing -system.physmem.readRowHits 14667428 # Number of row buffer hits during reads -system.physmem.writeRowHits 87892 # Number of row buffer hits during writes +system.physmem.avgRdQLen 6.42 # Average read queue length when enqueuing +system.physmem.avgWrQLen 16.63 # Average write queue length when enqueuing +system.physmem.readRowHits 14667378 # Number of row buffer hits during reads +system.physmem.writeRowHits 87909 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.80 # Row buffer hit rate for writes -system.physmem.avgGap 159139.76 # Average gap between requests +system.physmem.writeRowHitRate 83.83 # Row buffer hit rate for writes +system.physmem.avgGap 159246.64 # Average gap between requests system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2253794386750 # Time in different power states -system.physmem.memoryStateTime::REF 87693060000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2254944154750 # Time in different power states +system.physmem.memoryStateTime::REF 87751300000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 284666999500 # Time in different power states +system.physmem.memoryStateTime::ACT 285203111500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 54492260 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16743274 # Transaction distribution -system.membus.trans_dist::ReadResp 16743274 # Transaction distribution +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 16743265 # Transaction distribution +system.membus.trans_dist::ReadResp 16743265 # Transaction distribution system.membus.trans_dist::WriteReq 763389 # Transaction distribution system.membus.trans_dist::WriteResp 763389 # Transaction distribution -system.membus.trans_dist::Writeback 57468 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4522 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4522 # Transaction distribution -system.membus.trans_dist::ReadExReq 131560 # Transaction distribution -system.membus.trans_dist::ReadExResp 131560 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383096 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::Writeback 57404 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution +system.membus.trans_dist::ReadExReq 131496 # Transaction distribution +system.membus.trans_dist::ReadExResp 131496 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383094 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1891926 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4278894 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1891706 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4278672 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 35342958 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390558 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16450920 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 18849222 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 143105478 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 143105478 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1225841000 # Layer occupancy (ticks) +system.membus.pkt_count::total 35342736 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2390554 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16442216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18840514 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 143096770 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 213883 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 213883 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 213883 # Request fanout histogram +system.membus.reqLayer0.occupancy 1223591000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3816000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3677500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 18171677500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 18171099000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4988493167 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4987168321 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 38432312250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 38457119250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 61927 # number of replacements -system.l2c.tags.tagsinuse 50918.981702 # Cycle average of tags in use -system.l2c.tags.total_refs 1698761 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 127310 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.343500 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2574018004500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37920.667518 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000701 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2858.981429 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3190.441154 # Average occupied blocks per requestor +system.l2c.tags.replacements 61855 # number of replacements +system.l2c.tags.tagsinuse 50930.330896 # Cycle average of tags in use +system.l2c.tags.total_refs 1699074 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 127234 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.353931 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2574032162000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 37932.108407 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000700 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2848.249708 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3170.076160 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000187 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4136.744409 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2812.146305 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.578623 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu1.inst 4147.610246 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2832.285487 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.578798 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.043625 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.048682 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.043461 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.048372 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.063122 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.042910 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.776962 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65383 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2167 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6500 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 56664 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.997665 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17277278 # Number of tag accesses -system.l2c.tags.data_accesses 17277278 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 9702 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3502 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 462087 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 188003 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 9966 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3602 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 382555 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 182697 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1242114 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 596521 # number of Writeback hits -system.l2c.Writeback_hits::total 596521 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 15 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 11 # number of UpgradeReq hits +system.l2c.tags.occ_percent::cpu1.inst 0.063288 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.043217 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.777135 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65379 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2128 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6516 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 56686 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.997604 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 17278829 # Number of tag accesses +system.l2c.tags.data_accesses 17278829 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 9065 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3142 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 447117 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 182266 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 10696 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 4002 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 397485 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 188475 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1242248 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 596597 # number of Writeback hits +system.l2c.Writeback_hits::total 596597 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 60509 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 53980 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 114489 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 9702 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3502 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 462087 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 248512 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 9966 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3602 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 382555 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 236677 # number of demand (read+write) hits -system.l2c.demand_hits::total 1356603 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 9702 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3502 # number of overall hits -system.l2c.overall_hits::cpu0.inst 462087 # number of overall hits -system.l2c.overall_hits::cpu0.data 248512 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 9966 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3602 # number of overall hits -system.l2c.overall_hits::cpu1.inst 382555 # number of overall hits -system.l2c.overall_hits::cpu1.data 236677 # number of overall hits -system.l2c.overall_hits::total 1356603 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 57734 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 56826 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 114560 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 9065 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3142 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 447117 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 240000 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 10696 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 4002 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 397485 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 245301 # number of demand (read+write) hits +system.l2c.demand_hits::total 1356808 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 9065 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3142 # number of overall hits +system.l2c.overall_hits::cpu0.inst 447117 # number of overall hits +system.l2c.overall_hits::cpu0.data 240000 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 10696 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 4002 # number of overall hits +system.l2c.overall_hits::cpu1.inst 397485 # number of overall hits +system.l2c.overall_hits::cpu1.data 245301 # number of overall hits +system.l2c.overall_hits::total 1356808 # number of overall hits system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 4381 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 5534 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 4368 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 5525 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6235 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 4322 # number of ReadReq misses -system.l2c.ReadReq_misses::total 20475 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1413 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1464 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2877 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 65455 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 67750 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133205 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu1.inst 6248 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4323 # number of ReadReq misses +system.l2c.ReadReq_misses::total 20467 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1358 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1517 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2875 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 66435 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 66702 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133137 # number of ReadExReq misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 4381 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 70989 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 4368 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 71960 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 6235 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 72072 # number of demand (read+write) misses -system.l2c.demand_misses::total 153680 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 6248 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 71025 # number of demand (read+write) misses +system.l2c.demand_misses::total 153604 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 4381 # number of overall misses -system.l2c.overall_misses::cpu0.data 70989 # number of overall misses +system.l2c.overall_misses::cpu0.inst 4368 # number of overall misses +system.l2c.overall_misses::cpu0.data 71960 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 6235 # number of overall misses -system.l2c.overall_misses::cpu1.data 72072 # number of overall misses -system.l2c.overall_misses::total 153680 # number of overall misses +system.l2c.overall_misses::cpu1.inst 6248 # number of overall misses +system.l2c.overall_misses::cpu1.data 71025 # number of overall misses +system.l2c.overall_misses::total 153604 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 310394250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 412660750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 305909750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 407234000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 89250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 435283750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 322856500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1481434000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 232490 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 232990 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 465480 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 4532234420 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4730173185 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9262407605 # number of ReadExReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 435495000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 324083500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1472961000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 210491 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 255989 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 466480 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 4624449779 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4644924080 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9269373859 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 149500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 310394250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 4944895170 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 305909750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 5031683779 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 89250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 435283750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 5053029685 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 10743841605 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 435495000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 4969007580 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 10742334859 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 149500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 310394250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 4944895170 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 305909750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 5031683779 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 89250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 435283750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 5053029685 # number of overall miss cycles -system.l2c.overall_miss_latency::total 10743841605 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 9702 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 3504 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 466468 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 193537 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 9967 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 3602 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 388790 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 187019 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1262589 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 596521 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 596521 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1428 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1475 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2903 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 125964 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 121730 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247694 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 9702 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 3504 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 466468 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 319501 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 9967 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 3602 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 388790 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 308749 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1510283 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 9702 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 3504 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 466468 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 319501 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 9967 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 3602 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 388790 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 308749 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1510283 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000571 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.009392 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.028594 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000100 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.016037 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.023110 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016217 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.989496 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.992542 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.991044 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.519633 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.556560 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.537780 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000571 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.009392 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.222187 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000100 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.016037 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.233432 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.101756 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000571 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.009392 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.222187 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000100 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.016037 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.233432 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.101756 # miss rate for overall accesses +system.l2c.overall_miss_latency::cpu1.inst 435495000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 4969007580 # number of overall miss cycles +system.l2c.overall_miss_latency::total 10742334859 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 9065 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 3144 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 451485 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 187791 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 10697 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 4002 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 403733 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 192798 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1262715 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 596597 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 596597 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1371 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1530 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2901 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 124169 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 123528 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247697 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 9065 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 3144 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 451485 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 311960 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 10697 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 4002 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 403733 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 316326 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1510412 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 9065 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 3144 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 451485 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 311960 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 10697 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 4002 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 403733 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 316326 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1510412 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000636 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.009675 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.029421 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000093 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.015476 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.022422 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016209 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990518 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991503 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.991038 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.535037 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.539975 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.537499 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000636 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.009675 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.230671 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000093 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.015476 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.224531 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.101697 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000636 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.009675 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.230671 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000093 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.015476 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.224531 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.101697 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70850.091303 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 74568.259848 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70034.283425 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 73707.511312 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 89250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 69812.951083 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 74700.717261 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 72353.308913 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 164.536447 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 159.146175 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 161.793535 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 69241.989458 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 69818.054391 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 69534.984460 # average ReadExReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 69701.504481 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 74967.268101 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 71967.606391 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 155.000736 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 168.746869 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 162.253913 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 69608.636698 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 69636.953615 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 69622.823550 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 70850.091303 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 69657.202806 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 70034.283425 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 69923.343232 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 69812.951083 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 70110.856990 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 69910.473744 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 69701.504481 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 69961.387962 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 69935.254674 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 70850.091303 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 69657.202806 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 70034.283425 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 69923.343232 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 69812.951083 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 70110.856990 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 69910.473744 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 69701.504481 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 69961.387962 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 69935.254674 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -584,127 +594,127 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 57468 # number of writebacks -system.l2c.writebacks::total 57468 # number of writebacks +system.l2c.writebacks::writebacks 57404 # number of writebacks +system.l2c.writebacks::total 57404 # number of writebacks system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 4381 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 5534 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 4368 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 5525 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 6235 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 4322 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 20475 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1413 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1464 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2877 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 65455 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 67750 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 133205 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 6248 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 4323 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 20467 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1358 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1517 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2875 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 66435 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 66702 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 133137 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 4381 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 70989 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 4368 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 71960 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 6235 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 72072 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 153680 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 6248 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 71025 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 153604 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 4381 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 70989 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 4368 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 71960 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 6235 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 72072 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 153680 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 6248 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 71025 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 153604 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 254926750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 343694250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 250603750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 338351500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 76250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 356241750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 268891500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1223955500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 14131413 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 14641964 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 28773377 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3694483580 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3862282315 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 7556765895 # number of ReadExReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 356302000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 270143000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1215601500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13581358 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 15174017 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 28755375 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3774125721 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3790687920 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7564813641 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 254926750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 4038177830 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 250603750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 4112477221 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 356241750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 4131173815 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 8780721395 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 356302000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 4060830920 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 8780415141 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 254926750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 4038177830 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 250603750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 4112477221 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 76250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 356241750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 4131173815 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 8780721395 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 356302000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 4060830920 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 8780415141 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 349507750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83968607250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82715661500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167033776500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8327021074 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8376108487 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 16703129561 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83883763250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82798029500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167031300500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8325924664 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8377233499 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 16703158163 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 349507750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 92295628324 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 91091769987 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 183736906061 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000571 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.009392 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.028594 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000100 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.016037 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.023110 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.016217 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.989496 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.992542 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.991044 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.519633 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.556560 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.537780 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000571 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009392 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.222187 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000100 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.016037 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.233432 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.101756 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000571 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009392 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.222187 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000100 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.016037 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.233432 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.101756 # mshr miss rate for overall accesses +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 92209687914 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 91175262999 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 183734458663 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000636 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.009675 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.029421 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000093 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.015476 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.022422 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016209 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.990518 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991503 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.991038 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.535037 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.539975 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.537499 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000636 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009675 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.230671 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000093 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.015476 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.224531 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.101697 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000636 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009675 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.230671 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000093 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.015476 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.224531 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.101697 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58189.169139 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62105.936032 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57372.653388 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61240.090498 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 57135.805934 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62214.599722 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 59778.046398 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 57026.568502 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62489.706223 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 59393.242781 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001.341530 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.173792 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56443.107173 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57007.857048 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56730.347172 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.647989 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.869565 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56809.298126 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56830.198795 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 56819.769418 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58189.169139 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56884.557185 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 57372.653388 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57149.488897 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57135.805934 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57320.094003 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 57136.396376 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57026.568502 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57174.669764 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 57162.672463 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58189.169139 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56884.557185 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57372.653388 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57149.488897 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57135.805934 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57320.094003 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 57136.396376 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57026.568502 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57174.669764 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57162.672463 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -723,45 +733,57 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 52868072 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2471434 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2471434 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2471648 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2471648 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763389 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763389 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 596521 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2903 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2903 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 247694 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 247694 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725408 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753877 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20010 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 49988 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7549283 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54763036 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83799850 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 78676 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 138669986 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 138669986 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 170112 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4808749000 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::Writeback 596597 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2901 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2901 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 247697 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 247697 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725344 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5754019 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20105 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50232 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7549700 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54760476 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83807014 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28584 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79048 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 138675122 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 18167 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2128077 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 2128077 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 2128077 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4809198500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3866196743 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3866085496 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4420580083 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4420737429 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 12904000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 12959000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30319250 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30470250 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48225066 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16715396 # Transaction distribution -system.iobus.trans_dist::ReadResp 16715396 # Transaction distribution +system.iobus.trans_dist::ReadReq 16715395 # Transaction distribution +system.iobus.trans_dist::ReadResp 16715395 # Transaction distribution system.iobus.trans_dist::WriteReq 8184 # Transaction distribution system.iobus.trans_dist::WriteResp 8184 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7948 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1044 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -783,41 +805,40 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2383096 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2383094 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 33447160 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15896 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2088 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390558 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 126646814 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 126646814 # Total data (bytes) +system.iobus.pkt_count::total 33447158 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2088 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 2390554 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 126646810 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3979000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 536000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -861,11 +882,11 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 15532032000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374912000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 15532032000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2374910000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 39164946750 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 39130786750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -890,25 +911,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 6652404 # DTB read hits -system.cpu0.dtb.read_misses 6867 # DTB read misses -system.cpu0.dtb.write_hits 5702862 # DTB write hits -system.cpu0.dtb.write_misses 1758 # DTB write misses -system.cpu0.dtb.flush_tlb 2489 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 6554416 # DTB read hits +system.cpu0.dtb.read_misses 6570 # DTB read misses +system.cpu0.dtb.write_hits 5649486 # DTB write hits +system.cpu0.dtb.write_misses 1771 # DTB write misses +system.cpu0.dtb.flush_tlb 2491 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 727 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 6327 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 701 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 28 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 6094 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 129 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 127 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 214 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 6659271 # DTB read accesses -system.cpu0.dtb.write_accesses 5704620 # DTB write accesses +system.cpu0.dtb.perms_faults 206 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 6560986 # DTB read accesses +system.cpu0.dtb.write_accesses 5651257 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12355266 # DTB hits -system.cpu0.dtb.misses 8625 # DTB misses -system.cpu0.dtb.accesses 12363891 # DTB accesses +system.cpu0.dtb.hits 12203902 # DTB hits +system.cpu0.dtb.misses 8341 # DTB misses +system.cpu0.dtb.accesses 12212243 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -930,162 +951,162 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 30639417 # ITB inst hits -system.cpu0.itb.inst_misses 3605 # ITB inst misses +system.cpu0.itb.inst_hits 30237068 # ITB inst hits +system.cpu0.itb.inst_misses 3286 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 2489 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 2491 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 727 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2770 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 701 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 28 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2575 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30643022 # ITB inst accesses -system.cpu0.itb.hits 30639417 # DTB hits -system.cpu0.itb.misses 3605 # DTB misses -system.cpu0.itb.accesses 30643022 # DTB accesses -system.cpu0.numCycles 2625139831 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 30240354 # ITB inst accesses +system.cpu0.itb.hits 30237068 # DTB hits +system.cpu0.itb.misses 3286 # DTB misses +system.cpu0.itb.accesses 30240354 # DTB accesses +system.cpu0.numCycles 2626678485 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 30062808 # Number of instructions committed -system.cpu0.committedOps 36081752 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 32258130 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5851 # Number of float alu accesses -system.cpu0.num_func_calls 1105626 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3807715 # number of instructions that are conditional controls -system.cpu0.num_int_insts 32258130 # number of integer instructions -system.cpu0.num_fp_insts 5851 # number of float instructions -system.cpu0.num_int_register_reads 58404320 # number of times the integer registers were read -system.cpu0.num_int_register_writes 21560333 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4184 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1670 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 129650201 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 14353458 # number of times the CC registers were written -system.cpu0.num_mem_refs 12793226 # number of memory refs -system.cpu0.num_load_insts 6826552 # Number of load instructions -system.cpu0.num_store_insts 5966674 # Number of store instructions -system.cpu0.num_idle_cycles 2291568668.895058 # Number of idle cycles -system.cpu0.num_busy_cycles 333571162.104942 # Number of busy cycles -system.cpu0.not_idle_fraction 0.127068 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.872932 # Percentage of idle cycles -system.cpu0.Branches 5192489 # Number of branches fetched -system.cpu0.op_class::No_OpClass 12678 0.03% 0.03% # Class of executed instruction -system.cpu0.op_class::IntAlu 23764768 64.90% 64.94% # Class of executed instruction -system.cpu0.op_class::IntMult 45316 0.12% 65.06% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 1041 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::MemRead 6826552 18.64% 83.71% # Class of executed instruction -system.cpu0.op_class::MemWrite 5966674 16.29% 100.00% # Class of executed instruction +system.cpu0.committedInsts 29654606 # Number of instructions committed +system.cpu0.committedOps 35595186 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 31825632 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5298 # Number of float alu accesses +system.cpu0.num_func_calls 1084226 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3738020 # number of instructions that are conditional controls +system.cpu0.num_int_insts 31825632 # number of integer instructions +system.cpu0.num_fp_insts 5298 # number of float instructions +system.cpu0.num_int_register_reads 57689563 # number of times the integer registers were read +system.cpu0.num_int_register_writes 21244985 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3888 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1412 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 127837061 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 14183382 # number of times the CC registers were written +system.cpu0.num_mem_refs 12632580 # number of memory refs +system.cpu0.num_load_insts 6723962 # Number of load instructions +system.cpu0.num_store_insts 5908618 # Number of store instructions +system.cpu0.num_idle_cycles 2294291978.637380 # Number of idle cycles +system.cpu0.num_busy_cycles 332386506.362621 # Number of busy cycles +system.cpu0.not_idle_fraction 0.126543 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.873457 # Percentage of idle cycles +system.cpu0.Branches 5094853 # Number of branches fetched +system.cpu0.op_class::No_OpClass 11433 0.03% 0.03% # Class of executed instruction +system.cpu0.op_class::IntAlu 23427860 64.87% 64.90% # Class of executed instruction +system.cpu0.op_class::IntMult 44876 0.12% 65.02% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 988 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::MemRead 6723962 18.62% 83.64% # Class of executed instruction +system.cpu0.op_class::MemWrite 5908618 16.36% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 36617029 # Class of executed instruction +system.cpu0.op_class::total 36117737 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 83036 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 856376 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.872089 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 60655440 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 856888 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 70.785727 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 19833794250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 155.467241 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 355.404848 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.303647 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.694150 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997797 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 856352 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.872863 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 60653974 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 856864 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 70.785999 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 19832593000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 151.975513 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 358.897350 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.296827 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.700971 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997799 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 268 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 62369216 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 62369216 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 30172107 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 30483333 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 60655440 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 30172107 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 30483333 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 60655440 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 30172107 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 30483333 # number of overall hits -system.cpu0.icache.overall_hits::total 60655440 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 467310 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 389578 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 856888 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 467310 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 389578 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 856888 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 467310 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 389578 # number of overall misses -system.cpu0.icache.overall_misses::total 856888 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6355213744 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 5449642249 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11804855993 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6355213744 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 5449642249 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11804855993 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6355213744 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 5449642249 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11804855993 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 30639417 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 30872911 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 61512328 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 30639417 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 30872911 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 61512328 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 30639417 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 30872911 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 61512328 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015252 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.012619 # miss rate for ReadReq accesses +system.cpu0.icache.tags.tag_accesses 62367702 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 62367702 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 29784788 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 30869186 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 60653974 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29784788 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 30869186 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 60653974 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29784788 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 30869186 # number of overall hits +system.cpu0.icache.overall_hits::total 60653974 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 452280 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 404584 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 856864 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 452280 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 404584 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 856864 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 452280 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 404584 # number of overall misses +system.cpu0.icache.overall_misses::total 856864 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6154944247 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 5645212999 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11800157246 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 6154944247 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 5645212999 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11800157246 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 6154944247 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 5645212999 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11800157246 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 30237068 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 31273770 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 61510838 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 30237068 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 31273770 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 61510838 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 30237068 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 31273770 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 61510838 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014958 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.012937 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.013930 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015252 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.012619 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014958 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.012937 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.013930 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015252 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.012619 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014958 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.012937 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.013930 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13599.567191 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13988.578023 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13776.428183 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13599.567191 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13988.578023 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13776.428183 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13599.567191 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13988.578023 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13776.428183 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13608.703120 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13953.129632 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13771.330393 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13608.703120 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13953.129632 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13771.330393 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13608.703120 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13953.129632 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13771.330393 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1094,177 +1115,177 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467310 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 389578 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 856888 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 467310 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 389578 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 856888 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 467310 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 389578 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 856888 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5418947256 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 4668092751 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10087040007 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5418947256 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 4668092751 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10087040007 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5418947256 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 4668092751 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10087040007 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 452280 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 404584 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 856864 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 452280 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 404584 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 856864 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 452280 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 404584 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 856864 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5248743753 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 4833652001 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10082395754 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5248743753 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 4833652001 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10082395754 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5248743753 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 4833652001 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10082395754 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 440846250 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 440846250 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 440846250 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 440846250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.015252 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.012619 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014958 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.012937 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013930 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.015252 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.012619 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014958 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.012937 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.013930 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.015252 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.012619 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014958 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.012937 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.013930 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11596.043860 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11982.434201 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11771.713464 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11596.043860 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11982.434201 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11771.713464 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11596.043860 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11982.434201 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11771.713464 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11605.075955 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11947.214920 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11766.623121 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11605.075955 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11947.214920 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11766.623121 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11605.075955 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11947.214920 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11766.623121 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 627738 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.876206 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 21798920 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 628250 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 34.697843 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 627774 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.876288 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 21798278 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 628286 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 34.694833 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 668864250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 154.066297 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 357.809909 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.300911 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.698847 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 151.360555 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 360.515733 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.295626 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.704132 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999758 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 331 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 330 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 90464778 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 90464778 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5681092 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 5575113 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 11256205 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5059212 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 4912213 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9971425 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 43677 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 40519 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 84196 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 123460 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 112914 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 236374 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 129861 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 117956 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247817 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10740304 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 10487326 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 21227630 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10783981 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 10527845 # number of overall hits -system.cpu0.dcache.overall_hits::total 21311826 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 148158 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 147905 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 296063 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 129911 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 125509 # number of WriteReq misses +system.cpu0.dcache.tags.tag_accesses 90462374 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 90462374 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5593916 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 5661901 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 11255817 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5011257 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 4959929 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9971186 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 42993 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 41213 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 84206 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 120215 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 116148 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 236363 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 126346 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 121459 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247805 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10605173 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 10621830 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 21227003 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10648166 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 10663043 # number of overall hits +system.cpu0.dcache.overall_hits::total 21311209 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 143610 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 152503 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 296113 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 128053 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 127367 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 255420 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 52745 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 47443 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 100188 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6399 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5045 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11444 # number of LoadLockedReq misses -system.cpu0.dcache.demand_misses::cpu0.data 278069 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 273414 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 551483 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 330814 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 320857 # number of overall misses -system.cpu0.dcache.overall_misses::total 651671 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2069842250 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2010175249 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4080017499 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5698764993 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 5806816529 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 11505581522 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 85596250 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 73843500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 159439750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 7768607243 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 7816991778 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 15585599021 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 7768607243 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 7816991778 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 15585599021 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5829250 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 5723018 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 11552268 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5189123 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 5037722 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10226845 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 96422 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 87962 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 184384 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 129859 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 117959 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 247818 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 129861 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 117956 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247817 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11018373 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 10760740 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 21779113 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11114795 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 10848702 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 21963497 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025416 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.025844 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.025628 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025035 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.024914 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.024975 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.547022 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.539358 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.543366 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.049277 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.042769 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046179 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025237 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025408 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.025322 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029763 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.029576 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029671 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13970.506149 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13590.989142 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13780.909803 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43866.685600 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 46266.136524 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 45045.734563 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13376.504141 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14636.967294 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13932.169696 # average LoadLockedReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 27937.696194 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 28590.312778 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 28261.250158 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23483.308575 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 24362.852542 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 23916.361202 # average overall miss latency +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 51303 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 48866 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 100169 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6128 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5315 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 11443 # number of LoadLockedReq misses +system.cpu0.dcache.demand_misses::cpu0.data 271663 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 279870 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 551533 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 322966 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 328736 # number of overall misses +system.cpu0.dcache.overall_misses::total 651702 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2007762250 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2072626499 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4080388749 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5753453329 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 5756409687 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 11509863016 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 81968750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 77716000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 159684750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 7761215579 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 7829036186 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 15590251765 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 7761215579 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 7829036186 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 15590251765 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5737526 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 5814404 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 11551930 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5139310 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 5087296 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10226606 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 94296 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 90079 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 184375 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 126343 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 121463 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 247806 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 126346 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 121459 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247805 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10876836 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 10901700 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 21778536 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10971132 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 10991779 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 21962911 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025030 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.026228 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.025633 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.024916 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.025036 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.024976 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.544063 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.542479 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.543289 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048503 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.043758 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046177 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024976 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025672 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.025325 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029438 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.029907 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029673 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13980.657684 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13590.726078 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13779.836579 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44930.250201 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45195.456335 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 45062.497126 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13376.101501 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14622.013170 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13954.797693 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 28569.277299 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27973.831372 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 28267.124116 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24031.060790 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23815.572940 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 23922.362928 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -1273,101 +1294,101 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs 58 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 596521 # number of writebacks -system.cpu0.dcache.writebacks::total 596521 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 239 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 285 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 524 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 2519 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 2304 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 4823 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2758 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 2589 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 5347 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2758 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 2589 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 5347 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 147919 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 147620 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 295539 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 127392 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 123205 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 250597 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 39219 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 34354 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 73573 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6399 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5045 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11444 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 275311 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 270825 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 546136 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 314530 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 305179 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 619709 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1770558000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1711285000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3481843000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5304830507 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5433667721 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10738498228 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 656374250 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 573183000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1229557250 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72793750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63702500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136496250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7075388507 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7144952721 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 14220341228 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7731762757 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7718135721 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 15449898478 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91728534250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90349964750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182078499000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13171576426 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13067690513 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26239266939 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104900110676 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103417655263 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208317765939 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025375 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025794 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.025583 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024550 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024456 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024504 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.406743 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.390555 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.399021 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.049277 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.042769 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046179 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024987 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025168 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025076 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028298 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028130 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028215 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11969.780758 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11592.501016 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11781.331736 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41641.786823 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44102.655907 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42851.663140 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16736.129172 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16684.607324 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16712.071684 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11375.800906 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12626.858276 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11927.319993 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25699.621544 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26382.175652 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26038.095324 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24581.956433 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25290.520386 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24930.892529 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 596597 # number of writebacks +system.cpu0.dcache.writebacks::total 596597 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 230 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 293 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 523 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 2513 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 2309 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 4822 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2743 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 2602 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 5345 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2743 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 2602 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 5345 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 143380 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 152210 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 295590 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 125540 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 125058 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 250598 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 38283 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 35273 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 73556 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6128 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5315 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11443 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 268920 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 277268 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 546188 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 307203 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 312541 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 619744 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1717602000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1764563500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3482165500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5365627921 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5380262063 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10745889984 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 643406250 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 581822500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1225228750 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69708250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67035000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136743250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7083229921 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7144825563 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 14228055484 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7726636171 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7726648063 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15453284234 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91635621250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90440418250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182076039500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13169946836 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13069221001 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26239167837 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104805568086 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103509639251 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208315207337 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024990 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026178 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.025588 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024427 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024582 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024505 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.405988 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.391579 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.398948 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048503 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.043758 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046177 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024724 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025433 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025079 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028001 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028434 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028218 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11979.369508 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11592.953814 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11780.390067 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42740.384905 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43022.134234 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42880.988611 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16806.578638 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16494.840246 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16657.087797 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11375.367167 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12612.417686 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11949.947566 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26339.543065 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25768.662677 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26049.740170 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25151.564832 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24722.030271 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24934.947711 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1401,25 +1422,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 6516178 # DTB read hits -system.cpu1.dtb.read_misses 7066 # DTB read misses -system.cpu1.dtb.write_hits 5531450 # DTB write hits -system.cpu1.dtb.write_misses 1844 # DTB write misses -system.cpu1.dtb.flush_tlb 2489 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 6613806 # DTB read hits +system.cpu1.dtb.read_misses 7420 # DTB read misses +system.cpu1.dtb.write_hits 5584575 # DTB write hits +system.cpu1.dtb.write_misses 1868 # DTB write misses +system.cpu1.dtb.flush_tlb 2491 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 712 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 6501 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 738 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 35 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 6816 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 152 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 238 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 6523244 # DTB read accesses -system.cpu1.dtb.write_accesses 5533294 # DTB write accesses +system.cpu1.dtb.perms_faults 246 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 6621226 # DTB read accesses +system.cpu1.dtb.write_accesses 5586443 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 12047628 # DTB hits -system.cpu1.dtb.misses 8910 # DTB misses -system.cpu1.dtb.accesses 12056538 # DTB accesses +system.cpu1.dtb.hits 12198381 # DTB hits +system.cpu1.dtb.misses 9288 # DTB misses +system.cpu1.dtb.accesses 12207669 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1441,87 +1462,87 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 30872911 # ITB inst hits -system.cpu1.itb.inst_misses 3673 # ITB inst misses +system.cpu1.itb.inst_hits 31273770 # ITB inst hits +system.cpu1.itb.inst_misses 4023 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 2489 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 2491 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 712 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2794 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 738 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 35 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 3046 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 30876584 # ITB inst accesses -system.cpu1.itb.hits 30872911 # DTB hits -system.cpu1.itb.misses 3673 # DTB misses -system.cpu1.itb.accesses 30876584 # DTB accesses -system.cpu1.numCycles 2627183277 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 31277793 # ITB inst accesses +system.cpu1.itb.hits 31273770 # DTB hits +system.cpu1.itb.misses 4023 # DTB misses +system.cpu1.itb.accesses 31277793 # DTB accesses +system.cpu1.numCycles 2629128939 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 30155336 # Number of instructions committed -system.cpu1.committedOps 35837142 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 32021976 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 4418 # Number of float alu accesses -system.cpu1.num_func_calls 1035067 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3744201 # number of instructions that are conditional controls -system.cpu1.num_int_insts 32021976 # number of integer instructions -system.cpu1.num_fp_insts 4418 # number of float instructions -system.cpu1.num_int_register_reads 57765753 # number of times the integer registers were read -system.cpu1.num_int_register_writes 21325005 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3309 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1110 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 128250854 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 14653287 # number of times the CC registers were written -system.cpu1.num_mem_refs 12466012 # number of memory refs -system.cpu1.num_load_insts 6694911 # Number of load instructions -system.cpu1.num_store_insts 5771101 # Number of store instructions -system.cpu1.num_idle_cycles 2287259017.662607 # Number of idle cycles -system.cpu1.num_busy_cycles 339924259.337393 # Number of busy cycles -system.cpu1.not_idle_fraction 0.129387 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.870613 # Percentage of idle cycles -system.cpu1.Branches 5118153 # Number of branches fetched -system.cpu1.op_class::No_OpClass 15840 0.04% 0.04% # Class of executed instruction -system.cpu1.op_class::IntAlu 23832212 65.55% 65.59% # Class of executed instruction -system.cpu1.op_class::IntMult 42672 0.12% 65.71% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 1070 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::MemRead 6694911 18.41% 84.13% # Class of executed instruction -system.cpu1.op_class::MemWrite 5771101 15.87% 100.00% # Class of executed instruction +system.cpu1.committedInsts 30562057 # Number of instructions committed +system.cpu1.committedOps 36321926 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 32452923 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 4971 # Number of float alu accesses +system.cpu1.num_func_calls 1056400 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3813741 # number of instructions that are conditional controls +system.cpu1.num_int_insts 32452923 # number of integer instructions +system.cpu1.num_fp_insts 4971 # number of float instructions +system.cpu1.num_int_register_reads 58477662 # number of times the integer registers were read +system.cpu1.num_int_register_writes 21639168 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3605 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1368 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 130057431 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 14822724 # number of times the CC registers were written +system.cpu1.num_mem_refs 12626030 # number of memory refs +system.cpu1.num_load_insts 6797131 # Number of load instructions +system.cpu1.num_store_insts 5828899 # Number of store instructions +system.cpu1.num_idle_cycles 2287592720.742589 # Number of idle cycles +system.cpu1.num_busy_cycles 341536218.257411 # Number of busy cycles +system.cpu1.not_idle_fraction 0.129905 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.870095 # Percentage of idle cycles +system.cpu1.Branches 5215542 # Number of branches fetched +system.cpu1.op_class::No_OpClass 17085 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 24167965 65.58% 65.62% # Class of executed instruction +system.cpu1.op_class::IntMult 43107 0.12% 65.74% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 1123 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::MemRead 6797131 18.44% 84.18% # Class of executed instruction +system.cpu1.op_class::MemWrite 5828899 15.82% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 36357806 # Class of executed instruction +system.cpu1.op_class::total 36855310 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.tags.replacements 0 # number of replacements @@ -1540,10 +1561,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1781125703750 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1781125703750 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1781125703750 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1781125703750 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1779782747750 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1779782747750 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1779782747750 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1779782747750 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |