diff options
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm')
10 files changed, 6188 insertions, 0 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini new file mode 100644 index 000000000..424e22d03 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini @@ -0,0 +1,2037 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=true +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=LinuxArmSystem +children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain +atags_addr=256 +boot_loader=/arm/projectscratch/pd/sysrandd/dist/binaries/boot.arm +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_release_addr=65528 +cache_line_size=64 +clk_domain=system.clk_domain +dtb_filename= +early_kernel_symbols=false +enable_context_switch_stats_dump=false +eventq_index=0 +flags_addr=268435504 +gic_cpu_addr=520093952 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false +init_param=0 +kernel=/arm/projectscratch/pd/sysrandd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +load_addr_mask=268435455 +load_offset=0 +machine_type=RealView_PBX +mem_mode=timing +mem_ranges=0:134217727 +memories=system.physmem system.realview.nvmem +multi_proc=true +num_work_ids=16 +panic_on_oops=true +panic_on_panic=true +phys_addr_range_64=40 +readfile=tests/halt.sh +reset_addr_64=0 +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.bridge] +type=Bridge +clk_domain=system.clk_domain +delay=50000 +eventq_index=0 +ranges=268435456:520093695 1073741824:1610612735 +req_size=16 +resp_size=16 +master=system.iobus.slave[0] +slave=system.membus.master[0] + +[system.cf0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +eventq_index=0 +image=system.cf0.image + +[system.cf0.image] +type=CowDiskImage +children=child +child=system.cf0.image.child +eventq_index=0 +image_file= +read_only=false +table_size=65536 + +[system.cf0.image.child] +type=RawDiskImage +eventq_index=0 +image_file=/arm/projectscratch/pd/sysrandd/dist/disks/linux-arm-ael.img +read_only=true + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.cpu0] +type=MinorCPU +children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb tracer +branchPred=system.cpu0.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu0.dstage2_mmu +dtb=system.cpu0.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu0.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu0.interrupts +isa=system.cpu0.isa +istage2_mmu=system.cpu0.istage2_mmu +itb=system.cpu0.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +switched_out=false +system=system +tracer=system.cpu0.tracer +workload= +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + +[system.cpu0.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=4 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu0.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.slave[1] + +[system.cpu0.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu0.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb +tlb=system.cpu0.dtb + +[system.cpu0.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.dstage2_mmu.stage2_tlb.walker + +[system.cpu0.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[5] + +[system.cpu0.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu0.dtb.walker + +[system.cpu0.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[3] + +[system.cpu0.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu0.executeFuncUnits.funcUnits0 system.cpu0.executeFuncUnits.funcUnits1 system.cpu0.executeFuncUnits.funcUnits2 system.cpu0.executeFuncUnits.funcUnits3 system.cpu0.executeFuncUnits.funcUnits4 system.cpu0.executeFuncUnits.funcUnits5 system.cpu0.executeFuncUnits.funcUnits6 + +[system.cpu0.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu0.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu0.executeFuncUnits.funcUnits0.timings + +[system.cpu0.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu0.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu0.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu0.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu0.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu0.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu0.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu0.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu0.executeFuncUnits.funcUnits1.timings + +[system.cpu0.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu0.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu0.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu0.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu0.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu0.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu0.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu0.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu0.executeFuncUnits.funcUnits2.timings + +[system.cpu0.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu0.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu0.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu0.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu0.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu0.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu0.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=9 +opClasses=system.cpu0.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu0.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu0.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu0.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu0.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu0.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu0.executeFuncUnits.funcUnits4.timings + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 +eventq_index=0 +opClasses=system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses25 + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses00] +type=MinorOpClass +eventq_index=0 +opClass=FloatAdd + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses01] +type=MinorOpClass +eventq_index=0 +opClass=FloatCmp + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses02] +type=MinorOpClass +eventq_index=0 +opClass=FloatCvt + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses03] +type=MinorOpClass +eventq_index=0 +opClass=FloatMult + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses04] +type=MinorOpClass +eventq_index=0 +opClass=FloatDiv + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses05] +type=MinorOpClass +eventq_index=0 +opClass=FloatSqrt + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses06] +type=MinorOpClass +eventq_index=0 +opClass=SimdAdd + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses07] +type=MinorOpClass +eventq_index=0 +opClass=SimdAddAcc + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses08] +type=MinorOpClass +eventq_index=0 +opClass=SimdAlu + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses09] +type=MinorOpClass +eventq_index=0 +opClass=SimdCmp + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses10] +type=MinorOpClass +eventq_index=0 +opClass=SimdCvt + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdMult + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMultAcc + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses14] +type=MinorOpClass +eventq_index=0 +opClass=SimdShift + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses15] +type=MinorOpClass +eventq_index=0 +opClass=SimdShiftAcc + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses16] +type=MinorOpClass +eventq_index=0 +opClass=SimdSqrt + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses17] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAdd + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses18] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAlu + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses19] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCmp + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses20] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCvt + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses21] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatDiv + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses22] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMisc + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses23] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMult + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu0.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu0.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu0.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu0.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu0.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu0.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu0.executeFuncUnits.funcUnits5.timings + +[system.cpu0.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses1 + +[system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu0.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu0.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu0.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu0.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu0.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=1 +opClasses=system.cpu0.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu0.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu0.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu0.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu0.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu0.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu0.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=1 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu0.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.toL2Bus.slave[0] + +[system.cpu0.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu0.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu0.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu0.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb +tlb=system.cpu0.itb + +[system.cpu0.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu0.istage2_mmu.stage2_tlb.walker + +[system.cpu0.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[4] + +[system.cpu0.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu0.itb.walker + +[system.cpu0.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[2] + +[system.cpu0.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu1] +type=MinorCPU +children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb tracer +branchPred=system.cpu1.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=1 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu1.dstage2_mmu +dtb=system.cpu1.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu1.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu1.interrupts +isa=system.cpu1.isa +istage2_mmu=system.cpu1.istage2_mmu +itb=system.cpu1.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +switched_out=false +system=system +tracer=system.cpu1.tracer +workload= +dcache_port=system.cpu1.dcache.cpu_side +icache_port=system.cpu1.icache.cpu_side + +[system.cpu1.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + +[system.cpu1.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=4 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu1.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.dcache_port +mem_side=system.toL2Bus.slave[7] + +[system.cpu1.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu1.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb +tlb=system.cpu1.dtb + +[system.cpu1.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.dstage2_mmu.stage2_tlb.walker + +[system.cpu1.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[11] + +[system.cpu1.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu1.dtb.walker + +[system.cpu1.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[9] + +[system.cpu1.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu1.executeFuncUnits.funcUnits0 system.cpu1.executeFuncUnits.funcUnits1 system.cpu1.executeFuncUnits.funcUnits2 system.cpu1.executeFuncUnits.funcUnits3 system.cpu1.executeFuncUnits.funcUnits4 system.cpu1.executeFuncUnits.funcUnits5 system.cpu1.executeFuncUnits.funcUnits6 + +[system.cpu1.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu1.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu1.executeFuncUnits.funcUnits0.timings + +[system.cpu1.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu1.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu1.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu1.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu1.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu1.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu1.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu1.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu1.executeFuncUnits.funcUnits1.timings + +[system.cpu1.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu1.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu1.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu1.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu1.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu1.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu1.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu1.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu1.executeFuncUnits.funcUnits2.timings + +[system.cpu1.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu1.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu1.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu1.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu1.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu1.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu1.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=9 +opClasses=system.cpu1.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu1.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu1.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu1.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu1.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu1.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu1.executeFuncUnits.funcUnits4.timings + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 +eventq_index=0 +opClasses=system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses25 + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses00] +type=MinorOpClass +eventq_index=0 +opClass=FloatAdd + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses01] +type=MinorOpClass +eventq_index=0 +opClass=FloatCmp + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses02] +type=MinorOpClass +eventq_index=0 +opClass=FloatCvt + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses03] +type=MinorOpClass +eventq_index=0 +opClass=FloatMult + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses04] +type=MinorOpClass +eventq_index=0 +opClass=FloatDiv + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses05] +type=MinorOpClass +eventq_index=0 +opClass=FloatSqrt + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses06] +type=MinorOpClass +eventq_index=0 +opClass=SimdAdd + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses07] +type=MinorOpClass +eventq_index=0 +opClass=SimdAddAcc + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses08] +type=MinorOpClass +eventq_index=0 +opClass=SimdAlu + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses09] +type=MinorOpClass +eventq_index=0 +opClass=SimdCmp + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses10] +type=MinorOpClass +eventq_index=0 +opClass=SimdCvt + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdMult + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMultAcc + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses14] +type=MinorOpClass +eventq_index=0 +opClass=SimdShift + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses15] +type=MinorOpClass +eventq_index=0 +opClass=SimdShiftAcc + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses16] +type=MinorOpClass +eventq_index=0 +opClass=SimdSqrt + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses17] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAdd + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses18] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAlu + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses19] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCmp + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses20] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCvt + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses21] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatDiv + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses22] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMisc + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses23] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMult + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu1.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu1.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu1.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu1.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu1.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu1.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu1.executeFuncUnits.funcUnits5.timings + +[system.cpu1.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses1 + +[system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu1.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu1.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu1.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu1.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu1.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=1 +opClasses=system.cpu1.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu1.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu1.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu1.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu1.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu1.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu1.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=1 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu1.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.icache_port +mem_side=system.toL2Bus.slave[6] + +[system.cpu1.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu1.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu1.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu1.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb +tlb=system.cpu1.itb + +[system.cpu1.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu1.istage2_mmu.stage2_tlb.walker + +[system.cpu1.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[10] + +[system.cpu1.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu1.itb.walker + +[system.cpu1.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[8] + +[system.cpu1.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.intrctrl] +type=IntrControl +eventq_index=0 +sys=system + +[system.iobus] +type=NoncoherentBus +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +use_default_range=false +width=8 +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side +slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma + +[system.iocache] +type=BaseCache +children=tags +addr_ranges=0:134217727 +assoc=8 +clk_domain=system.clk_domain +eventq_index=0 +forward_snoops=false +hit_latency=50 +is_top_level=true +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=50 +sequential_access=false +size=1024 +system=system +tags=system.iocache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.iobus.master[25] +mem_side=system.membus.slave[2] + +[system.iocache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=50 +sequential_access=false +size=1024 + +[system.l2c] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=4194304 +system=system +tags=system.l2c.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.l2c.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=4194304 + +[system.membus] +type=CoherentBus +children=badaddr_responder +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=8 +default=system.membus.badaddr_responder.pio +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port +slave=system.system_port system.l2c.mem_side system.iocache.mem_side + +[system.membus.badaddr_responder] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=0 +pio_latency=100000 +pio_size=8 +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access=warn +pio=system.membus.default + +[system.physmem] +type=DRAMCtrl +activation_limit=4 +addr_mapping=RoRaBaChCo +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCL=13750 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=300000 +tRP=13750 +tRRD=6250 +tWTR=7500 +tXAW=40000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[6] + +[system.realview] +type=RealView +children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 +intrctrl=system.intrctrl +max_mem_size=268435456 +mem_start_addr=0 +pci_cfg_base=0 +system=system + +[system.realview.a9scu] +type=A9SCU +clk_domain=system.clk_domain +eventq_index=0 +pio_addr=520093696 +pio_latency=100000 +system=system +pio=system.membus.master[4] + +[system.realview.aaci_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=268451840 +pio_latency=100000 +system=system +pio=system.iobus.master[21] + +[system.realview.cf_ctrl] +type=IdeController +BAR0=402653184 +BAR0LegacyIO=true +BAR0Size=16 +BAR1=402653440 +BAR1LegacyIO=true +BAR1Size=1 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=1 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=31 +InterruptPin=1 +LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=2 +disks=system.cf0 +eventq_index=0 +io_shift=1 +pci_bus=2 +pci_dev=7 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[8] +dma=system.iobus.slave[2] +pio=system.iobus.master[7] + +[system.realview.clcd] +type=Pl111 +amba_id=1315089 +clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 +gic=system.realview.gic +int_num=55 +pio_addr=268566528 +pio_latency=10000 +pixel_clock=41667 +system=system +vnc=system.vncserver +dma=system.iobus.slave[1] +pio=system.iobus.master[4] + +[system.realview.dmac_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=268632064 +pio_latency=100000 +system=system +pio=system.iobus.master[9] + +[system.realview.flash_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=true +pio_addr=1073741824 +pio_latency=100000 +pio_size=536870912 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[24] + +[system.realview.gic] +type=Pl390 +clk_domain=system.clk_domain +cpu_addr=520093952 +cpu_pio_delay=10000 +dist_addr=520097792 +dist_pio_delay=10000 +eventq_index=0 +int_latency=10000 +it_lines=128 +msix_addr=0 +platform=system.realview +system=system +pio=system.membus.master[2] + +[system.realview.gpio0_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=268513280 +pio_latency=100000 +system=system +pio=system.iobus.master[16] + +[system.realview.gpio1_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=268517376 +pio_latency=100000 +system=system +pio=system.iobus.master[17] + +[system.realview.gpio2_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=268521472 +pio_latency=100000 +system=system +pio=system.iobus.master[18] + +[system.realview.kmi0] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=52 +is_mouse=false +pio_addr=268460032 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[5] + +[system.realview.kmi1] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=53 +is_mouse=true +pio_addr=268464128 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[6] + +[system.realview.l2x0_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=520101888 +pio_latency=100000 +pio_size=4095 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.membus.master[3] + +[system.realview.local_cpu_timer] +type=CpuLocalTimer +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_num_timer=29 +int_num_watchdog=30 +pio_addr=520095232 +pio_latency=100000 +system=system +pio=system.membus.master[5] + +[system.realview.mmc_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=268455936 +pio_latency=100000 +system=system +pio=system.iobus.master[22] + +[system.realview.nvmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=false +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=2147483648:2214592511 +port=system.membus.master[1] + +[system.realview.realview_io] +type=RealViewCtrl +clk_domain=system.clk_domain +eventq_index=0 +idreg=0 +pio_addr=268435456 +pio_latency=100000 +proc_id0=201326592 +proc_id1=201327138 +system=system +pio=system.iobus.master[1] + +[system.realview.rtc] +type=PL031 +amba_id=3412017 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=100000 +int_num=42 +pio_addr=268529664 +pio_latency=100000 +system=system +time=Thu Jan 1 00:00:00 2009 +pio=system.iobus.master[23] + +[system.realview.sci_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=268492800 +pio_latency=100000 +system=system +pio=system.iobus.master[20] + +[system.realview.smc_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=269357056 +pio_latency=100000 +system=system +pio=system.iobus.master[13] + +[system.realview.sp810_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=true +pio_addr=268439552 +pio_latency=100000 +system=system +pio=system.iobus.master[14] + +[system.realview.ssp_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=268488704 +pio_latency=100000 +system=system +pio=system.iobus.master[19] + +[system.realview.timer0] +type=Sp804 +amba_id=1316868 +clk_domain=system.clk_domain +clock0=1000000 +clock1=1000000 +eventq_index=0 +gic=system.realview.gic +int_num0=36 +int_num1=36 +pio_addr=268505088 +pio_latency=100000 +system=system +pio=system.iobus.master[2] + +[system.realview.timer1] +type=Sp804 +amba_id=1316868 +clk_domain=system.clk_domain +clock0=1000000 +clock1=1000000 +eventq_index=0 +gic=system.realview.gic +int_num0=37 +int_num1=37 +pio_addr=268509184 +pio_latency=100000 +system=system +pio=system.iobus.master[3] + +[system.realview.uart] +type=Pl011 +clk_domain=system.clk_domain +end_on_eot=false +eventq_index=0 +gic=system.realview.gic +int_delay=100000 +int_num=44 +pio_addr=268472320 +pio_latency=100000 +platform=system.realview +system=system +terminal=system.terminal +pio=system.iobus.master[0] + +[system.realview.uart1_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=268476416 +pio_latency=100000 +system=system +pio=system.iobus.master[10] + +[system.realview.uart2_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=268480512 +pio_latency=100000 +system=system +pio=system.iobus.master[11] + +[system.realview.uart3_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=268484608 +pio_latency=100000 +system=system +pio=system.iobus.master[12] + +[system.realview.watchdog_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=268500992 +pio_latency=100000 +system=system +pio=system.iobus.master[15] + +[system.terminal] +type=Terminal +eventq_index=0 +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.toL2Bus] +type=CoherentBus +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=8 +master=system.l2c.cpu_side +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port + +[system.vncserver] +type=VncServer +eventq_index=0 +frame_capture=false +number=0 +port=5900 + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simerr new file mode 100644 index 000000000..9dee17aa2 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simerr @@ -0,0 +1,13 @@ +warn: Sockets disabled, not accepting vnc client connections +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections +warn: The clidr register always reports 0 caches. +warn: clidr LoUIS field of 0b001 to match current ARM implementations. +warn: The csselr register isn't implemented. +warn: The ccsidr register isn't implemented and always reads as 0. +warn: instruction 'mcr bpiallis' unimplemented +warn: instruction 'mcr icialluis' unimplemented +warn: instruction 'mcr dccimvac' unimplemented +warn: instruction 'mcr dccmvau' unimplemented +warn: instruction 'mcr icimvau' unimplemented +warn: LCD dual screen mode not supported diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout new file mode 100644 index 000000000..a85df4ce3 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout @@ -0,0 +1,17 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled May 7 2014 10:57:46 +gem5 started May 7 2014 12:48:24 +gem5 executing on cz3211bhr8 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual +Global frequency set at 1000000000000 ticks per second +info: kernel located at: /arm/projectscratch/pd/sysrandd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 + 0: system.cpu0.isa: ISA system set to: 0x15f94710 0x15f94710 + 0: system.cpu1.isa: ISA system set to: 0x15f94710 0x15f94710 +info: Using bootloader at address 0x80000000 +info: Using kernel entry physical address at 0x8000 +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 1146870140500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt new file mode 100644 index 000000000..e0d04ae07 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -0,0 +1,1628 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 1146785401000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 81646 # Simulator instruction rate (inst/s) +host_mem_usage 463904 # Number of bytes of host memory used +host_op_rate 105090 # Simulator op (including micro ops) rate (op/s) +host_seconds 758.04 # Real time elapsed on the host +host_tick_rate 1512825196 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 61891142 # Number of instructions simulated +sim_ops 79662361 # Number of ops (including micro ops) simulated +sim_seconds 1.146785 # Number of seconds simulated +sim_ticks 1146785401000 # Number of ticks simulated +system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. +system.cf0.dma_write_txs 0 # Number of DMA write transactions. +system.clk_domain.clock 1000 # Clock period in ticks +system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu0.branchPred.BTBHitPct 71.700237 # BTB Hit Percentage +system.cpu0.branchPred.BTBHits 3353058 # Number of BTB hits +system.cpu0.branchPred.BTBLookups 4676495 # Number of BTB lookups +system.cpu0.branchPred.RASInCorrect 70484 # Number of incorrect RAS predictions. +system.cpu0.branchPred.condIncorrect 650965 # Number of conditional branches incorrect +system.cpu0.branchPred.condPredicted 5175442 # Number of conditional branches predicted +system.cpu0.branchPred.lookups 6862341 # Number of BP lookups +system.cpu0.branchPred.usedRAS 848882 # Number of times the RAS was used to get a target. +system.cpu0.committedInsts 29915640 # Number of instructions committed +system.cpu0.committedOps 39339363 # Number of ops (including micro ops) committed +system.cpu0.cpi 14.502071 # CPI: cycles per instruction +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 161256 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 161256 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 10306.777196 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10306.777196 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 8288.517611 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8288.517611 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 152661 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 152661 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 88586750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 88586750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.053300 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053300 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 8595 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8595 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 21 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 21 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 71065750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 71065750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.053170 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.053170 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 8574 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8574 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.ReadReq_accesses::cpu0.inst 6911519 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6911519 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 14955.771110 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14955.771110 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12252.616817 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12252.616817 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_hits::cpu0.inst 6653819 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6653819 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 3854102215 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3854102215 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.037286 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.037286 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses::cpu0.inst 257700 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 257700 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 51318 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 51318 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 2528719564 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2528719564 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.029861 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029861 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 206382 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 206382 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 170751064250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 170751064250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 161153 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 161153 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 6297.509524 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6297.509524 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 4297.199471 # average StoreCondReq mshr miss latency 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WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42966.373247 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_hits::cpu0.inst 5512001 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5512001 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 15130018902 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 15130018902 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.052829 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.052829 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses::cpu0.inst 307436 # number of WriteReq misses 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overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33592.128474 # average overall miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 26026.541451 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26026.541451 # average overall mshr miss latency +system.cpu0.dcache.demand_hits::cpu0.inst 12165820 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12165820 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency::cpu0.inst 18984121117 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 18984121117 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.044391 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.044391 # miss rate for demand accesses +system.cpu0.dcache.demand_misses::cpu0.inst 565136 # number of demand (read+write) misses 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writebacks +system.cpu0.discardedOps 1920081 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 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to domain restrictions +system.cpu0.dtb.flush_entries 1942 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.hits 14297430 # DTB hits +system.cpu0.dtb.inst_accesses 0 # ITB inst accesses +system.cpu0.dtb.inst_hits 0 # ITB inst hits +system.cpu0.dtb.inst_misses 0 # ITB inst misses +system.cpu0.dtb.misses 23836 # DTB misses +system.cpu0.dtb.perms_faults 284 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.prefetch_faults 167 # Number of TLB faults due to prefetch +system.cpu0.dtb.read_accesses 8272964 # DTB read accesses +system.cpu0.dtb.read_hits 8250552 # DTB read hits +system.cpu0.dtb.read_misses 22412 # DTB read misses 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of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10813145411 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.062659 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.062659 # miss rate for demand accesses +system.cpu0.icache.demand_misses::cpu0.inst 784828 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 784828 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9239301587 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9239301587 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.062659 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.062659 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 784828 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 784828 # number of demand (read+write) MSHR misses +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.overall_accesses::cpu0.inst 12525310 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 12525310 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13777.726344 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13777.726344 # average overall miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11772.390367 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11772.390367 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.icache.overall_hits::cpu0.inst 11740482 # number of overall hits +system.cpu0.icache.overall_hits::total 11740482 # number of overall hits +system.cpu0.icache.overall_miss_latency::cpu0.inst 10813145411 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10813145411 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.062659 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.062659 # miss rate for overall accesses +system.cpu0.icache.overall_misses::cpu0.inst 784828 # number of overall misses +system.cpu0.icache.overall_misses::total 784828 # number of overall misses +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9239301587 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9239301587 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.062659 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.062659 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 784828 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 784828 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 171826250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 171826250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.tags.age_task_id_blocks_1024::2 506 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id +system.cpu0.icache.tags.avg_refs 14.959363 # Average number of references to valid blocks. +system.cpu0.icache.tags.data_accesses 13310138 # Number of data accesses +system.cpu0.icache.tags.occ_blocks::cpu0.inst 510.783510 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.997624 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997624 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.replacements 784313 # number of replacements +system.cpu0.icache.tags.sampled_refs 784825 # Sample count of references to valid blocks. +system.cpu0.icache.tags.tag_accesses 13310138 # Number of tag accesses +system.cpu0.icache.tags.tagsinuse 510.783510 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 11740482 # Total number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10281183000 # Cycle when the warmup percentage was hit. +system.cpu0.idleCycles 80090425 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.ipc 0.068956 # IPC: instructions per cycle +system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.itb.accesses 12532416 # DTB accesses +system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.itb.flush_entries 1298 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.hits 12527520 # DTB hits +system.cpu0.itb.inst_accesses 12532416 # ITB inst accesses +system.cpu0.itb.inst_hits 12527520 # ITB inst hits +system.cpu0.itb.inst_misses 4896 # ITB inst misses +system.cpu0.itb.misses 4896 # DTB misses +system.cpu0.itb.perms_faults 2037 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.itb.read_accesses 0 # DTB read accesses +system.cpu0.itb.read_hits 0 # DTB read hits +system.cpu0.itb.read_misses 0 # DTB read misses +system.cpu0.itb.write_accesses 0 # DTB write accesses +system.cpu0.itb.write_hits 0 # DTB write hits +system.cpu0.itb.write_misses 0 # DTB write misses +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 50383 # number of quiesce instructions executed +system.cpu0.numCycles 433838745 # number of cpu cycles simulated +system.cpu0.numFetchSuspends 39517 # Number of times Execute suspended instruction fetching +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.quiesceCycles 1859796920 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.tickCycles 353748320 # Number of cycles that the CPU actually ticked +system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu1.branchPred.BTBHitPct 75.016066 # BTB Hit Percentage +system.cpu1.branchPred.BTBHits 3095670 # Number of BTB hits +system.cpu1.branchPred.BTBLookups 4126676 # Number of BTB lookups +system.cpu1.branchPred.RASInCorrect 63011 # Number of incorrect RAS predictions. +system.cpu1.branchPred.condIncorrect 435091 # Number of conditional branches incorrect +system.cpu1.branchPred.condPredicted 4929472 # Number of conditional branches predicted +system.cpu1.branchPred.lookups 6347852 # Number of BP lookups +system.cpu1.branchPred.usedRAS 662563 # Number of times the RAS was used to get a target. +system.cpu1.committedInsts 31975502 # Number of instructions committed +system.cpu1.committedOps 40322998 # Number of ops (including micro ops) committed +system.cpu1.cpi 4.679096 # CPI: cycles per instruction +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 89293 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 89293 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 8380.702313 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8380.702313 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 6356.969903 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6356.969903 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 78530 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 78530 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 90201499 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 90201499 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.120536 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120536 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 10763 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 10763 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst 31 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 31 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 68223001 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 68223001 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.120189 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120189 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 10732 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 10732 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.ReadReq_accesses::cpu1.inst 7361037 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 7361037 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14987.876806 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14987.876806 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11879.325450 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11879.325450 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_hits::cpu1.inst 7117762 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 7117762 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 3646175730 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3646175730 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.033049 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.033049 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses::cpu1.inst 243275 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 243275 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 37480 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 37480 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2444705781 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2444705781 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.027957 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.027957 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 205795 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 205795 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 11991518750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 11991518750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 89217 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 89217 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 5027.484214 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5027.484214 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 3027.420473 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3027.420473 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 79145 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 79145 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 50636821 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 50636821 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.112893 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.112893 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 10072 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10072 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 30492179 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30492179 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.112893 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112893 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 10072 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10072 # number of StoreCondReq MSHR misses +system.cpu1.dcache.WriteReq_accesses::cpu1.inst 4649691 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4649691 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 38966.175425 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 38966.175425 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 32823.531262 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32823.531262 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_hits::cpu1.inst 4425658 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4425658 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 8729709179 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 8729709179 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.048182 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.048182 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses::cpu1.inst 224033 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 224033 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 98146 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 98146 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 4132055880 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4132055880 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.027074 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027074 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 125887 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 125887 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 24672578609 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 24672578609 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.demand_accesses::cpu1.inst 12010728 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 12010728 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 26483.357676 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 26483.357676 # average overall miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 19828.515449 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19828.515449 # average overall mshr miss latency +system.cpu1.dcache.demand_hits::cpu1.inst 11543420 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 11543420 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency::cpu1.inst 12375884909 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 12375884909 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.038908 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.038908 # miss rate for demand accesses +system.cpu1.dcache.demand_misses::cpu1.inst 467308 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 467308 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits::cpu1.inst 135626 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 135626 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 6576761661 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6576761661 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.027615 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027615 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_misses::cpu1.inst 331682 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 331682 # number of demand (read+write) MSHR misses +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.overall_accesses::cpu1.inst 12010728 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 12010728 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 26483.357676 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 26483.357676 # average overall miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 19828.515449 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19828.515449 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_hits::cpu1.inst 11543420 # number of overall hits +system.cpu1.dcache.overall_hits::total 11543420 # number of overall hits +system.cpu1.dcache.overall_miss_latency::cpu1.inst 12375884909 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 12375884909 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.038908 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.038908 # miss rate for overall accesses +system.cpu1.dcache.overall_misses::cpu1.inst 467308 # number of overall misses +system.cpu1.dcache.overall_misses::total 467308 # number of overall misses +system.cpu1.dcache.overall_mshr_hits::cpu1.inst 135626 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 135626 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 6576761661 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6576761661 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.027615 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027615 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_misses::cpu1.inst 331682 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 331682 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 36664097359 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 36664097359 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu1.dcache.tags.avg_refs 38.928946 # Average number of references to valid blocks. +system.cpu1.dcache.tags.data_accesses 49080911 # Number of data accesses +system.cpu1.dcache.tags.occ_blocks::cpu1.inst 448.678844 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.876326 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.876326 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.replacements 300905 # number of replacements +system.cpu1.dcache.tags.sampled_refs 301417 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.tag_accesses 49080911 # Number of tag accesses +system.cpu1.dcache.tags.tagsinuse 448.678844 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 11733846 # Total number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 76695286250 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks::writebacks 270884 # number of writebacks +system.cpu1.dcache.writebacks::total 270884 # number of writebacks +system.cpu1.discardedOps 1803588 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.dtb.accesses 13158810 # DTB accesses +system.cpu1.dtb.align_faults 2430 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dtb.flush_entries 1717 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.hits 13135953 # DTB hits +system.cpu1.dtb.inst_accesses 0 # ITB inst accesses +system.cpu1.dtb.inst_hits 0 # ITB inst hits +system.cpu1.dtb.inst_misses 0 # ITB inst misses +system.cpu1.dtb.misses 22857 # DTB misses +system.cpu1.dtb.perms_faults 233 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.prefetch_faults 234 # Number of TLB faults due to prefetch +system.cpu1.dtb.read_accesses 7605254 # DTB read accesses +system.cpu1.dtb.read_hits 7584952 # DTB read hits +system.cpu1.dtb.read_misses 20302 # DTB read misses +system.cpu1.dtb.write_accesses 5553556 # DTB write accesses +system.cpu1.dtb.write_hits 5551001 # DTB write hits +system.cpu1.dtb.write_misses 2555 # DTB write misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 11366597 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 11366597 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13387.195767 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13387.195767 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11384.787952 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11384.787952 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_hits::cpu1.inst 10566141 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 10566141 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10715861175 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 10715861175 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.070422 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.070422 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses::cpu1.inst 800456 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 800456 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 9113021825 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 9113021825 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.070422 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.070422 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 800456 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 800456 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5643750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5643750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.demand_accesses::cpu1.inst 11366597 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 11366597 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13387.195767 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13387.195767 # average overall miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11384.787952 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11384.787952 # average overall mshr miss latency +system.cpu1.icache.demand_hits::cpu1.inst 10566141 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 10566141 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency::cpu1.inst 10715861175 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 10715861175 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.070422 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.070422 # miss rate for demand accesses +system.cpu1.icache.demand_misses::cpu1.inst 800456 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 800456 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 9113021825 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 9113021825 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.070422 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.070422 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 800456 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 800456 # number of demand (read+write) MSHR misses +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.overall_accesses::cpu1.inst 11366597 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 11366597 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13387.195767 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13387.195767 # average overall miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11384.787952 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11384.787952 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.icache.overall_hits::cpu1.inst 10566141 # number of overall hits +system.cpu1.icache.overall_hits::total 10566141 # number of overall hits +system.cpu1.icache.overall_miss_latency::cpu1.inst 10715861175 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 10715861175 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.070422 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.070422 # miss rate for overall accesses +system.cpu1.icache.overall_misses::cpu1.inst 800456 # number of overall misses +system.cpu1.icache.overall_misses::total 800456 # number of overall misses +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 9113021825 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 9113021825 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.070422 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.070422 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 800456 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 800456 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5643750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 5643750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 194 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id +system.cpu1.icache.tags.avg_refs 13.200169 # Average number of references to valid blocks. +system.cpu1.icache.tags.data_accesses 12167052 # Number of data accesses +system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.617049 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938705 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.938705 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.replacements 799943 # number of replacements +system.cpu1.icache.tags.sampled_refs 800455 # Sample count of references to valid blocks. +system.cpu1.icache.tags.tag_accesses 12167052 # Number of tag accesses +system.cpu1.icache.tags.tagsinuse 480.617049 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 10566141 # Total number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 82057257250 # Cycle when the warmup percentage was hit. +system.cpu1.idleCycles 29483115 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.ipc 0.213717 # IPC: instructions per cycle +system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.itb.accesses 11372965 # DTB accesses +system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.itb.flush_entries 1189 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.hits 11368674 # DTB hits +system.cpu1.itb.inst_accesses 11372965 # ITB inst accesses +system.cpu1.itb.inst_hits 11368674 # ITB inst hits +system.cpu1.itb.inst_misses 4291 # ITB inst misses +system.cpu1.itb.misses 4291 # DTB misses +system.cpu1.itb.perms_faults 1912 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.itb.read_accesses 0 # DTB read accesses +system.cpu1.itb.read_hits 0 # DTB read hits +system.cpu1.itb.read_misses 0 # DTB read misses +system.cpu1.itb.write_accesses 0 # DTB write accesses +system.cpu1.itb.write_hits 0 # DTB write hits +system.cpu1.itb.write_misses 0 # DTB write misses +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 40529 # number of quiesce instructions executed +system.cpu1.numCycles 149616439 # number of cpu cycles simulated +system.cpu1.numFetchSuspends 40001 # Number of times Execute suspended instruction fetching +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.quiesceCycles 2144894120 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.tickCycles 120133324 # Number of cycles that the CPU actually ticked +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.iobus.data_through_bus 52721660 # Total data (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30566 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8050 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 732 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 498 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382664 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12582912 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 12582912 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 14965576 # Packet count per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 21429000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 4031000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 6291456000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 372000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 299000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2374698000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) +system.iobus.respLayer1.occupancy 15868889251 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) +system.iobus.throughput 45973431 # Throughput (bytes/s) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40335 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16100 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1464 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 273 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390012 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 50331648 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 50331648 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 52721660 # Cumulative packet size per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 7474822 # Transaction distribution +system.iobus.trans_dist::ReadResp 7474822 # Transaction distribution +system.iobus.trans_dist::WriteReq 7966 # Transaction distribution +system.iobus.trans_dist::WriteResp 7966 # Transaction distribution +system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency +system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 722546651251 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 722546651251 # number of ReadReq MSHR uncacheable cycles +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 722546651251 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 722546651251 # number of overall MSHR uncacheable cycles +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.data_accesses 0 # Number of data accesses +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.tag_accesses 0 # Number of tag accesses +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.ReadExReq_accesses::cpu0.inst 151088 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.inst 98363 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 249451 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 68340.802831 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 70836.135654 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 69186.818320 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 55784.041664 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 58278.521386 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 56629.767918 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits::cpu0.inst 58609 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.inst 50926 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 109535 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency::cpu0.inst 6320089105 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.inst 3360253767 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9680342872 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::cpu0.inst 0.612087 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.inst 0.482265 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.560896 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::cpu0.inst 92479 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.inst 47437 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 139916 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 5158852389 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 2764558219 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7923410608 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.612087 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.482265 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.560896 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses::cpu0.inst 92479 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.inst 47437 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 139916 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 28623 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 6686 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 972984 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 26977 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 5385 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 980230 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2020885 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 75197.368421 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70701.604050 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 88575 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75547.349058 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 72536.539775 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 62802.631579 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58187.997185 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76175 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 63048.000202 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 60029.934536 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_hits::cpu0.dtb.walker 28604 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 6684 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 956588 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 26967 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5385 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 970309 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1994537 # number of ReadReq hits +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1428750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 1159223500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 885750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 749505250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1911192750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000664 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000299 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.016851 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000371 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010121 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.013038 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::cpu0.dtb.walker 19 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 16396 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 10 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 9921 # number of ReadReq misses +system.l2c.ReadReq_misses::total 26348 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits::cpu0.inst 54 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 20 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1193250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 950908250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 761750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 624238250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1577226500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000664 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000299 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016796 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000371 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010101 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.013001 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 19 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 16342 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 10 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 9901 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 26274 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 156403460492 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10977229000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167380689492 # number of ReadReq MSHR uncacheable cycles +system.l2c.SCUpgradeReq_accesses::cpu0.inst 889 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.inst 428 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1317 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 821.973412 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 6364.211838 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 2604.597194 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10035.706056 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10002.557632 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10025.044088 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_hits::cpu0.inst 212 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.inst 107 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 319 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 556476 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 2042912 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 2599388 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.761530 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.750000 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.757783 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_misses::cpu0.inst 677 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.inst 321 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 998 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 6794173 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 3210821 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 10004994 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.761530 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.750000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.757783 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 677 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 321 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 998 # number of SCUpgradeReq MSHR misses +system.l2c.UpgradeReq_accesses::cpu0.inst 5825 # number of UpgradeReq accesses(hits+misses) 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+system.l2c.UpgradeReq_miss_latency::cpu0.inst 7940154 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.inst 13889404 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 21829558 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.835536 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.801659 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.819586 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::cpu0.inst 4867 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.inst 4155 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 9022 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 48797337 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 41573649 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 90370986 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.835536 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.801659 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.819586 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_misses::cpu0.inst 4867 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.inst 4155 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 9022 # number of UpgradeReq MSHR misses +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 1364457493 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 15414956890 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 16779414383 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::writebacks 577052 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 577052 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::writebacks 577052 # number of Writeback hits +system.l2c.Writeback_hits::total 577052 # number of Writeback hits +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.demand_accesses::cpu0.dtb.walker 28623 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 6686 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 1124072 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 26977 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 5385 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 1078593 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2270336 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 75197.368421 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 68696.327026 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88575 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 71651.016720 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 69717.651578 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62802.631579 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56145.051406 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76175 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59102.104521 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 57167.321187 # average overall mshr miss latency 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of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 57358 # number of demand (read+write) misses +system.l2c.demand_misses::total 166264 # number of demand (read+write) misses +system.l2c.demand_mshr_hits::cpu0.inst 54 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 20 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1193250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 6109760639 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 761750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 3388796469 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 9500637108 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000664 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000299 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.096810 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000371 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.053160 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.073201 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 19 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 108821 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 10 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 57338 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 166190 # number of demand (read+write) MSHR misses +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.overall_accesses::cpu0.dtb.walker 28623 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 6686 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 1124072 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 26977 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 5385 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 1078593 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2270336 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 75197.368421 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 68696.327026 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88575 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 71651.016720 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 69717.651578 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62802.631579 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56145.051406 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76175 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59102.104521 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57167.321187 # average overall mshr miss latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.overall_hits::cpu0.dtb.walker 28604 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 6684 # number of overall hits +system.l2c.overall_hits::cpu0.inst 1015197 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 26967 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5385 # number of overall hits +system.l2c.overall_hits::cpu1.inst 1021235 # number of overall hits +system.l2c.overall_hits::total 2104072 # number of overall hits +system.l2c.overall_miss_latency::cpu0.dtb.walker 1428750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 149500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 7479312605 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 885750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 4109759017 # number of overall miss cycles +system.l2c.overall_miss_latency::total 11591535622 # number of overall miss cycles +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000664 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000299 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.096858 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000371 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.053179 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.073233 # miss rate for overall accesses +system.l2c.overall_misses::cpu0.dtb.walker 19 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses +system.l2c.overall_misses::cpu0.inst 108875 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 10 # number of overall misses +system.l2c.overall_misses::cpu1.inst 57358 # number of overall misses +system.l2c.overall_misses::total 166264 # number of overall misses +system.l2c.overall_mshr_hits::cpu0.inst 54 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 20 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 74 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1193250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 6109760639 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 761750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 3388796469 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 9500637108 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000664 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000299 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.096810 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000371 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.053160 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.073201 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 19 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 108821 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 10 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 57338 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 166190 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 157767917985 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 26392185890 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 184160103875 # number of overall MSHR uncacheable cycles +system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2318 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 8665 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54076 # Occupied blocks per task id +system.l2c.tags.avg_refs 17.496486 # Average number of references to valid blocks. +system.l2c.tags.data_accesses 23293968 # Number of data accesses +system.l2c.tags.occ_blocks::writebacks 38836.595678 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 12.172943 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001299 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 8927.165185 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.671671 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 6116.054658 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.592599 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000186 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.136218 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000132 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.093324 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.822459 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000122 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id +system.l2c.tags.replacements 73691 # number of replacements +system.l2c.tags.sampled_refs 138862 # Sample count of references to valid blocks. +system.l2c.tags.tag_accesses 23293968 # Number of tag accesses +system.l2c.tags.tagsinuse 53900.661434 # Cycle average of tags in use +system.l2c.tags.total_refs 2429597 # Total number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.writebacks::writebacks 67203 # number of writebacks +system.l2c.writebacks::total 67203 # number of writebacks +system.membus.data_through_bus 70713692 # Total data (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382664 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11296 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 874 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1977013 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4371873 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12582912 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 12582912 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 16954785 # Packet count per connected master and slave (bytes) +system.membus.reqLayer0.occupancy 1725804499 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.reqLayer1.occupancy 16500 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 10159500 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) +system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 707500 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer6.occupancy 8809576499 # Layer occupancy (ticks) +system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 4910157489 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.respLayer2.occupancy 15563933749 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.4 # Layer utilization (%) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.throughput 61662532 # Throughput (bytes/s) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390012 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 22592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1748 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17966980 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 20382044 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 50331648 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 50331648 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 70713692 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 7506677 # Transaction distribution +system.membus.trans_dist::ReadResp 7506677 # Transaction distribution +system.membus.trans_dist::WriteReq 767829 # Transaction distribution +system.membus.trans_dist::WriteResp 767829 # Transaction distribution +system.membus.trans_dist::Writeback 67203 # Transaction distribution +system.membus.trans_dist::UpgradeReq 33449 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 17313 # Transaction distribution +system.membus.trans_dist::UpgradeResp 12389 # Transaction distribution +system.membus.trans_dist::ReadExReq 137872 # Transaction distribution +system.membus.trans_dist::ReadExResp 137547 # Transaction distribution +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgGap 157485.55 # Average gap between requests +system.physmem.avgMemAccLat 44404.73 # Average memory access latency per DRAM burst +system.physmem.avgQLat 25654.73 # Average queueing delay per DRAM burst +system.physmem.avgRdBW 360.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgRdBWSys 53.17 # Average system read bandwidth in MiByte/s +system.physmem.avgRdQLen 4.16 # Average read queue length when enqueuing +system.physmem.avgWrBW 6.40 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBWSys 6.39 # Average system write bandwidth in MiByte/s +system.physmem.avgWrQLen 23.53 # Average write queue length when enqueuing +system.physmem.busUtil 2.87 # Data bus utilization in percentage +system.physmem.busUtilRead 2.82 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes +system.physmem.bw_inst_read::cpu0.inst 666071 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 241370 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 907441 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.clcd 43889334 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 1060 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 112 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 6125781 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 558 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 3149416 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53166261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3750477 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43889334 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1060 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 112 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 6140605 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 558 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 5774444 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 59556590 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 3750477 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.inst 14824 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.inst 2625028 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6390329 # Write bandwidth from this memory (bytes/s) +system.physmem.bytesPerActivate::samples 461405 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 911.601183 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 779.379075 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 292.108282 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24920 5.40% 5.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 21689 4.70% 10.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5921 1.28% 11.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2595 0.56% 11.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2392 0.52% 12.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1620 0.35% 12.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3961 0.86% 13.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 945 0.20% 13.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 397362 86.12% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 461405 # Bytes accessed per row activation +system.physmem.bytesReadDRAM 413277056 # Total number of bytes read from DRAM +system.physmem.bytesReadSys 60970292 # Total read bytes from the system interface side +system.physmem.bytesReadWrQ 21312 # Total number of bytes read from write queue +system.physmem.bytesWritten 7340288 # Total number of bytes written to DRAM +system.physmem.bytesWrittenSys 7328336 # Total written bytes from the system interface side +system.physmem.bytes_inst_read::cpu0.inst 763840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 276800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1040640 # Number of instructions bytes read from this memory +system.physmem.bytes_read::realview.clcd 50331648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 7024956 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3611704 # Number of bytes read from this memory +system.physmem.bytes_read::total 60970292 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 4300992 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.inst 17000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.inst 3010344 # Number of bytes written to this memory +system.physmem.bytes_written::total 7328336 # Number of bytes written to this memory +system.physmem.memoryStateTime::IDLE 907580229250 # Time in different power states +system.physmem.memoryStateTime::REF 38293580000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 200908709500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.mergedWrBursts 709322 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 12389 # Number of requests that are neither read nor write +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.num_reads::realview.clcd 6291456 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 19 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 109839 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 56461 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6457787 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 67203 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.inst 4250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.inst 752586 # Number of write requests responded to by this memory +system.physmem.num_writes::total 824039 # Number of write requests responded to by this memory +system.physmem.pageHitRate 92.98 # Row buffer hit rate, read and write combined +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.perBankRdBursts::0 403322 # Per bank write bursts +system.physmem.perBankRdBursts::1 403674 # Per bank write bursts +system.physmem.perBankRdBursts::2 403179 # Per bank write bursts +system.physmem.perBankRdBursts::3 403456 # Per bank write bursts +system.physmem.perBankRdBursts::4 406212 # Per bank write bursts +system.physmem.perBankRdBursts::5 403697 # Per bank write bursts +system.physmem.perBankRdBursts::6 403585 # Per bank write bursts +system.physmem.perBankRdBursts::7 403309 # Per bank write bursts +system.physmem.perBankRdBursts::8 403688 # Per bank write bursts +system.physmem.perBankRdBursts::9 404195 # Per bank write bursts +system.physmem.perBankRdBursts::10 403096 # Per bank write bursts +system.physmem.perBankRdBursts::11 402549 # Per bank write bursts +system.physmem.perBankRdBursts::12 403605 # Per bank write bursts +system.physmem.perBankRdBursts::13 403586 # Per bank write bursts +system.physmem.perBankRdBursts::14 403320 # Per bank write bursts +system.physmem.perBankRdBursts::15 402981 # Per bank write bursts +system.physmem.perBankWrBursts::0 7004 # Per bank write bursts +system.physmem.perBankWrBursts::1 7414 # Per bank write bursts +system.physmem.perBankWrBursts::2 6962 # Per bank write bursts +system.physmem.perBankWrBursts::3 7076 # Per bank write bursts +system.physmem.perBankWrBursts::4 7614 # Per bank write bursts +system.physmem.perBankWrBursts::5 7289 # Per bank write bursts +system.physmem.perBankWrBursts::6 7332 # Per bank write bursts +system.physmem.perBankWrBursts::7 7122 # Per bank write bursts +system.physmem.perBankWrBursts::8 7331 # Per bank write bursts +system.physmem.perBankWrBursts::9 7785 # Per bank write bursts +system.physmem.perBankWrBursts::10 6895 # Per bank write bursts +system.physmem.perBankWrBursts::11 6483 # Per bank write bursts +system.physmem.perBankWrBursts::12 7357 # Per bank write bursts +system.physmem.perBankWrBursts::13 7159 # Per bank write bursts +system.physmem.perBankWrBursts::14 7082 # Per bank write bursts +system.physmem.perBankWrBursts::15 6787 # Per bank write bursts +system.physmem.rdPerTurnAround::samples 6667 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 968.567572 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 25247.895153 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-65535 6659 99.88% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-262143 4 0.06% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::589824-655359 1 0.01% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::786432-851967 2 0.03% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.50733e+06-1.57286e+06 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6667 # Reads before turning the bus around for writes +system.physmem.rdQLenPdf::0 559033 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 398819 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 399992 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 446086 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 404802 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 432883 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1116979 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1080646 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1404200 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 57088 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 46892 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 43646 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 42022 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8400 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 7955 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 7847 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 159 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.readBursts 6457787 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 109 # Read request sizes (log2) +system.physmem.readPktSize::3 6291456 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 166222 # Read request sizes (log2) +system.physmem.readReqs 6457787 # Number of read requests accepted +system.physmem.readRowHitRate 93.17 # Row buffer hit rate for reads +system.physmem.readRowHits 6016258 # Number of row buffer hits during reads +system.physmem.servicedByWrQ 333 # Number of DRAM read bursts serviced by the write queue +system.physmem.totBusLat 32287270000 # Total ticks spent in databus transfers +system.physmem.totGap 1146782404500 # Total gap between requests +system.physmem.totMemAccLat 286741508250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 165664245750 # Total ticks spent queuing +system.physmem.wrPerTurnAround::samples 6667 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.202940 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.174263 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.985830 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2664 39.96% 39.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 13 0.19% 40.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3969 59.53% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 17 0.25% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 3 0.04% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6667 # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3989 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4002 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.writeBursts 824039 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 756836 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 67203 # Write request sizes (log2) +system.physmem.writeReqs 824039 # Number of write requests accepted +system.physmem.writeRowHitRate 82.36 # Row buffer hit rate for writes +system.physmem.writeRowHits 94483 # Number of row buffer hits during writes +system.realview.nvmem.bw_inst_read::cpu0.inst 223 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 391 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 614 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu0.inst 223 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 391 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 614 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 223 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 391 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 614 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_inst_read::cpu0.inst 256 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_read::cpu0.inst 256 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 704 # Number of bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 4 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory +system.toL2Bus.data_through_bus 183769016 # Total data (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1573579 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3284792 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 16388 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 66250 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1600218 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2575101 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 13938 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 63483 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 9193749 # Packet count per connected master and slave (bytes) +system.toL2Bus.reqLayer0.occupancy 5169689504 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 3544874662 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 2799461047 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 9704495 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 37627749 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 3603369425 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 1938898298 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer8.occupancy 8556493 # Layer occupancy (ticks) +system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer9.occupancy 36509744 # Layer occupancy (ticks) +system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) +system.toL2Bus.snoop_data_through_bus 4881844 # Total snoop data (bytes) +system.toL2Bus.throughput 164504065 # Throughput (bytes/s) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 50330560 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 43616868 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26744 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 114492 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 51179904 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 38371000 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 21540 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 107908 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 183769016 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.trans_dist::ReadReq 3298101 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 3298100 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 767829 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 767829 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 577052 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 33066 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 17632 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 50698 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 260633 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 260633 # Transaction distribution +system.voltage_domain.voltage 1 # Voltage in Volts + +---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/system.terminal Binary files differnew file mode 100644 index 000000000..04e1f4d41 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/system.terminal diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini new file mode 100644 index 000000000..f89afb299 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini @@ -0,0 +1,1390 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=true +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=LinuxArmSystem +children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain +atags_addr=256 +boot_loader=/arm/projectscratch/pd/sysrandd/dist/binaries/boot.arm +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_release_addr=65528 +cache_line_size=64 +clk_domain=system.clk_domain +dtb_filename= +early_kernel_symbols=false +enable_context_switch_stats_dump=false +eventq_index=0 +flags_addr=268435504 +gic_cpu_addr=520093952 +have_generic_timer=false +have_large_asid_64=false +have_lpae=false +have_security=false +have_virtualization=false +highest_el_is_64=false +init_param=0 +kernel=/arm/projectscratch/pd/sysrandd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +load_addr_mask=268435455 +load_offset=0 +machine_type=RealView_PBX +mem_mode=timing +mem_ranges=0:134217727 +memories=system.physmem system.realview.nvmem +multi_proc=true +num_work_ids=16 +panic_on_oops=true +panic_on_panic=true +phys_addr_range_64=40 +readfile=tests/halt.sh +reset_addr_64=0 +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.bridge] +type=Bridge +clk_domain=system.clk_domain +delay=50000 +eventq_index=0 +ranges=268435456:520093695 1073741824:1610612735 +req_size=16 +resp_size=16 +master=system.iobus.slave[0] +slave=system.membus.master[0] + +[system.cf0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +eventq_index=0 +image=system.cf0.image + +[system.cf0.image] +type=CowDiskImage +children=child +child=system.cf0.image.child +eventq_index=0 +image_file= +read_only=false +table_size=65536 + +[system.cf0.image.child] +type=RawDiskImage +eventq_index=0 +image_file=/arm/projectscratch/pd/sysrandd/dist/disks/linux-arm-ael.img +read_only=true + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +switched_out=false +system=system +tracer=system.cpu.tracer +workload= +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + +[system.cpu.dcache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=4 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=4 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[5] + +[system.cpu.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[3] + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits2.timings + +[system.cpu.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=9 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] +type=MinorOpClass +eventq_index=0 +opClass=FloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] +type=MinorOpClass +eventq_index=0 +opClass=FloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] +type=MinorOpClass +eventq_index=0 +opClass=FloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] +type=MinorOpClass +eventq_index=0 +opClass=FloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] +type=MinorOpClass +eventq_index=0 +opClass=FloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] +type=MinorOpClass +eventq_index=0 +opClass=FloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] +type=MinorOpClass +eventq_index=0 +opClass=SimdAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] +type=MinorOpClass +eventq_index=0 +opClass=SimdAddAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] +type=MinorOpClass +eventq_index=0 +opClass=SimdAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] +type=MinorOpClass +eventq_index=0 +opClass=SimdCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] +type=MinorOpClass +eventq_index=0 +opClass=SimdCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] +type=MinorOpClass +eventq_index=0 +opClass=SimdShift + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] +type=MinorOpClass +eventq_index=0 +opClass=SimdShiftAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] +type=MinorOpClass +eventq_index=0 +opClass=SimdSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.timings] +type=MinorFUTiming +children=opClasses +description=FloatSimd +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits5] +type=MinorFU +children=opClasses timings +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses +opLat=1 +timings=system.cpu.executeFuncUnits.funcUnits5.timings + +[system.cpu.executeFuncUnits.funcUnits5.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=MemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=MemWrite + +[system.cpu.executeFuncUnits.funcUnits5.timings] +type=MinorFUTiming +children=opClasses +description=Mem +eventq_index=0 +extraAssumedLat=2 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses +srcRegsRelativeLats=1 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits6] +type=MinorFU +children=opClasses +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses +opLat=1 +timings= + +[system.cpu.executeFuncUnits.funcUnits6.opClasses] +type=MinorOpClassSet +children=opClasses0 opClasses1 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] +type=MinorOpClass +eventq_index=0 +opClass=IprAccess + +[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] +type=MinorOpClass +eventq_index=0 +opClass=InstPrefetch + +[system.cpu.icache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=1 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=32768 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=1 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=32768 + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[4] + +[system.cpu.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +clk_domain=system.cpu_clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system +port=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=4194304 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=4194304 + +[system.cpu.toL2Bus] +type=CoherentBus +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +eventq_index=0 +voltage_domain=system.voltage_domain + +[system.intrctrl] +type=IntrControl +eventq_index=0 +sys=system + +[system.iobus] +type=NoncoherentBus +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +use_default_range=false +width=8 +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side +slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma + +[system.iocache] +type=BaseCache +children=tags +addr_ranges=0:134217727 +assoc=8 +clk_domain=system.clk_domain +eventq_index=0 +forward_snoops=false +hit_latency=50 +is_top_level=true +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=50 +sequential_access=false +size=1024 +system=system +tags=system.iocache.tags +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.iobus.master[25] +mem_side=system.membus.slave[2] + +[system.iocache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=50 +sequential_access=false +size=1024 + +[system.membus] +type=CoherentBus +children=badaddr_responder +clk_domain=system.clk_domain +eventq_index=0 +header_cycles=1 +system=system +use_default_range=false +width=8 +default=system.membus.badaddr_responder.pio +master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side + +[system.membus.badaddr_responder] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=0 +pio_latency=100000 +pio_size=8 +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access=warn +pio=system.membus.default + +[system.physmem] +type=DRAMCtrl +activation_limit=4 +addr_mapping=RoRaBaChCo +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +devices_per_rank=8 +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCL=13750 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=300000 +tRP=13750 +tRRD=6250 +tWTR=7500 +tXAW=40000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[6] + +[system.realview] +type=RealView +children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 +intrctrl=system.intrctrl +max_mem_size=268435456 +mem_start_addr=0 +pci_cfg_base=0 +system=system + +[system.realview.a9scu] +type=A9SCU +clk_domain=system.clk_domain +eventq_index=0 +pio_addr=520093696 +pio_latency=100000 +system=system +pio=system.membus.master[4] + +[system.realview.aaci_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=268451840 +pio_latency=100000 +system=system +pio=system.iobus.master[21] + +[system.realview.cf_ctrl] +type=IdeController +BAR0=402653184 +BAR0LegacyIO=true +BAR0Size=16 +BAR1=402653440 +BAR1LegacyIO=true +BAR1Size=1 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CapabilityPtr=0 +CardbusCIS=0 +ClassCode=1 +Command=1 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=31 +InterruptPin=1 +LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 +MaximumLatency=0 +MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clk_domain=system.clk_domain +config_latency=20000 +ctrl_offset=2 +disks=system.cf0 +eventq_index=0 +io_shift=1 +pci_bus=2 +pci_dev=7 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[8] +dma=system.iobus.slave[2] +pio=system.iobus.master[7] + +[system.realview.clcd] +type=Pl111 +amba_id=1315089 +clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 +gic=system.realview.gic +int_num=55 +pio_addr=268566528 +pio_latency=10000 +pixel_clock=41667 +system=system +vnc=system.vncserver +dma=system.iobus.slave[1] +pio=system.iobus.master[4] + +[system.realview.dmac_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=268632064 +pio_latency=100000 +system=system +pio=system.iobus.master[9] + +[system.realview.flash_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=true +pio_addr=1073741824 +pio_latency=100000 +pio_size=536870912 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[24] + +[system.realview.gic] +type=Pl390 +clk_domain=system.clk_domain +cpu_addr=520093952 +cpu_pio_delay=10000 +dist_addr=520097792 +dist_pio_delay=10000 +eventq_index=0 +int_latency=10000 +it_lines=128 +msix_addr=0 +platform=system.realview +system=system +pio=system.membus.master[2] + +[system.realview.gpio0_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=268513280 +pio_latency=100000 +system=system +pio=system.iobus.master[16] + +[system.realview.gpio1_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=268517376 +pio_latency=100000 +system=system +pio=system.iobus.master[17] + +[system.realview.gpio2_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=268521472 +pio_latency=100000 +system=system +pio=system.iobus.master[18] + +[system.realview.kmi0] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=52 +is_mouse=false +pio_addr=268460032 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[5] + +[system.realview.kmi1] +type=Pl050 +amba_id=1314896 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=1000000 +int_num=53 +is_mouse=true +pio_addr=268464128 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[6] + +[system.realview.l2x0_fake] +type=IsaFake +clk_domain=system.clk_domain +eventq_index=0 +fake_mem=false +pio_addr=520101888 +pio_latency=100000 +pio_size=4095 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.membus.master[3] + +[system.realview.local_cpu_timer] +type=CpuLocalTimer +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_num_timer=29 +int_num_watchdog=30 +pio_addr=520095232 +pio_latency=100000 +system=system +pio=system.membus.master[5] + +[system.realview.mmc_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=268455936 +pio_latency=100000 +system=system +pio=system.iobus.master[22] + +[system.realview.nvmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=false +eventq_index=0 +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=2147483648:2214592511 +port=system.membus.master[1] + +[system.realview.realview_io] +type=RealViewCtrl +clk_domain=system.clk_domain +eventq_index=0 +idreg=0 +pio_addr=268435456 +pio_latency=100000 +proc_id0=201326592 +proc_id1=201327138 +system=system +pio=system.iobus.master[1] + +[system.realview.rtc] +type=PL031 +amba_id=3412017 +clk_domain=system.clk_domain +eventq_index=0 +gic=system.realview.gic +int_delay=100000 +int_num=42 +pio_addr=268529664 +pio_latency=100000 +system=system +time=Thu Jan 1 00:00:00 2009 +pio=system.iobus.master[23] + +[system.realview.sci_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=268492800 +pio_latency=100000 +system=system +pio=system.iobus.master[20] + +[system.realview.smc_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=269357056 +pio_latency=100000 +system=system +pio=system.iobus.master[13] + +[system.realview.sp810_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=true +pio_addr=268439552 +pio_latency=100000 +system=system +pio=system.iobus.master[14] + +[system.realview.ssp_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=268488704 +pio_latency=100000 +system=system +pio=system.iobus.master[19] + +[system.realview.timer0] +type=Sp804 +amba_id=1316868 +clk_domain=system.clk_domain +clock0=1000000 +clock1=1000000 +eventq_index=0 +gic=system.realview.gic +int_num0=36 +int_num1=36 +pio_addr=268505088 +pio_latency=100000 +system=system +pio=system.iobus.master[2] + +[system.realview.timer1] +type=Sp804 +amba_id=1316868 +clk_domain=system.clk_domain +clock0=1000000 +clock1=1000000 +eventq_index=0 +gic=system.realview.gic +int_num0=37 +int_num1=37 +pio_addr=268509184 +pio_latency=100000 +system=system +pio=system.iobus.master[3] + +[system.realview.uart] +type=Pl011 +clk_domain=system.clk_domain +end_on_eot=false +eventq_index=0 +gic=system.realview.gic +int_delay=100000 +int_num=44 +pio_addr=268472320 +pio_latency=100000 +platform=system.realview +system=system +terminal=system.terminal +pio=system.iobus.master[0] + +[system.realview.uart1_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=268476416 +pio_latency=100000 +system=system +pio=system.iobus.master[10] + +[system.realview.uart2_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=268480512 +pio_latency=100000 +system=system +pio=system.iobus.master[11] + +[system.realview.uart3_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=268484608 +pio_latency=100000 +system=system +pio=system.iobus.master[12] + +[system.realview.watchdog_fake] +type=AmbaFake +amba_id=0 +clk_domain=system.clk_domain +eventq_index=0 +ignore_access=false +pio_addr=268500992 +pio_latency=100000 +system=system +pio=system.iobus.master[15] + +[system.terminal] +type=Terminal +eventq_index=0 +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.vncserver] +type=VncServer +eventq_index=0 +frame_capture=false +number=0 +port=5900 + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simerr new file mode 100644 index 000000000..9dee17aa2 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simerr @@ -0,0 +1,13 @@ +warn: Sockets disabled, not accepting vnc client connections +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections +warn: The clidr register always reports 0 caches. +warn: clidr LoUIS field of 0b001 to match current ARM implementations. +warn: The csselr register isn't implemented. +warn: The ccsidr register isn't implemented and always reads as 0. +warn: instruction 'mcr bpiallis' unimplemented +warn: instruction 'mcr icialluis' unimplemented +warn: instruction 'mcr dccimvac' unimplemented +warn: instruction 'mcr dccmvau' unimplemented +warn: instruction 'mcr icimvau' unimplemented +warn: LCD dual screen mode not supported diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout new file mode 100644 index 000000000..7e5f71538 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout @@ -0,0 +1,16 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled May 7 2014 10:57:46 +gem5 started May 7 2014 17:07:27 +gem5 executing on cz3211bhr8 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor +Global frequency set at 1000000000000 ticks per second +info: kernel located at: /arm/projectscratch/pd/sysrandd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 + 0: system.cpu.isa: ISA system set to: 0x1a1f0030 0x1a1f0030 +info: Using bootloader at address 0x80000000 +info: Using kernel entry physical address at 0x8000 +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 2567809308500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt new file mode 100644 index 000000000..cd537ca0c --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -0,0 +1,1074 @@ + +---------- Begin Simulation Statistics ---------- +final_tick 2567690995500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +host_inst_rate 83247 # Simulator instruction rate (inst/s) +host_mem_usage 453632 # Number of bytes of host memory used +host_op_rate 107007 # Simulator op (including micro ops) rate (op/s) +host_seconds 727.87 # Real time elapsed on the host +host_tick_rate 3527658330 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 60593069 # Number of instructions simulated +sim_ops 77887632 # Number of ops (including micro ops) simulated +sim_seconds 2.567691 # Number of seconds simulated +sim_ticks 2567690995500 # Number of ticks simulated +system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. +system.cf0.dma_write_txs 0 # Number of DMA write transactions. +system.clk_domain.clock 1000 # Clock period in ticks +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 71.037327 # BTB Hit Percentage +system.cpu.branchPred.BTBHits 6285951 # Number of BTB hits +system.cpu.branchPred.BTBLookups 8848800 # Number of BTB lookups +system.cpu.branchPred.RASInCorrect 141766 # Number of incorrect RAS predictions. +system.cpu.branchPred.condIncorrect 1083327 # Number of conditional branches incorrect +system.cpu.branchPred.condPredicted 9899581 # Number of conditional branches predicted +system.cpu.branchPred.lookups 12901223 # Number of BP lookups +system.cpu.branchPred.usedRAS 1514142 # Number of times the RAS was used to get a target. +system.cpu.committedInsts 60593069 # Number of instructions committed +system.cpu.committedOps 77887632 # Number of ops (including micro ops) committed +system.cpu.cpi 9.521608 # CPI: cycles per instruction +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 247603 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 247603 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13892.781561 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13892.781561 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11890.018527 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11890.018527 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 236735 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236735 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 150986750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 150986750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.043893 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.043893 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::cpu.inst 10868 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 10868 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 73 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 73 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 128352750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 128352750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.043598 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.043598 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 10795 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 10795 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses::cpu.inst 13864450 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13864450 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 15150.498583 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15150.498583 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12786.142134 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12786.142134 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_hits::cpu.inst 13401466 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13401466 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7014438436 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7014438436 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.033394 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.033394 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::cpu.inst 462984 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 462984 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 82872 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 82872 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4860166059 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4860166059 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.027416 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027416 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 380112 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 380112 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 182581857500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182581857500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses::cpu.inst 247602 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247602 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::cpu.inst 247602 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247602 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses::cpu.inst 10222557 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222557 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 46293.122518 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 46293.122518 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 42586.604187 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42586.604187 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_hits::cpu.inst 9749254 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9749254 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 21910673767 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21910673767 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.046300 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.046300 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::cpu.inst 473303 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 473303 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 222786 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 222786 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10668668321 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10668668321 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.024506 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024506 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 250517 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250517 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 26058222680 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26058222680 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses::cpu.inst 24087007 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24087007 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 30893.424989 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30893.424989 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 24624.358188 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24624.358188 # average overall mshr miss latency +system.cpu.dcache.demand_hits::cpu.inst 23150720 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23150720 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency::cpu.inst 28925112203 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28925112203 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::cpu.inst 0.038871 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.038871 # miss rate for demand accesses +system.cpu.dcache.demand_misses::cpu.inst 936287 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 936287 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits::cpu.inst 305658 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 305658 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 15528834380 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15528834380 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.026181 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.026181 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses::cpu.inst 630629 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 630629 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.overall_accesses::cpu.inst 24087007 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24087007 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 30893.424989 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30893.424989 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 24624.358188 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24624.358188 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits::cpu.inst 23150720 # number of overall hits +system.cpu.dcache.overall_hits::total 23150720 # number of overall hits +system.cpu.dcache.overall_miss_latency::cpu.inst 28925112203 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28925112203 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::cpu.inst 0.038871 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.038871 # miss rate for overall accesses +system.cpu.dcache.overall_misses::cpu.inst 936287 # number of overall misses +system.cpu.dcache.overall_misses::total 936287 # number of overall misses +system.cpu.dcache.overall_mshr_hits::cpu.inst 305658 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 305658 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 15528834380 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15528834380 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.026181 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.026181 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses::cpu.inst 630629 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 630629 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 208640080180 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 208640080180 # number of overall MSHR uncacheable cycles +system.cpu.dcache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 341 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id +system.cpu.dcache.tags.avg_refs 37.024295 # Average number of references to valid blocks. +system.cpu.dcache.tags.data_accesses 98967296 # Number of data accesses +system.cpu.dcache.tags.occ_blocks::cpu.inst 511.959208 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.999920 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999920 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.replacements 637936 # number of replacements +system.cpu.dcache.tags.sampled_refs 638448 # Sample count of references to valid blocks. +system.cpu.dcache.tags.tag_accesses 98967296 # Number of tag accesses +system.cpu.dcache.tags.tagsinuse 511.959208 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 23638087 # Total number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 227414250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks::writebacks 603000 # number of writebacks +system.cpu.dcache.writebacks::total 603000 # number of writebacks +system.cpu.discardedOps 3607979 # Number of ops (including micro ops) which were discarded before commit +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dtb.accesses 26805017 # DTB accesses +system.cpu.dtb.align_faults 1584 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.flush_entries 3457 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.hits 26758984 # DTB hits +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.misses 46033 # DTB misses +system.cpu.dtb.perms_faults 524 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.prefetch_faults 266 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 15458164 # DTB read accesses +system.cpu.dtb.read_hits 15416095 # DTB read hits +system.cpu.dtb.read_misses 42069 # DTB read misses +system.cpu.dtb.write_accesses 11346853 # DTB write accesses +system.cpu.dtb.write_hits 11342889 # DTB write hits +system.cpu.dtb.write_misses 3964 # DTB write misses +system.cpu.icache.ReadReq_accesses::cpu.inst 23332180 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 23332180 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13520.944355 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13520.944355 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11517.182541 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11517.182541 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_hits::cpu.inst 21786211 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 21786211 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20902960824 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20902960824 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.066259 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.066259 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::cpu.inst 1545969 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1545969 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17805207176 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17805207176 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.066259 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.066259 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1545969 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1545969 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 172412750 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 172412750 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses::cpu.inst 23332180 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 23332180 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13520.944355 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13520.944355 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11517.182541 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11517.182541 # average overall mshr miss latency +system.cpu.icache.demand_hits::cpu.inst 21786211 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 21786211 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency::cpu.inst 20902960824 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20902960824 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::cpu.inst 0.066259 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.066259 # miss rate for demand accesses +system.cpu.icache.demand_misses::cpu.inst 1545969 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1545969 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17805207176 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17805207176 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.066259 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.066259 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses::cpu.inst 1545969 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1545969 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.overall_accesses::cpu.inst 23332180 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 23332180 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13520.944355 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13520.944355 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11517.182541 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11517.182541 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.icache.overall_hits::cpu.inst 21786211 # number of overall hits +system.cpu.icache.overall_hits::total 21786211 # number of overall hits +system.cpu.icache.overall_miss_latency::cpu.inst 20902960824 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20902960824 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::cpu.inst 0.066259 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.066259 # miss rate for overall accesses +system.cpu.icache.overall_misses::cpu.inst 1545969 # number of overall misses +system.cpu.icache.overall_misses::total 1545969 # number of overall misses +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17805207176 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17805207176 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.066259 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.066259 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses::cpu.inst 1545969 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1545969 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 172412750 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 172412750 # number of overall MSHR uncacheable cycles +system.cpu.icache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 210 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 181 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.icache.tags.avg_refs 14.092278 # Average number of references to valid blocks. +system.cpu.icache.tags.data_accesses 24878148 # Number of data accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 511.467492 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998960 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998960 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.replacements 1545456 # number of replacements +system.cpu.icache.tags.sampled_refs 1545968 # Sample count of references to valid blocks. +system.cpu.icache.tags.tag_accesses 24878148 # Number of tag accesses +system.cpu.icache.tags.tagsinuse 511.467492 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 21786211 # Total number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 10068892000 # Cycle when the warmup percentage was hit. +system.cpu.idleCycles 106196788 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.ipc 0.105024 # IPC: instructions per cycle +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.itb.accesses 23345804 # DTB accesses +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.flush_entries 2396 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.hits 23336489 # DTB hits +system.cpu.itb.inst_accesses 23345804 # ITB inst accesses +system.cpu.itb.inst_hits 23336489 # ITB inst hits +system.cpu.itb.inst_misses 9315 # ITB inst misses +system.cpu.itb.misses 9315 # DTB misses +system.cpu.itb.perms_faults 4052 # Number of TLB faults due to permissions restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 82977 # number of quiesce instructions executed +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 247542 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 247542 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69059.848663 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69059.848663 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56515.321009 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56515.321009 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits::cpu.inst 114197 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 114197 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 9208785520 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 9208785520 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.538676 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.538676 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 133345 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133345 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 7536035480 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7536035480 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.538676 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.538676 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 133345 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133345 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52818 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11330 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1934916 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1999064 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85107.142857 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 74750 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71955.193483 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71966.894361 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72773.809524 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59447.036018 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59458.945900 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52797 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11328 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 1910857 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1974982 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1787250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 149500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1731170000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1733106750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000398 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000177 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012434 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.012047 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 21 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 24059 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 24082 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 71 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1528250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1426015500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1427668750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000398 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000177 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012397 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.012011 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 21 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 23988 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 24011 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 167311975000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167311975000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.UpgradeReq_accesses::cpu.inst 2976 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2976 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst 126.265763 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 126.265763 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10004.558983 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10004.558983 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_hits::cpu.inst 26 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst 372484 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 372484 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst 0.991263 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991263 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_misses::cpu.inst 2950 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2950 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst 29513449 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29513449 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.991263 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991263 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst 2950 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2950 # number of UpgradeReq MSHR misses +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 16707831820 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16707831820 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.Writeback_accesses::writebacks 603000 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 603000 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits::writebacks 603000 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 603000 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52818 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 11330 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 2182458 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2246606 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85107.142857 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69502.398414 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69504.546679 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72773.809524 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56962.309115 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56964.489629 # average overall mshr miss latency +system.cpu.l2cache.demand_hits::cpu.dtb.walker 52797 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 11328 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 2025054 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2089179 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1787250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 149500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 10939955520 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10941892270 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000398 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000177 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.072122 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.070073 # miss rate for demand accesses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 21 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 157404 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 157427 # number of demand (read+write) misses +system.cpu.l2cache.demand_mshr_hits::cpu.inst 71 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1528250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8962050980 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8963704230 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000398 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000177 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.072090 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.070042 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 21 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 157333 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 157356 # number of demand (read+write) MSHR misses +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52818 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 11330 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 2182458 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2246606 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85107.142857 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69502.398414 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69504.546679 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72773.809524 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56962.309115 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56964.489629 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits::cpu.dtb.walker 52797 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 11328 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 2025054 # number of overall hits +system.cpu.l2cache.overall_hits::total 2089179 # number of overall hits +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1787250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 149500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 10939955520 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10941892270 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000398 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000177 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.072122 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.070073 # miss rate for overall accesses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 21 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 157404 # number of overall misses +system.cpu.l2cache.overall_misses::total 157427 # number of overall misses +system.cpu.l2cache.overall_mshr_hits::cpu.inst 71 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 71 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1528250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8962050980 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8963704230 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000398 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000177 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.072090 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.070042 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 21 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 157333 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 157356 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 184019806820 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184019806820 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2431 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6707 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56131 # Occupied blocks per task id +system.cpu.l2cache.tags.avg_refs 18.629243 # Average number of references to valid blocks. +system.cpu.l2cache.tags.data_accesses 23223720 # Number of data accesses +system.cpu.l2cache.tags.occ_blocks::writebacks 36351.350875 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 12.813342 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000576 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 15263.969553 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.554678 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000196 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.232910 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.787783 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65377 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997574 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.replacements 65515 # number of replacements +system.cpu.l2cache.tags.sampled_refs 130905 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.tag_accesses 23223720 # Number of tag accesses +system.cpu.l2cache.tags.tagsinuse 51628.134347 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2438661 # Total number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2525287108000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks::writebacks 59837 # number of writebacks +system.cpu.l2cache.writebacks::total 59837 # number of writebacks +system.cpu.numCycles 576943440 # number of cpu cycles simulated +system.cpu.numFetchSuspends 77491 # Number of times Execute suspended instruction fetching +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.quiesceCycles 4560354752 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.tickCycles 470746652 # Number of cycles that the CPU actually ticked +system.cpu.toL2Bus.data_through_bus 184089158 # Total data (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3094634 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5780828 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 29817 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 125263 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 9030542 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3400418424 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 2325892574 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2551470440 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer2.occupancy 18491990 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer3.occupancy 72446749 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.snoop_data_through_bus 232512 # Total snoop data (bytes) +system.cpu.toL2Bus.throughput 71784989 # Throughput (bytes/s) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 98965568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84866998 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 45320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 211272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 184089158 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 3214260 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3214259 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 763365 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 763365 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 603000 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2976 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2976 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 247542 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 247542 # Transaction distribution +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.iobus.data_through_bus 123501026 # Total data (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7942 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 524 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2383066 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32660698 # Packet count per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 3976000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 524000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 522000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2374888000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) +system.iobus.respLayer1.occupancy 38216821000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) +system.iobus.throughput 48098087 # Throughput (bytes/s) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1048 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390498 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 123501026 # Cumulative packet size per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 16322171 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322171 # Transaction distribution +system.iobus.trans_dist::WriteReq 8178 # Transaction distribution +system.iobus.trans_dist::WriteResp 8178 # Transaction distribution +system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency +system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1738144017000 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1738144017000 # number of ReadReq MSHR uncacheable cycles +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1738144017000 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1738144017000 # number of overall MSHR uncacheable cycles +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.data_accesses 0 # Number of data accesses +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.tag_accesses 0 # Number of tag accesses +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.membus.data_through_bus 140463478 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383066 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 8 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3800 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893209 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280085 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34557717 # Packet count per connected master and slave (bytes) +system.membus.reqLayer0.occupancy 1731044000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.reqLayer1.occupancy 6000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 3530500 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) +system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer6.occupancy 17560934000 # Layer occupancy (ticks) +system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 4805612001 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer2.occupancy 37417137000 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.5 # Layer utilization (%) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.throughput 54704199 # Throughput (bytes/s) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390498 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 256 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7600 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16954592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19352950 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 140463478 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 16349280 # Transaction distribution +system.membus.trans_dist::ReadResp 16349280 # Transaction distribution +system.membus.trans_dist::WriteReq 763365 # Transaction distribution +system.membus.trans_dist::WriteResp 763365 # Transaction distribution +system.membus.trans_dist::Writeback 59837 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4680 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4680 # Transaction distribution +system.membus.trans_dist::ReadExReq 131615 # Transaction distribution +system.membus.trans_dist::ReadExResp 131615 # Transaction distribution +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgGap 159378.28 # Average gap between requests +system.physmem.avgMemAccLat 44638.69 # Average memory access latency per DRAM burst +system.physmem.avgQLat 25888.69 # Average queueing delay per DRAM burst +system.physmem.avgRdBW 381.23 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.10 # Average system read bandwidth in MiByte/s +system.physmem.avgRdQLen 6.57 # Average read queue length when enqueuing +system.physmem.avgWrBW 2.67 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s +system.physmem.avgWrQLen 25.93 # Average write queue length when enqueuing +system.physmem.busUtil 3.00 # Data bus utilization in percentage +system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.bw_inst_read::cpu.inst 396534 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 396534 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.clcd 47167096 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 523 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 50 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3936408 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51104078 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1491444 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47167096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 523 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 5111032 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53770146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 1491444 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.inst 1174624 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2666068 # Write bandwidth from this memory (bytes/s) +system.physmem.bytesPerActivate::samples 1015061 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 971.117866 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 904.579267 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 205.091565 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22463 2.21% 2.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22781 2.24% 4.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8586 0.85% 5.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2483 0.24% 5.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2672 0.26% 5.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1833 0.18% 5.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8618 0.85% 6.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 926 0.09% 6.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 944699 93.07% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1015061 # Bytes accessed per row activation +system.physmem.bytesReadDRAM 978888704 # Total number of bytes read from DRAM +system.physmem.bytesReadSys 131219480 # Total read bytes from the system interface side +system.physmem.bytesReadWrQ 106752 # Total number of bytes read from write queue +system.physmem.bytesWritten 6855168 # Total number of bytes written to DRAM +system.physmem.bytesWrittenSys 6845640 # Total written bytes from the system interface side +system.physmem.bytes_inst_read::cpu.inst 1018176 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1018176 # Number of instructions bytes read from this memory +system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 10107480 # Number of bytes read from this memory +system.physmem.bytes_read::total 131219480 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 3829568 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.inst 3016072 # Number of bytes written to this memory +system.physmem.bytes_written::total 6845640 # Number of bytes written to this memory +system.physmem.memoryStateTime::IDLE 2210491886500 # Time in different power states +system.physmem.memoryStateTime::REF 85740720000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 271454888500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.mergedWrBursts 706728 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4680 # Number of requests that are neither read nor write +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 157965 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15296804 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59837 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.inst 754018 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813855 # Number of write requests responded to by this memory +system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.perBankRdBursts::0 955934 # Per bank write bursts +system.physmem.perBankRdBursts::1 955610 # Per bank write bursts +system.physmem.perBankRdBursts::2 955719 # Per bank write bursts +system.physmem.perBankRdBursts::3 955960 # Per bank write bursts +system.physmem.perBankRdBursts::4 957705 # Per bank write bursts +system.physmem.perBankRdBursts::5 955718 # Per bank write bursts +system.physmem.perBankRdBursts::6 955569 # Per bank write bursts +system.physmem.perBankRdBursts::7 955478 # Per bank write bursts +system.physmem.perBankRdBursts::8 956345 # Per bank write bursts +system.physmem.perBankRdBursts::9 955973 # Per bank write bursts +system.physmem.perBankRdBursts::10 955562 # Per bank write bursts +system.physmem.perBankRdBursts::11 955146 # Per bank write bursts +system.physmem.perBankRdBursts::12 956303 # Per bank write bursts +system.physmem.perBankRdBursts::13 956034 # Per bank write bursts +system.physmem.perBankRdBursts::14 956157 # Per bank write bursts +system.physmem.perBankRdBursts::15 955923 # Per bank write bursts +system.physmem.perBankWrBursts::0 6634 # Per bank write bursts +system.physmem.perBankWrBursts::1 6445 # Per bank write bursts +system.physmem.perBankWrBursts::2 6533 # Per bank write bursts +system.physmem.perBankWrBursts::3 6602 # Per bank write bursts +system.physmem.perBankWrBursts::4 6504 # Per bank write bursts +system.physmem.perBankWrBursts::5 6748 # Per bank write bursts +system.physmem.perBankWrBursts::6 6784 # Per bank write bursts +system.physmem.perBankWrBursts::7 6699 # Per bank write bursts +system.physmem.perBankWrBursts::8 7075 # Per bank write bursts +system.physmem.perBankWrBursts::9 6807 # Per bank write bursts +system.physmem.perBankWrBursts::10 6488 # Per bank write bursts +system.physmem.perBankWrBursts::11 6148 # Per bank write bursts +system.physmem.perBankWrBursts::12 7101 # Per bank write bursts +system.physmem.perBankWrBursts::13 6684 # Per bank write bursts +system.physmem.perBankWrBursts::14 7006 # Per bank write bursts +system.physmem.perBankWrBursts::15 6854 # Per bank write bursts +system.physmem.rdPerTurnAround::samples 6216 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2460.607465 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 89585.482628 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-262143 6210 99.90% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::786432-1.04858e+06 2 0.03% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.31072e+06-1.57286e+06 1 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2.62144e+06-2.88358e+06 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6.02931e+06-6.29146e+06 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6216 # Reads before turning the bus around for writes +system.physmem.rdQLenPdf::0 1112302 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 958564 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 963836 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1083179 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 974176 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1042396 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2682768 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2583039 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3365419 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 138919 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 118710 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 109585 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 106194 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18426 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 159 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.readBursts 15296804 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 38 # Read request sizes (log2) +system.physmem.readPktSize::3 15138816 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 157950 # Read request sizes (log2) +system.physmem.readReqs 15296804 # Number of read requests accepted +system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads +system.physmem.readRowHits 14297551 # Number of row buffer hits during reads +system.physmem.servicedByWrQ 1668 # Number of DRAM read bursts serviced by the write queue +system.physmem.totBusLat 76475680000 # Total ticks spent in databus transfers +system.physmem.totGap 2567689117500 # Total gap between requests +system.physmem.totMemAccLat 682754832250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 395971032250 # Total ticks spent queuing +system.physmem.wrPerTurnAround::samples 6216 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.231660 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.203648 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.973536 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2382 38.32% 38.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 22 0.35% 38.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3802 61.16% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 10 0.16% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6216 # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.writeBursts 813855 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 754018 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 59837 # Write request sizes (log2) +system.physmem.writeReqs 813855 # Number of write requests accepted +system.physmem.writeRowHitRate 83.67 # Row buffer hit rate for writes +system.physmem.writeRowHits 89636 # Number of row buffer hits during writes +system.realview.nvmem.bw_inst_read::cpu.inst 100 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 100 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu.inst 100 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 100 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 100 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 100 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_inst_read::cpu.inst 256 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 256 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_read::cpu.inst 256 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 256 # Number of bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 4 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 4 # Number of read requests responded to by this memory +system.voltage_domain.voltage 1 # Voltage in Volts + +---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/system.terminal Binary files differnew file mode 100644 index 000000000..7aa71fcbc --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/system.terminal |